1 /* -*- linux-c -*- */ 2 /* 3 * Copyright (C) 2001 By Joachim Martillo, Telford Tools, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 **/ 11 12 #ifndef _8253XMCS_H_ 13 #define _8253XMCS_H_ 14 15 #include "8253xctl.h" 16 17 /* structures for the multi channel server, the host card, GLINK and 18 * extensions cards. This system uses the AMCC S5920 instead of the 19 * PLX 9050 */ 20 21 /* ------------------------------------------------------------------------- */ 22 /* Useful macros */ 23 24 /* 25 * NOTICE: pciat_identify: pci125c,102 unit 1 26 * NOTICE: pciat_probe: pci125c,102 unit 1 27 * NOTICE: pciat_attach: pci125c,102 instance 1 28 * NOTICE: Reg End Size Pointer AccHandle 29 * NOTICE: 0 -- 00000000 5093a000 5033f160 30 * NOTICE: 0 be 00000000 5093c000 5033f128 31 * NOTICE: 0 le 00000000 50940000 5033f0f0 32 * NOTICE: 1 -- 00000080 50942000 5033f0b8 33 * NOTICE: 1 be 00000080 50944000 5033f080 34 * NOTICE: 1 le 00000080 50946000 5033f048 35 * NOTICE: 2 -- 00004000 50948000 5033f010 36 * NOTICE: 2 be 00004000 5094c000 5033efd8 37 * NOTICE: 2 le 00004000 50950000 5033efa0 38 * NOTICE: 3 -- 00008000 50954000 5033ef68 39 * NOTICE: 3 be 00008000 5095c000 5033ef30 40 * NOTICE: 3 le 00008000 50964000 5033eef8 41 * NOTICE: 4 -- 00000800 5096c000 5033eec0 42 * NOTICE: 4 be 00000800 5096e000 5033ee88 43 * NOTICE: 4 le 00000800 50970000 5033ee50 44 * NOTICE: pciat_attach: pci125c,102 1: PCI reg property 45 * NOTICE: Idx Bus Dev Fun Reg Spc Addr Size 46 * NOTICE: 0 000 004 000 000 CFG 00000000 00000000 00000000 00000000 47 * NOTICE: 1 000 004 000 010 MEM 00000000 00000000 00000000 00000080 48 * NOTICE: 2 000 004 000 014 MEM 00000000 00000000 00000000 00004000 49 * NOTICE: 3 000 004 000 018 MEM 00000000 00000000 00000000 00008000 50 * NOTICE: 4 000 004 000 01c MEM 00000000 00000000 00000000 00000800 51 * PCI-device: pci125c,102@4, pciat #1 52 */ 53 54 /* 55 * Serial EPROM information: 56 * 57 * + chip speed grade [ one byte ] 58 * + chip oscillator speed [ 4 bytes ] 59 * + board revision [ ascii string ] 60 * + date of manufacture [ ascii string ] 61 * + location of manufacture [ ascii string ] 62 * + serial number [ ascii string ] 63 * + prototype/production flag [ one bit ] 64 * + sync/async license [ one bit ] 65 * + CIM type [ one byte ] 66 * + assembly house [ ascii string ] 67 */ 68 69 /* 70 * Serial EPROM map. 71 */ 72 73 #define MCS_SEP_TYPE 0x00 74 #define MCS_SEP_FLAGS 0x01 75 #define MCS_SEP_SPDGRD 0x02 76 #define MCS_SEP_MAGIC 0x03 77 #define MCS_SEP_CLKSPD 0x04 78 #define MCS_SEP_SN 0x10 79 #define MCS_SEP_SNLEN 0x10 80 #define MCS_SEP_REV 0x20 81 #define MCS_SEP_REVLEN 0x10 82 #define MCS_SEP_MFGLOC 0x30 83 #define MCS_SEP_MFGLOCLEN 0x10 84 #define MCS_SEP_MFGDATE 0x40 85 #define MCS_SEP_MFGDATELEN 0x20 86 87 #define MCS_SEP_MAGICVAL 0x65 88 89 /* Host NVRAM DEFINES */ 90 91 #define AMCC_NVR_VENDEVID 0x10 /* offset in 32bit quantities */ 92 93 /* 94 * PCI spaces on the CIM. 95 */ 96 #if 0 /* Solaris driver stuff */ 97 #define AMCC_REG 1 98 #define CIMCMD_REG 2 99 #define MICCMD_REG 3 100 #define FIFOCACHE_REG 4 101 #else 102 #define AMCC_REG virtbaseaddress0 /* bridge */ 103 #define CIMCMD_REG virtbaseaddress1 104 #define MICCMD_REG virtbaseaddress2 105 #define FIFOCACHE_REG virtbaseaddress3 106 #endif 107 108 /* 109 * AMCC registers: 110 */ 111 112 #define AMCC_OMB 0x0c /* 4 bytes */ 113 #define AMCC_IMB 0x1c /* 4 bytes */ 114 #define AMCC_MBEF 0x34 /* 4 bytes */ 115 #define AMCC_INTCSR 0x38 /* 4 bytes */ 116 #define AMCC_INTASSERT 0x00800000 /* RO */ 117 #define AMCC_AOINTPIN 0x00400000 /* RO */ 118 #define AMCC_IMINT 0x00020000 /* R/WC */ 119 #define AMCC_OMINT 0x00010000 /* R/WC */ 120 #define AMCC_AOINTPINENA 0x00002000 /* R/W */ 121 #define AMCC_RCR 0x3c /* 4 bytes */ 122 #define AMCC_NVRACCCTRLMASK 0xe0000000 /* nvRAM Acc. Ctrl */ 123 #define AMCC_NVRACCFAIL 0x10000000 /* RO */ 124 #define AMCC_NVRBUSY 0x80000000 125 #define AMCC_NVRWRLA 0x80000000 126 #define AMCC_NVRWRHA 0xa0000000 127 #define AMCC_NVRRDDB 0xe0000000 128 #define AMCC_NVROPPMASK 0x000f0000 /* R/W */ 129 #define AMCC_MBXFLGRESET 0x08000000 /* WO */ 130 #define AMCC_RDFIFORESET 0x02000000 /* WO */ 131 #define AMCC_AORESET 0x01000000 /* R/W */ 132 #define AMCC_PTCR 0x60 /* 4 bytes */ 133 #define AMCC_AMWTSTATEMASK 0x07 134 #define AMCC_PREFETCHMASK 0x18 135 #define AMCC_WRFIFODIS 0x20 136 #define AMCC_ENDCONV 0x40 137 #define AMCC_PTMODE 0x80 138 139 #define AMCC_SIZE 0x80 /* space size, in bytes */ 140 #define AMCC_NVRAM_SIZE 0x40 /* in shorts just to be consistent with 141 * other eprom and nvram sizes*/ 142 143 /* 144 * CIM Command space 0x0000 - 0x3fff 145 */ 146 147 #define CIMCMD_CHANSHIFT 6 /* shift channel# to the left */ 148 #define CIMCMD_CHANMASK 0x3f /* 6 bits of mask */ 149 #define CIMCMD_CIMSHIFT 10 /* shift cim# to the left */ 150 #define CIMCMD_CIMMASK 0x3 /* 2 bits of mask */ 151 #define CIMCMD_CTRLSHIFT 1 /* shift control address to the left */ 152 #define CIMCMD_CTRLMASK 0x7 /* 3 bits of mask */ 153 #define CIMCMD_CHIPSHIFT 9 154 155 #define CIMCMD_RESET 0x0000 156 #define CIMCMD_RDINT 0x0002 157 #define CIMCMD_RDINT_ESCCMASK 0x00ff 158 #define CIMCMD_WRINT 0x0003 159 #define CIMCMD_WRINTENA 0x0004 160 #define CIMCMD_WRINTDIS 0x0006 161 #define CIMCMD_RESETENA 0x0007 /* assert reset */ 162 #define CIMCMD_RESETDIS 0x0000 /* deassert the reset */ 163 #define CIMCMD_RDFIFOW 0x1000 /* add channel# */ 164 #define CIMCMD_WRFIFOB 0x2002 /* add channel# */ 165 #define CIMCMD_WRFIFOW 0x2000 /* add channel# */ 166 #define CIMCMD_RDREGB 0x1000 /* add channel# and reg# (>= 0x20) */ 167 #define CIMCMD_WRREGB 0x2000 /* add channel# and reg# (>= 0x20) */ 168 #define CIMCMD_RDSETUP 0x3200 /* add cim# and address (word acc) */ 169 #define CIMCMD_WRSETUP 0x3220 /* add cim# and address (word acc) */ 170 #define CIMCMD_RDCIMCSR 0x3000 /* add cim# */ 171 #define CIMCMD_CIMCSR_LED 0x01 172 #define CIMCMD_CIMCSR_SWI 0x02 173 #define CIMCMD_CIMCSR_SDA 0x04 174 #define CIMCMD_CIMCSR_SCL 0x08 175 #define CIMCMD_CIMCSR_TESTMASK 0xc0 176 #define CIMCMD_WRCIMCSR 0x3020 /* add cim# */ 177 178 #define CIMCMD_SIZE 0x4000 /* space size, in bytes */ 179 180 /* 181 * MIC Command space 0x0000 - 0x5fc0 182 */ 183 184 #define MICCMD_CHANSHIFT 6 /* shift channel# to the left */ 185 #define MICCMD_CHANMASK 0x3f /* 6 bits of mask */ 186 187 #define MICCMD_MICCSR 0x0000 /* R/W (byte) */ 188 #define MICCMD_MICCSR_END 0x80 189 #define MICCMD_MICCSR_ENL 0x40 190 #define MICCMD_MICCSR_LPN 0x20 191 #define MICCMD_MICCSR_DGM 0x10 192 #define MICCMD_MICCSR_CPY 0x08 193 #define MICCMD_MICCSR_GLE 0x04 194 #define MICCMD_MICCSR_RXE 0x02 195 #define MICCMD_MICCSR_IRQ 0x01 196 #define MICCMD_REV 0x0001 /* RO (byte) */ 197 #define MICCMD_CACHETRIG 0x5000 /* WO (byte: #words-1) add channel# */ 198 199 #define MICCMD_SIZE 0x8000 /* space size, in bytes */ 200 201 /* 202 * FIFO Cache space 0x000 - 0x7ff 203 */ 204 205 #define FIFOCACHE_CHANSHIFT 5 /* shift channel# to the left */ 206 #define FIFOCACHE_CHANMASK 0x3f /* 6 bits of mask */ 207 208 #define FIFOCACHE_FIFOCACHE 0x000 /* add channel# and word offset */ 209 210 #define FIFOCACHE_SIZE 0x800 /* space size, in bytes */ 211 212 /* 213 * Other miscellaneous constants 214 */ 215 216 #define MAX_NCIMS 4 /* maximum of 4 CIMS */ 217 #define CIM_NPORTS 16 /* 16 ports per CIM */ 218 #define CIM_NCHIPS 2 /* 2 ESCC8s/CIM */ 219 #define CHIP_NPORTS 8 /* 8 ports per chip */ 220 221 #define WANMCS_CLKSPEED 7372800 /* 7.3728 MHz */ 222 223 224 /* PCR/PVR (Universal Port) */ 225 226 /* 227 * To summarize the use of the parallel port: 228 * RS-232 229 * Parallel port A -- TxClkdir control (output) ports 0 - 7 230 * Parallel port B -- DTR (output) ports 0 - 7 231 * Parallel port C -- DSR (input) ports 0 - 7 232 * Parallel port D -- unused 233 */ 234 235 #define WANMCS_PCRAVAL 0x00 /* all output bits */ 236 #define WANMCS_PCRBVAL 0x00 /* all output bits */ 237 #define WANMCS_PCRCVAL 0xff /* all input bits */ 238 #define WANMCS_PCRDVAL 0x0f /* 4 input bits */ 239 240 #define WANMCS_PIMAVAL 0xff /* all interrupts off */ 241 #define WANMCS_PIMBVAL 0xff /* all interrupts off */ 242 #define WANMCS_PIMCVAL 0xff /* all interrupts off */ 243 #define WANMCS_PIMDVAL 0x0f /* all interrupts off */ 244 245 #define WANMCS_PVRAVAL 0xff /* all high */ 246 #define WANMCS_PVRBVAL 0xff /* all high */ 247 248 #define ANY_BITS_ARE_ON(x, b) (((x) & (b)) != 0) 249 #define ANY_BITS_ARE_OFF(x, b) ((((x) & (b)) ^ (b)) != 0) 250 #define ALL_BITS_ARE_ON(x, b) ((((x) & (b)) ^ (b)) == 0) 251 252 /* ------------------------------------------------------------------------- */ 253 /* New types and type specific macros */ 254 255 typedef struct _mcs_sep 256 { 257 #if 0 258 ddi_acc_handle_t s_handle; /* something from Solaris */ 259 #endif 260 unsigned char *s_rdptr; 261 unsigned char *s_wrptr; 262 unsigned int s_scl; 263 unsigned int s_sda; 264 } mcs_sep_t; 265 266 /* 267 * Per-line private information for wanmcs. 268 */ 269 270 typedef struct _wanmcspriv 271 { 272 unsigned char r_chipunit; /* [0, 1] or [0, 7] */ 273 274 /* these items are for accessing the ESCCx registers as bytes */ 275 #if 0 276 ddi_acc_handle_t r_reghandle; /* handle for access to ESCCx regs */ 277 #endif 278 unsigned char *r_rdregbase; /* base for reading ESCCx registers */ 279 unsigned char *r_wrregbase; /* base for writing ESCCx registers */ 280 281 /* these items are for accessing the ESCCx FIFOs as bytes and words */ 282 #if 0 283 ddi_acc_handle_t r_fifohandle; 284 #endif 285 unsigned short *r_rdfifow; /* read FIFO word */ 286 unsigned char *r_wrfifob; /* write FIFO byte */ 287 unsigned short *r_wrfifow; /* write FIFO word */ 288 289 /* these items are for accessing the MIC command space */ 290 #if 0 291 ddi_acc_handle_t r_miccmdhandle; 292 #endif 293 unsigned char *r_wrcachetrig; /* the FIFO cache trigger */ 294 295 /* these itmes are for accessing the FIFO cache space */ 296 #if 0 297 ddi_acc_handle_t r_fifocachehandle; 298 #endif 299 unsigned short *r_fifocachebase; 300 } wanmcspriv_t; 301 302 #define AMCC_INT_OFF 0 303 304 extern unsigned int 305 amcc_read_nvram(unsigned char* buffer, 306 unsigned length, 307 unsigned char *bridge_space); 308 309 extern unsigned int mcs_ciminit(SAB_BOARD *bptr, AURA_CIM *cim); 310 311 extern int wanmcs_reset(SAB_BOARD* bptr); 312 313 #endif 314