1 /* ----------------------------------------------------------------------------
2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9 Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License.
14
15 Ported to Linux 1.3.* network driver environment by
16 Matti Aarnio <mea@utu.fi>
17
18 References
19
20 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
21 Am79C940 (MACE) Data Sheet, 1994
22 Am79C90 (C-LANCE) Data Sheet, 1994
23 Linux PCMCIA Programmer's Guide v1.17
24 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
25
26 Eric Mears, New Media Corporation
27 Tom Pollard, New Media Corporation
28 Dean Siasoyco, New Media Corporation
29 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
30 Donald Becker <becker@scyld.com>
31 David Hinds <dahinds@users.sourceforge.net>
32
33 The Linux client driver is based on the 3c589_cs.c client driver by
34 David Hinds.
35
36 The Linux network driver outline is based on the 3c589_cs.c driver,
37 the 8390.c driver, and the example skeleton.c kernel code, which are
38 by Donald Becker.
39
40 The Am2150 network driver hardware interface code is based on the
41 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
42
43 Special thanks for testing and help in debugging this driver goes
44 to Ken Lesniak.
45
46 -------------------------------------------------------------------------------
47 Driver Notes and Issues
48 -------------------------------------------------------------------------------
49
50 1. Developed on a Dell 320SLi
51 PCMCIA Card Services 2.6.2
52 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
53
54 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
55 'insmod pcmcia_core.o io_speed=300'.
56 This will avoid problems with fast systems which causes rx_framecnt
57 to return random values.
58
59 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
60 before extraction.
61
62 4. There is a bad slow-down problem in this driver.
63
64 5. Future: Multicast processing. In the meantime, do _not_ compile your
65 kernel with multicast ip enabled.
66
67 -------------------------------------------------------------------------------
68 History
69 -------------------------------------------------------------------------------
70 Log: nmclan_cs.c,v
71 * Revision 0.16 1995/07/01 06:42:17 rpao
72 * Bug fix: nmclan_reset() called CardServices incorrectly.
73 *
74 * Revision 0.15 1995/05/24 08:09:47 rpao
75 * Re-implement MULTI_TX dev->tbusy handling.
76 *
77 * Revision 0.14 1995/05/23 03:19:30 rpao
78 * Added, in nmclan_config(), "tuple.Attributes = 0;".
79 * Modified MACE ID check to ignore chip revision level.
80 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
81 *
82 * Revision 0.13 1995/05/18 05:56:34 rpao
83 * Statistics changes.
84 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
85 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
86 *
87 * Revision 0.12 1995/05/14 00:12:23 rpao
88 * Statistics overhaul.
89 *
90
91 95/05/13 rpao V0.10a
92 Bug fix: MACE statistics counters used wrong I/O ports.
93 Bug fix: mace_interrupt() needed to allow statistics to be
94 processed without RX or TX interrupts pending.
95 95/05/11 rpao V0.10
96 Multiple transmit request processing.
97 Modified statistics to use MACE counters where possible.
98 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
99 *Released
100 95/05/10 rpao V0.08
101 Bug fix: Make all non-exported functions private by using
102 static keyword.
103 Bug fix: Test IntrCnt _before_ reading MACE_IR.
104 95/05/10 rpao V0.07 Statistics.
105 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
106
107 ---------------------------------------------------------------------------- */
108
109 #define DRV_NAME "nmclan_cs"
110 #define DRV_VERSION "0.16"
111
112
113 /* ----------------------------------------------------------------------------
114 Conditional Compilation Options
115 ---------------------------------------------------------------------------- */
116
117 #define MULTI_TX 0
118 #define RESET_ON_TIMEOUT 1
119 #define TX_INTERRUPTABLE 1
120 #define RESET_XILINX 0
121
122 /* ----------------------------------------------------------------------------
123 Include Files
124 ---------------------------------------------------------------------------- */
125
126 #include <linux/module.h>
127 #include <linux/kernel.h>
128 #include <linux/init.h>
129 #include <linux/sched.h>
130 #include <linux/ptrace.h>
131 #include <linux/slab.h>
132 #include <linux/string.h>
133 #include <linux/timer.h>
134 #include <linux/interrupt.h>
135 #include <linux/in.h>
136 #include <linux/delay.h>
137 #include <linux/ethtool.h>
138
139 #include <asm/uaccess.h>
140 #include <asm/io.h>
141 #include <asm/system.h>
142 #include <asm/bitops.h>
143
144 #include <linux/netdevice.h>
145 #include <linux/etherdevice.h>
146 #include <linux/skbuff.h>
147 #include <linux/if_arp.h>
148 #include <linux/ioport.h>
149
150 #include <pcmcia/version.h>
151 #include <pcmcia/cs_types.h>
152 #include <pcmcia/cs.h>
153 #include <pcmcia/cisreg.h>
154 #include <pcmcia/cistpl.h>
155 #include <pcmcia/ds.h>
156
157 /* ----------------------------------------------------------------------------
158 Defines
159 ---------------------------------------------------------------------------- */
160
161 #define ETHER_ADDR_LEN ETH_ALEN
162 /* 6 bytes in an Ethernet Address */
163 #define MACE_LADRF_LEN 8
164 /* 8 bytes in Logical Address Filter */
165
166 /* Loop Control Defines */
167 #define MACE_MAX_IR_ITERATIONS 10
168 #define MACE_MAX_RX_ITERATIONS 12
169 /*
170 TBD: Dean brought this up, and I assumed the hardware would
171 handle it:
172
173 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
174 non-zero when the isr exits. We may not get another interrupt
175 to process the remaining packets for some time.
176 */
177
178 /*
179 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
180 which manages the interface between the MACE and the PCMCIA bus. It
181 also includes buffer management for the 32K x 8 SRAM to control up to
182 four transmit and 12 receive frames at a time.
183 */
184 #define AM2150_MAX_TX_FRAMES 4
185 #define AM2150_MAX_RX_FRAMES 12
186
187 /* Am2150 Ethernet Card I/O Mapping */
188 #define AM2150_RCV 0x00
189 #define AM2150_XMT 0x04
190 #define AM2150_XMT_SKIP 0x09
191 #define AM2150_RCV_NEXT 0x0A
192 #define AM2150_RCV_FRAME_COUNT 0x0B
193 #define AM2150_MACE_BANK 0x0C
194 #define AM2150_MACE_BASE 0x10
195
196 /* MACE Registers */
197 #define MACE_RCVFIFO 0
198 #define MACE_XMTFIFO 1
199 #define MACE_XMTFC 2
200 #define MACE_XMTFS 3
201 #define MACE_XMTRC 4
202 #define MACE_RCVFC 5
203 #define MACE_RCVFS 6
204 #define MACE_FIFOFC 7
205 #define MACE_IR 8
206 #define MACE_IMR 9
207 #define MACE_PR 10
208 #define MACE_BIUCC 11
209 #define MACE_FIFOCC 12
210 #define MACE_MACCC 13
211 #define MACE_PLSCC 14
212 #define MACE_PHYCC 15
213 #define MACE_CHIPIDL 16
214 #define MACE_CHIPIDH 17
215 #define MACE_IAC 18
216 /* Reserved */
217 #define MACE_LADRF 20
218 #define MACE_PADR 21
219 /* Reserved */
220 /* Reserved */
221 #define MACE_MPC 24
222 /* Reserved */
223 #define MACE_RNTPC 26
224 #define MACE_RCVCC 27
225 /* Reserved */
226 #define MACE_UTR 29
227 #define MACE_RTR1 30
228 #define MACE_RTR2 31
229
230 /* MACE Bit Masks */
231 #define MACE_XMTRC_EXDEF 0x80
232 #define MACE_XMTRC_XMTRC 0x0F
233
234 #define MACE_XMTFS_XMTSV 0x80
235 #define MACE_XMTFS_UFLO 0x40
236 #define MACE_XMTFS_LCOL 0x20
237 #define MACE_XMTFS_MORE 0x10
238 #define MACE_XMTFS_ONE 0x08
239 #define MACE_XMTFS_DEFER 0x04
240 #define MACE_XMTFS_LCAR 0x02
241 #define MACE_XMTFS_RTRY 0x01
242
243 #define MACE_RCVFS_RCVSTS 0xF000
244 #define MACE_RCVFS_OFLO 0x8000
245 #define MACE_RCVFS_CLSN 0x4000
246 #define MACE_RCVFS_FRAM 0x2000
247 #define MACE_RCVFS_FCS 0x1000
248
249 #define MACE_FIFOFC_RCVFC 0xF0
250 #define MACE_FIFOFC_XMTFC 0x0F
251
252 #define MACE_IR_JAB 0x80
253 #define MACE_IR_BABL 0x40
254 #define MACE_IR_CERR 0x20
255 #define MACE_IR_RCVCCO 0x10
256 #define MACE_IR_RNTPCO 0x08
257 #define MACE_IR_MPCO 0x04
258 #define MACE_IR_RCVINT 0x02
259 #define MACE_IR_XMTINT 0x01
260
261 #define MACE_MACCC_PROM 0x80
262 #define MACE_MACCC_DXMT2PD 0x40
263 #define MACE_MACCC_EMBA 0x20
264 #define MACE_MACCC_RESERVED 0x10
265 #define MACE_MACCC_DRCVPA 0x08
266 #define MACE_MACCC_DRCVBC 0x04
267 #define MACE_MACCC_ENXMT 0x02
268 #define MACE_MACCC_ENRCV 0x01
269
270 #define MACE_PHYCC_LNKFL 0x80
271 #define MACE_PHYCC_DLNKTST 0x40
272 #define MACE_PHYCC_REVPOL 0x20
273 #define MACE_PHYCC_DAPC 0x10
274 #define MACE_PHYCC_LRT 0x08
275 #define MACE_PHYCC_ASEL 0x04
276 #define MACE_PHYCC_RWAKE 0x02
277 #define MACE_PHYCC_AWAKE 0x01
278
279 #define MACE_IAC_ADDRCHG 0x80
280 #define MACE_IAC_PHYADDR 0x04
281 #define MACE_IAC_LOGADDR 0x02
282
283 #define MACE_UTR_RTRE 0x80
284 #define MACE_UTR_RTRD 0x40
285 #define MACE_UTR_RPA 0x20
286 #define MACE_UTR_FCOLL 0x10
287 #define MACE_UTR_RCVFCSE 0x08
288 #define MACE_UTR_LOOP_INCL_MENDEC 0x06
289 #define MACE_UTR_LOOP_NO_MENDEC 0x04
290 #define MACE_UTR_LOOP_EXTERNAL 0x02
291 #define MACE_UTR_LOOP_NONE 0x00
292 #define MACE_UTR_RESERVED 0x01
293
294 /* Switch MACE register bank (only 0 and 1 are valid) */
295 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
296
297 #define MACE_IMR_DEFAULT \
298 (0xFF - \
299 ( \
300 MACE_IR_CERR | \
301 MACE_IR_RCVCCO | \
302 MACE_IR_RNTPCO | \
303 MACE_IR_MPCO | \
304 MACE_IR_RCVINT | \
305 MACE_IR_XMTINT \
306 ) \
307 )
308 #undef MACE_IMR_DEFAULT
309 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
310
311 #define TX_TIMEOUT ((400*HZ)/1000)
312
313 /* ----------------------------------------------------------------------------
314 Type Definitions
315 ---------------------------------------------------------------------------- */
316
317 typedef struct _mace_statistics {
318 /* MACE_XMTFS */
319 int xmtsv;
320 int uflo;
321 int lcol;
322 int more;
323 int one;
324 int defer;
325 int lcar;
326 int rtry;
327
328 /* MACE_XMTRC */
329 int exdef;
330 int xmtrc;
331
332 /* RFS1--Receive Status (RCVSTS) */
333 int oflo;
334 int clsn;
335 int fram;
336 int fcs;
337
338 /* RFS2--Runt Packet Count (RNTPC) */
339 int rfs_rntpc;
340
341 /* RFS3--Receive Collision Count (RCVCC) */
342 int rfs_rcvcc;
343
344 /* MACE_IR */
345 int jab;
346 int babl;
347 int cerr;
348 int rcvcco;
349 int rntpco;
350 int mpco;
351
352 /* MACE_MPC */
353 int mpc;
354
355 /* MACE_RNTPC */
356 int rntpc;
357
358 /* MACE_RCVCC */
359 int rcvcc;
360 } mace_statistics;
361
362 typedef struct _mace_private {
363 dev_link_t link;
364 struct net_device dev;
365 dev_node_t node;
366 struct net_device_stats linux_stats; /* Linux statistics counters */
367 mace_statistics mace_stats; /* MACE chip statistics counters */
368
369 /* restore_multicast_list() state variables */
370 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
371 int multicast_num_addrs;
372
373 char tx_free_frames; /* Number of free transmit frame buffers */
374 char tx_irq_disabled; /* MACE TX interrupt disabled */
375 } mace_private;
376
377 /* ----------------------------------------------------------------------------
378 Private Global Variables
379 ---------------------------------------------------------------------------- */
380
381 #ifdef PCMCIA_DEBUG
382 static char rcsid[] =
383 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
384 static char *version =
385 DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
386 #endif
387
388 static dev_info_t dev_info="nmclan_cs";
389 static dev_link_t *dev_list;
390
391 static char *if_names[]={
392 "Auto", "10baseT", "BNC",
393 };
394
395 /* ----------------------------------------------------------------------------
396 Parameters
397 These are the parameters that can be set during loading with
398 'insmod'.
399 ---------------------------------------------------------------------------- */
400
401 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
402 MODULE_LICENSE("GPL");
403
404 #define INT_MODULE_PARM(n, v) static int n = v; MODULE_PARM(n, "i")
405
406 static int irq_list[4] = { -1 };
407 MODULE_PARM(irq_list, "1-4i");
408
409 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
410 INT_MODULE_PARM(if_port, 0);
411 /* Bit map of interrupts to choose from */
412 INT_MODULE_PARM(irq_mask, 0xdeb8);
413
414 #ifdef PCMCIA_DEBUG
415 INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
416 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
417 #else
418 #define DEBUG(n, args...)
419 #endif
420
421 /* ----------------------------------------------------------------------------
422 Function Prototypes
423 ---------------------------------------------------------------------------- */
424
425 static void nmclan_config(dev_link_t *link);
426 static void nmclan_release(u_long arg);
427 static int nmclan_event(event_t event, int priority,
428 event_callback_args_t *args);
429
430 static void nmclan_reset(struct net_device *dev);
431 static int mace_config(struct net_device *dev, struct ifmap *map);
432 static int mace_open(struct net_device *dev);
433 static int mace_close(struct net_device *dev);
434 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
435 static void mace_tx_timeout(struct net_device *dev);
436 static void mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
437 static struct net_device_stats *mace_get_stats(struct net_device *dev);
438 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
439 static void restore_multicast_list(struct net_device *dev);
440 static void set_multicast_list(struct net_device *dev);
441 static struct ethtool_ops netdev_ethtool_ops;
442
443
444 static dev_link_t *nmclan_attach(void);
445 static void nmclan_detach(dev_link_t *);
446
447 /* ----------------------------------------------------------------------------
448 flush_stale_links
449 Clean up stale device structures
450 ---------------------------------------------------------------------------- */
451
flush_stale_links(void)452 static void flush_stale_links(void)
453 {
454 dev_link_t *link, *next;
455 for (link = dev_list; link; link = next) {
456 next = link->next;
457 if (link->state & DEV_STALE_LINK)
458 nmclan_detach(link);
459 }
460 }
461
462 /* ----------------------------------------------------------------------------
463 cs_error
464 Report a Card Services related error.
465 ---------------------------------------------------------------------------- */
466
cs_error(client_handle_t handle,int func,int ret)467 static void cs_error(client_handle_t handle, int func, int ret)
468 {
469 error_info_t err = { func, ret };
470 CardServices(ReportError, handle, &err);
471 }
472
473 /* ----------------------------------------------------------------------------
474 nmclan_attach
475 Creates an "instance" of the driver, allocating local data
476 structures for one device. The device is registered with Card
477 Services.
478 ---------------------------------------------------------------------------- */
479
nmclan_attach(void)480 static dev_link_t *nmclan_attach(void)
481 {
482 mace_private *lp;
483 dev_link_t *link;
484 struct net_device *dev;
485 client_reg_t client_reg;
486 int i, ret;
487
488 DEBUG(0, "nmclan_attach()\n");
489 DEBUG(1, "%s\n", rcsid);
490 flush_stale_links();
491
492 /* Create new ethernet device */
493 lp = kmalloc(sizeof(*lp), GFP_KERNEL);
494 if (!lp) return NULL;
495 memset(lp, 0, sizeof(*lp));
496 link = &lp->link; dev = &lp->dev;
497 link->priv = dev->priv = link->irq.Instance = lp;
498
499 link->release.function = &nmclan_release;
500 link->release.data = (u_long)link;
501 link->io.NumPorts1 = 32;
502 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
503 link->io.IOAddrLines = 5;
504 link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
505 link->irq.IRQInfo1 = IRQ_INFO2_VALID|IRQ_LEVEL_ID;
506 if (irq_list[0] == -1)
507 link->irq.IRQInfo2 = irq_mask;
508 else
509 for (i = 0; i < 4; i++)
510 link->irq.IRQInfo2 |= 1 << irq_list[i];
511 link->irq.Handler = &mace_interrupt;
512 link->conf.Attributes = CONF_ENABLE_IRQ;
513 link->conf.Vcc = 50;
514 link->conf.IntType = INT_MEMORY_AND_IO;
515 link->conf.ConfigIndex = 1;
516 link->conf.Present = PRESENT_OPTION;
517
518 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
519
520 dev->hard_start_xmit = &mace_start_xmit;
521 dev->set_config = &mace_config;
522 dev->get_stats = &mace_get_stats;
523 dev->set_multicast_list = &set_multicast_list;
524 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
525 ether_setup(dev);
526 dev->open = &mace_open;
527 dev->stop = &mace_close;
528 #ifdef HAVE_TX_TIMEOUT
529 dev->tx_timeout = mace_tx_timeout;
530 dev->watchdog_timeo = TX_TIMEOUT;
531 #endif
532
533 /* Register with Card Services */
534 link->next = dev_list;
535 dev_list = link;
536 client_reg.dev_info = &dev_info;
537 client_reg.Attributes = INFO_IO_CLIENT | INFO_CARD_SHARE;
538 client_reg.EventMask =
539 CS_EVENT_CARD_INSERTION | CS_EVENT_CARD_REMOVAL |
540 CS_EVENT_RESET_PHYSICAL | CS_EVENT_CARD_RESET |
541 CS_EVENT_PM_SUSPEND | CS_EVENT_PM_RESUME;
542 client_reg.event_handler = &nmclan_event;
543 client_reg.Version = 0x0210;
544 client_reg.event_callback_args.client_data = link;
545 ret = CardServices(RegisterClient, &link->handle, &client_reg);
546 if (ret != 0) {
547 cs_error(link->handle, RegisterClient, ret);
548 nmclan_detach(link);
549 return NULL;
550 }
551
552 return link;
553 } /* nmclan_attach */
554
555 /* ----------------------------------------------------------------------------
556 nmclan_detach
557 This deletes a driver "instance". The device is de-registered
558 with Card Services. If it has been released, all local data
559 structures are freed. Otherwise, the structures will be freed
560 when the device is released.
561 ---------------------------------------------------------------------------- */
562
nmclan_detach(dev_link_t * link)563 static void nmclan_detach(dev_link_t *link)
564 {
565 mace_private *lp = link->priv;
566 dev_link_t **linkp;
567
568 DEBUG(0, "nmclan_detach(0x%p)\n", link);
569
570 /* Locate device structure */
571 for (linkp = &dev_list; *linkp; linkp = &(*linkp)->next)
572 if (*linkp == link) break;
573 if (*linkp == NULL)
574 return;
575
576 del_timer(&link->release);
577 if (link->state & DEV_CONFIG) {
578 nmclan_release((u_long)link);
579 if (link->state & DEV_STALE_CONFIG) {
580 link->state |= DEV_STALE_LINK;
581 return;
582 }
583 }
584
585 if (link->handle)
586 CardServices(DeregisterClient, link->handle);
587
588 /* Unlink device structure, free bits */
589 *linkp = link->next;
590 if (link->dev)
591 unregister_netdev(&lp->dev);
592 kfree(lp);
593
594 } /* nmclan_detach */
595
596 /* ----------------------------------------------------------------------------
597 mace_read
598 Reads a MACE register. This is bank independent; however, the
599 caller must ensure that this call is not interruptable. We are
600 assuming that during normal operation, the MACE is always in
601 bank 0.
602 ---------------------------------------------------------------------------- */
mace_read(ioaddr_t ioaddr,int reg)603 static int mace_read(ioaddr_t ioaddr, int reg)
604 {
605 int data = 0xFF;
606 unsigned long flags;
607
608 switch (reg >> 4) {
609 case 0: /* register 0-15 */
610 data = inb(ioaddr + AM2150_MACE_BASE + reg);
611 break;
612 case 1: /* register 16-31 */
613 save_flags(flags);
614 cli();
615 MACEBANK(1);
616 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
617 MACEBANK(0);
618 restore_flags(flags);
619 break;
620 }
621 return (data & 0xFF);
622 } /* mace_read */
623
624 /* ----------------------------------------------------------------------------
625 mace_write
626 Writes to a MACE register. This is bank independent; however,
627 the caller must ensure that this call is not interruptable. We
628 are assuming that during normal operation, the MACE is always in
629 bank 0.
630 ---------------------------------------------------------------------------- */
mace_write(ioaddr_t ioaddr,int reg,int data)631 static void mace_write(ioaddr_t ioaddr, int reg, int data)
632 {
633 unsigned long flags;
634
635 switch (reg >> 4) {
636 case 0: /* register 0-15 */
637 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
638 break;
639 case 1: /* register 16-31 */
640 save_flags(flags);
641 cli();
642 MACEBANK(1);
643 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
644 MACEBANK(0);
645 restore_flags(flags);
646 break;
647 }
648 } /* mace_write */
649
650 /* ----------------------------------------------------------------------------
651 mace_init
652 Resets the MACE chip.
653 ---------------------------------------------------------------------------- */
mace_init(ioaddr_t ioaddr,char * enet_addr)654 static void mace_init(ioaddr_t ioaddr, char *enet_addr)
655 {
656 int i;
657
658 /* MACE Software reset */
659 mace_write(ioaddr, MACE_BIUCC, 1);
660 while (mace_read(ioaddr, MACE_BIUCC) & 0x01) {
661 /* Wait for reset bit to be cleared automatically after <= 200ns */;
662 }
663 mace_write(ioaddr, MACE_BIUCC, 0);
664
665 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
666 mace_write(ioaddr, MACE_FIFOCC, 0x0F);
667
668 mace_write(ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
669 mace_write(ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
670
671 /*
672 * Bit 2-1 PORTSEL[1-0] Port Select.
673 * 00 AUI/10Base-2
674 * 01 10Base-T
675 * 10 DAI Port (reserved in Am2150)
676 * 11 GPSI
677 * For this card, only the first two are valid.
678 * So, PLSCC should be set to
679 * 0x00 for 10Base-2
680 * 0x02 for 10Base-T
681 * Or just set ASEL in PHYCC below!
682 */
683 switch (if_port) {
684 case 1:
685 mace_write(ioaddr, MACE_PLSCC, 0x02);
686 break;
687 case 2:
688 mace_write(ioaddr, MACE_PLSCC, 0x00);
689 break;
690 default:
691 mace_write(ioaddr, MACE_PHYCC, /* ASEL */ 4);
692 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
693 and the MACE device will automatically select the operating media
694 interface port. */
695 break;
696 }
697
698 mace_write(ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
699 /* Poll ADDRCHG bit */
700 while (mace_read(ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
701 ;
702 /* Set PADR register */
703 for (i = 0; i < ETHER_ADDR_LEN; i++)
704 mace_write(ioaddr, MACE_PADR, enet_addr[i]);
705
706 /* MAC Configuration Control Register should be written last */
707 /* Let set_multicast_list set this. */
708 /* mace_write(ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
709 mace_write(ioaddr, MACE_MACCC, 0x00);
710 } /* mace_init */
711
712 /* ----------------------------------------------------------------------------
713 nmclan_config
714 This routine is scheduled to run after a CARD_INSERTION event
715 is received, to configure the PCMCIA socket, and to make the
716 ethernet device available to the system.
717 ---------------------------------------------------------------------------- */
718
719 #define CS_CHECK(fn, args...) \
720 while ((last_ret=CardServices(last_fn=(fn), args))!=0) goto cs_failed
721
nmclan_config(dev_link_t * link)722 static void nmclan_config(dev_link_t *link)
723 {
724 client_handle_t handle = link->handle;
725 mace_private *lp = link->priv;
726 struct net_device *dev = &lp->dev;
727 tuple_t tuple;
728 cisparse_t parse;
729 u_char buf[64];
730 int i, last_ret, last_fn;
731 ioaddr_t ioaddr;
732
733 DEBUG(0, "nmclan_config(0x%p)\n", link);
734
735 tuple.Attributes = 0;
736 tuple.TupleData = buf;
737 tuple.TupleDataMax = 64;
738 tuple.TupleOffset = 0;
739 tuple.DesiredTuple = CISTPL_CONFIG;
740 CS_CHECK(GetFirstTuple, handle, &tuple);
741 CS_CHECK(GetTupleData, handle, &tuple);
742 CS_CHECK(ParseTuple, handle, &tuple, &parse);
743 link->conf.ConfigBase = parse.config.base;
744
745 /* Configure card */
746 link->state |= DEV_CONFIG;
747
748 CS_CHECK(RequestIO, handle, &link->io);
749 CS_CHECK(RequestIRQ, handle, &link->irq);
750 CS_CHECK(RequestConfiguration, handle, &link->conf);
751 dev->irq = link->irq.AssignedIRQ;
752 dev->base_addr = link->io.BasePort1;
753 i = register_netdev(dev);
754 if (i != 0) {
755 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
756 goto failed;
757 }
758
759 ioaddr = dev->base_addr;
760
761 /* Read the ethernet address from the CIS. */
762 tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
763 tuple.TupleData = buf;
764 tuple.TupleDataMax = 64;
765 tuple.TupleOffset = 0;
766 CS_CHECK(GetFirstTuple, handle, &tuple);
767 CS_CHECK(GetTupleData, handle, &tuple);
768 memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
769
770 /* Verify configuration by reading the MACE ID. */
771 {
772 char sig[2];
773
774 sig[0] = mace_read(ioaddr, MACE_CHIPIDL);
775 sig[1] = mace_read(ioaddr, MACE_CHIPIDH);
776 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
777 DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
778 sig[0], sig[1]);
779 } else {
780 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
781 " be 0x40 0x?9\n", sig[0], sig[1]);
782 link->state &= ~DEV_CONFIG_PENDING;
783 return;
784 }
785 }
786
787 mace_init(ioaddr, dev->dev_addr);
788
789 /* The if_port symbol can be set when the module is loaded */
790 if (if_port <= 2)
791 dev->if_port = if_port;
792 else
793 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
794
795 strcpy(lp->node.dev_name, dev->name);
796 link->dev = &lp->node;
797 link->state &= ~DEV_CONFIG_PENDING;
798
799 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port, hw_addr ",
800 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port]);
801 for (i = 0; i < 6; i++)
802 printk("%02X%s", dev->dev_addr[i], ((i<5) ? ":" : "\n"));
803 return;
804
805 cs_failed:
806 cs_error(link->handle, last_fn, last_ret);
807 failed:
808 nmclan_release((u_long)link);
809 return;
810
811 } /* nmclan_config */
812
813 /* ----------------------------------------------------------------------------
814 nmclan_release
815 After a card is removed, nmclan_release() will unregister the
816 net device, and release the PCMCIA configuration. If the device
817 is still open, this will be postponed until it is closed.
818 ---------------------------------------------------------------------------- */
nmclan_release(u_long arg)819 static void nmclan_release(u_long arg)
820 {
821 dev_link_t *link = (dev_link_t *)arg;
822
823 DEBUG(0, "nmclan_release(0x%p)\n", link);
824
825 if (link->open) {
826 DEBUG(1, "nmclan_cs: release postponed, '%s' "
827 "still open\n", link->dev->dev_name);
828 link->state |= DEV_STALE_CONFIG;
829 return;
830 }
831
832 CardServices(ReleaseConfiguration, link->handle);
833 CardServices(ReleaseIO, link->handle, &link->io);
834 CardServices(ReleaseIRQ, link->handle, &link->irq);
835
836 link->state &= ~DEV_CONFIG;
837
838 } /* nmclan_release */
839
840 /* ----------------------------------------------------------------------------
841 nmclan_event
842 The card status event handler. Mostly, this schedules other
843 stuff to run after an event is received. A CARD_REMOVAL event
844 also sets some flags to discourage the net drivers from trying
845 to talk to the card any more.
846 ---------------------------------------------------------------------------- */
nmclan_event(event_t event,int priority,event_callback_args_t * args)847 static int nmclan_event(event_t event, int priority,
848 event_callback_args_t *args)
849 {
850 dev_link_t *link = args->client_data;
851 mace_private *lp = link->priv;
852 struct net_device *dev = &lp->dev;
853
854 DEBUG(1, "nmclan_event(0x%06x)\n", event);
855
856 switch (event) {
857 case CS_EVENT_CARD_REMOVAL:
858 link->state &= ~DEV_PRESENT;
859 if (link->state & DEV_CONFIG) {
860 netif_device_detach(dev);
861 mod_timer(&link->release, jiffies + HZ/20);
862 }
863 break;
864 case CS_EVENT_CARD_INSERTION:
865 link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
866 nmclan_config(link);
867 break;
868 case CS_EVENT_PM_SUSPEND:
869 link->state |= DEV_SUSPEND;
870 /* Fall through... */
871 case CS_EVENT_RESET_PHYSICAL:
872 if (link->state & DEV_CONFIG) {
873 if (link->open)
874 netif_device_detach(dev);
875 CardServices(ReleaseConfiguration, link->handle);
876 }
877 break;
878 case CS_EVENT_PM_RESUME:
879 link->state &= ~DEV_SUSPEND;
880 /* Fall through... */
881 case CS_EVENT_CARD_RESET:
882 if (link->state & DEV_CONFIG) {
883 CardServices(RequestConfiguration, link->handle, &link->conf);
884 if (link->open) {
885 nmclan_reset(dev);
886 netif_device_attach(dev);
887 }
888 }
889 break;
890 case CS_EVENT_RESET_REQUEST:
891 return 1;
892 break;
893 }
894 return 0;
895 } /* nmclan_event */
896
897 /* ----------------------------------------------------------------------------
898 nmclan_reset
899 Reset and restore all of the Xilinx and MACE registers.
900 ---------------------------------------------------------------------------- */
nmclan_reset(struct net_device * dev)901 static void nmclan_reset(struct net_device *dev)
902 {
903 mace_private *lp = dev->priv;
904
905 #if RESET_XILINX
906 dev_link_t *link = &lp->link;
907 conf_reg_t reg;
908 u_long OrigCorValue;
909
910 /* Save original COR value */
911 reg.Function = 0;
912 reg.Action = CS_READ;
913 reg.Offset = CISREG_COR;
914 reg.Value = 0;
915 CardServices(AccessConfigurationRegister, link->handle, ®);
916 OrigCorValue = reg.Value;
917
918 /* Reset Xilinx */
919 reg.Action = CS_WRITE;
920 reg.Offset = CISREG_COR;
921 DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
922 OrigCorValue);
923 reg.Value = COR_SOFT_RESET;
924 CardServices(AccessConfigurationRegister, link->handle, ®);
925 /* Need to wait for 20 ms for PCMCIA to finish reset. */
926
927 /* Restore original COR configuration index */
928 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
929 CardServices(AccessConfigurationRegister, link->handle, ®);
930 /* Xilinx is now completely reset along with the MACE chip. */
931 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
932
933 #endif /* #if RESET_XILINX */
934
935 /* Xilinx is now completely reset along with the MACE chip. */
936 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
937
938 /* Reinitialize the MACE chip for operation. */
939 mace_init(dev->base_addr, dev->dev_addr);
940 mace_write(dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
941
942 /* Restore the multicast list and enable TX and RX. */
943 restore_multicast_list(dev);
944 } /* nmclan_reset */
945
946 /* ----------------------------------------------------------------------------
947 mace_config
948 [Someone tell me what this is supposed to do? Is if_port a defined
949 standard? If so, there should be defines to indicate 1=10Base-T,
950 2=10Base-2, etc. including limited automatic detection.]
951 ---------------------------------------------------------------------------- */
mace_config(struct net_device * dev,struct ifmap * map)952 static int mace_config(struct net_device *dev, struct ifmap *map)
953 {
954 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
955 if (map->port <= 2) {
956 dev->if_port = map->port;
957 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
958 if_names[dev->if_port]);
959 } else
960 return -EINVAL;
961 }
962 return 0;
963 } /* mace_config */
964
965 /* ----------------------------------------------------------------------------
966 mace_open
967 Open device driver.
968 ---------------------------------------------------------------------------- */
mace_open(struct net_device * dev)969 static int mace_open(struct net_device *dev)
970 {
971 ioaddr_t ioaddr = dev->base_addr;
972 mace_private *lp = dev->priv;
973 dev_link_t *link = &lp->link;
974
975 if (!DEV_OK(link))
976 return -ENODEV;
977
978 link->open++;
979 MOD_INC_USE_COUNT;
980
981 MACEBANK(0);
982
983 netif_start_queue(dev);
984 nmclan_reset(dev);
985
986 return 0; /* Always succeed */
987 } /* mace_open */
988
989 /* ----------------------------------------------------------------------------
990 mace_close
991 Closes device driver.
992 ---------------------------------------------------------------------------- */
mace_close(struct net_device * dev)993 static int mace_close(struct net_device *dev)
994 {
995 ioaddr_t ioaddr = dev->base_addr;
996 mace_private *lp = dev->priv;
997 dev_link_t *link = &lp->link;
998
999 DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
1000
1001 /* Mask off all interrupts from the MACE chip. */
1002 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
1003
1004 link->open--;
1005 netif_stop_queue(dev);
1006 if (link->state & DEV_STALE_CONFIG)
1007 mod_timer(&link->release, jiffies + HZ/20);
1008
1009 MOD_DEC_USE_COUNT;
1010
1011 return 0;
1012 } /* mace_close */
1013
netdev_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1014 static void netdev_get_drvinfo(struct net_device *dev,
1015 struct ethtool_drvinfo *info)
1016 {
1017 strcpy(info->driver, DRV_NAME);
1018 strcpy(info->version, DRV_VERSION);
1019 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
1020 }
1021
1022 #ifdef PCMCIA_DEBUG
netdev_get_msglevel(struct net_device * dev)1023 static u32 netdev_get_msglevel(struct net_device *dev)
1024 {
1025 return pc_debug;
1026 }
1027
netdev_set_msglevel(struct net_device * dev,u32 level)1028 static void netdev_set_msglevel(struct net_device *dev, u32 level)
1029 {
1030 pc_debug = level;
1031 }
1032 #endif /* PCMCIA_DEBUG */
1033
1034 static struct ethtool_ops netdev_ethtool_ops = {
1035 .get_drvinfo = netdev_get_drvinfo,
1036 #ifdef PCMCIA_DEBUG
1037 .get_msglevel = netdev_get_msglevel,
1038 .set_msglevel = netdev_set_msglevel,
1039 #endif /* PCMCIA_DEBUG */
1040 };
1041
1042 /* ----------------------------------------------------------------------------
1043 mace_start_xmit
1044 This routine begins the packet transmit function. When completed,
1045 it will generate a transmit interrupt.
1046
1047 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
1048 returns 0, the "packet is now solely the responsibility of the
1049 driver." If _start_xmit returns non-zero, the "transmission
1050 failed, put skb back into a list."
1051 ---------------------------------------------------------------------------- */
1052
mace_tx_timeout(struct net_device * dev)1053 static void mace_tx_timeout(struct net_device *dev)
1054 {
1055 mace_private *lp = (mace_private *)dev->priv;
1056 dev_link_t *link = &lp->link;
1057
1058 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
1059 #if RESET_ON_TIMEOUT
1060 printk("resetting card\n");
1061 CardServices(ResetCard, link->handle);
1062 #else /* #if RESET_ON_TIMEOUT */
1063 printk("NOT resetting card\n");
1064 #endif /* #if RESET_ON_TIMEOUT */
1065 dev->trans_start = jiffies;
1066 netif_wake_queue(dev);
1067 }
1068
mace_start_xmit(struct sk_buff * skb,struct net_device * dev)1069 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
1070 {
1071 mace_private *lp = (mace_private *)dev->priv;
1072 ioaddr_t ioaddr = dev->base_addr;
1073
1074 netif_stop_queue(dev);
1075
1076 DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
1077 dev->name, (long)skb->len);
1078
1079 #if (!TX_INTERRUPTABLE)
1080 /* Disable MACE TX interrupts. */
1081 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
1082 ioaddr + AM2150_MACE_BASE + MACE_IMR);
1083 lp->tx_irq_disabled=1;
1084 #endif /* #if (!TX_INTERRUPTABLE) */
1085
1086 {
1087 /* This block must not be interrupted by another transmit request!
1088 mace_tx_timeout will take care of timer-based retransmissions from
1089 the upper layers. The interrupt handler is guaranteed never to
1090 service a transmit interrupt while we are in here.
1091 */
1092
1093 lp->linux_stats.tx_bytes += skb->len;
1094 lp->tx_free_frames--;
1095
1096 /* WARNING: Write the _exact_ number of bytes written in the header! */
1097 /* Put out the word header [must be an outw()] . . . */
1098 outw(skb->len, ioaddr + AM2150_XMT);
1099 /* . . . and the packet [may be any combination of outw() and outb()] */
1100 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
1101 if (skb->len & 1) {
1102 /* Odd byte transfer */
1103 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
1104 }
1105
1106 dev->trans_start = jiffies;
1107
1108 #if MULTI_TX
1109 if (lp->tx_free_frames > 0)
1110 netif_start_queue(dev);
1111 #endif /* #if MULTI_TX */
1112 }
1113
1114 #if (!TX_INTERRUPTABLE)
1115 /* Re-enable MACE TX interrupts. */
1116 lp->tx_irq_disabled=0;
1117 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
1118 #endif /* #if (!TX_INTERRUPTABLE) */
1119
1120 dev_kfree_skb(skb);
1121
1122 return 0;
1123 } /* mace_start_xmit */
1124
1125 /* ----------------------------------------------------------------------------
1126 mace_interrupt
1127 The interrupt handler.
1128 ---------------------------------------------------------------------------- */
mace_interrupt(int irq,void * dev_id,struct pt_regs * regs)1129 static void mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1130 {
1131 mace_private *lp = (mace_private *)dev_id;
1132 struct net_device *dev = &lp->dev;
1133 ioaddr_t ioaddr = dev->base_addr;
1134 int status;
1135 int IntrCnt = MACE_MAX_IR_ITERATIONS;
1136
1137 if (dev == NULL) {
1138 DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1139 irq);
1140 return;
1141 }
1142
1143 if (lp->tx_irq_disabled) {
1144 printk(
1145 (lp->tx_irq_disabled?
1146 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1147 "[isr=%02X, imr=%02X]\n":
1148 KERN_NOTICE "%s: Re-entering the interrupt handler "
1149 "[isr=%02X, imr=%02X]\n"),
1150 dev->name,
1151 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1152 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1153 );
1154 /* WARNING: MACE_IR has been read! */
1155 return;
1156 }
1157
1158 if (!netif_device_present(dev)) {
1159 DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1160 goto exception;
1161 }
1162
1163 do {
1164 /* WARNING: MACE_IR is a READ/CLEAR port! */
1165 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1166
1167 DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1168
1169 if (status & MACE_IR_RCVINT) {
1170 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1171 }
1172
1173 if (status & MACE_IR_XMTINT) {
1174 unsigned char fifofc;
1175 unsigned char xmtrc;
1176 unsigned char xmtfs;
1177
1178 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1179 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1180 lp->linux_stats.tx_errors++;
1181 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1182 }
1183
1184 /* Transmit Retry Count (XMTRC, reg 4) */
1185 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1186 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1187 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1188
1189 if (
1190 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1191 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1192 ) {
1193 lp->mace_stats.xmtsv++;
1194
1195 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1196 if (xmtfs & MACE_XMTFS_UFLO) {
1197 /* Underflow. Indicates that the Transmit FIFO emptied before
1198 the end of frame was reached. */
1199 lp->mace_stats.uflo++;
1200 }
1201 if (xmtfs & MACE_XMTFS_LCOL) {
1202 /* Late Collision */
1203 lp->mace_stats.lcol++;
1204 }
1205 if (xmtfs & MACE_XMTFS_MORE) {
1206 /* MORE than one retry was needed */
1207 lp->mace_stats.more++;
1208 }
1209 if (xmtfs & MACE_XMTFS_ONE) {
1210 /* Exactly ONE retry occurred */
1211 lp->mace_stats.one++;
1212 }
1213 if (xmtfs & MACE_XMTFS_DEFER) {
1214 /* Transmission was defered */
1215 lp->mace_stats.defer++;
1216 }
1217 if (xmtfs & MACE_XMTFS_LCAR) {
1218 /* Loss of carrier */
1219 lp->mace_stats.lcar++;
1220 }
1221 if (xmtfs & MACE_XMTFS_RTRY) {
1222 /* Retry error: transmit aborted after 16 attempts */
1223 lp->mace_stats.rtry++;
1224 }
1225 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1226
1227 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1228
1229 lp->linux_stats.tx_packets++;
1230 lp->tx_free_frames++;
1231 netif_wake_queue(dev);
1232 } /* if (status & MACE_IR_XMTINT) */
1233
1234 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1235 if (status & MACE_IR_JAB) {
1236 /* Jabber Error. Excessive transmit duration (20-150ms). */
1237 lp->mace_stats.jab++;
1238 }
1239 if (status & MACE_IR_BABL) {
1240 /* Babble Error. >1518 bytes transmitted. */
1241 lp->mace_stats.babl++;
1242 }
1243 if (status & MACE_IR_CERR) {
1244 /* Collision Error. CERR indicates the absence of the
1245 Signal Quality Error Test message after a packet
1246 transmission. */
1247 lp->mace_stats.cerr++;
1248 }
1249 if (status & MACE_IR_RCVCCO) {
1250 /* Receive Collision Count Overflow; */
1251 lp->mace_stats.rcvcco++;
1252 }
1253 if (status & MACE_IR_RNTPCO) {
1254 /* Runt Packet Count Overflow */
1255 lp->mace_stats.rntpco++;
1256 }
1257 if (status & MACE_IR_MPCO) {
1258 /* Missed Packet Count Overflow */
1259 lp->mace_stats.mpco++;
1260 }
1261 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1262
1263 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1264
1265 exception:
1266 return;
1267 } /* mace_interrupt */
1268
1269 /* ----------------------------------------------------------------------------
1270 mace_rx
1271 Receives packets.
1272 ---------------------------------------------------------------------------- */
mace_rx(struct net_device * dev,unsigned char RxCnt)1273 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1274 {
1275 mace_private *lp = (mace_private *)dev->priv;
1276 ioaddr_t ioaddr = dev->base_addr;
1277 unsigned char rx_framecnt;
1278 unsigned short rx_status;
1279
1280 while (
1281 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1282 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1283 (RxCnt--)
1284 ) {
1285 rx_status = inw(ioaddr + AM2150_RCV);
1286
1287 DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1288 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1289
1290 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1291 lp->linux_stats.rx_errors++;
1292 if (rx_status & MACE_RCVFS_OFLO) {
1293 lp->mace_stats.oflo++;
1294 }
1295 if (rx_status & MACE_RCVFS_CLSN) {
1296 lp->mace_stats.clsn++;
1297 }
1298 if (rx_status & MACE_RCVFS_FRAM) {
1299 lp->mace_stats.fram++;
1300 }
1301 if (rx_status & MACE_RCVFS_FCS) {
1302 lp->mace_stats.fcs++;
1303 }
1304 } else {
1305 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1306 /* Auto Strip is off, always subtract 4 */
1307 struct sk_buff *skb;
1308
1309 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1310 /* runt packet count */
1311 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1312 /* rcv collision count */
1313
1314 DEBUG(3, " receiving packet size 0x%X rx_status"
1315 " 0x%X.\n", pkt_len, rx_status);
1316
1317 skb = dev_alloc_skb(pkt_len+2);
1318
1319 if (skb != NULL) {
1320 skb->dev = dev;
1321
1322 skb_reserve(skb, 2);
1323 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1324 if (pkt_len & 1)
1325 *(skb->tail-1) = inb(ioaddr + AM2150_RCV);
1326 skb->protocol = eth_type_trans(skb, dev);
1327
1328 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1329
1330 dev->last_rx = jiffies;
1331 lp->linux_stats.rx_packets++;
1332 lp->linux_stats.rx_bytes += skb->len;
1333 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1334 continue;
1335 } else {
1336 DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1337 " %d.\n", dev->name, pkt_len);
1338 lp->linux_stats.rx_dropped++;
1339 }
1340 }
1341 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1342 } /* while */
1343
1344 return 0;
1345 } /* mace_rx */
1346
1347 /* ----------------------------------------------------------------------------
1348 pr_linux_stats
1349 ---------------------------------------------------------------------------- */
pr_linux_stats(struct net_device_stats * pstats)1350 static void pr_linux_stats(struct net_device_stats *pstats)
1351 {
1352 DEBUG(2, "pr_linux_stats\n");
1353 DEBUG(2, " rx_packets=%-7ld tx_packets=%ld\n",
1354 (long)pstats->rx_packets, (long)pstats->tx_packets);
1355 DEBUG(2, " rx_errors=%-7ld tx_errors=%ld\n",
1356 (long)pstats->rx_errors, (long)pstats->tx_errors);
1357 DEBUG(2, " rx_dropped=%-7ld tx_dropped=%ld\n",
1358 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1359 DEBUG(2, " multicast=%-7ld collisions=%ld\n",
1360 (long)pstats->multicast, (long)pstats->collisions);
1361
1362 DEBUG(2, " rx_length_errors=%-7ld rx_over_errors=%ld\n",
1363 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1364 DEBUG(2, " rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1365 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1366 DEBUG(2, " rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1367 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1368
1369 DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1370 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1371 DEBUG(2, " tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1372 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1373 DEBUG(2, " tx_window_errors=%ld\n",
1374 (long)pstats->tx_window_errors);
1375 } /* pr_linux_stats */
1376
1377 /* ----------------------------------------------------------------------------
1378 pr_mace_stats
1379 ---------------------------------------------------------------------------- */
pr_mace_stats(mace_statistics * pstats)1380 static void pr_mace_stats(mace_statistics *pstats)
1381 {
1382 DEBUG(2, "pr_mace_stats\n");
1383
1384 DEBUG(2, " xmtsv=%-7d uflo=%d\n",
1385 pstats->xmtsv, pstats->uflo);
1386 DEBUG(2, " lcol=%-7d more=%d\n",
1387 pstats->lcol, pstats->more);
1388 DEBUG(2, " one=%-7d defer=%d\n",
1389 pstats->one, pstats->defer);
1390 DEBUG(2, " lcar=%-7d rtry=%d\n",
1391 pstats->lcar, pstats->rtry);
1392
1393 /* MACE_XMTRC */
1394 DEBUG(2, " exdef=%-7d xmtrc=%d\n",
1395 pstats->exdef, pstats->xmtrc);
1396
1397 /* RFS1--Receive Status (RCVSTS) */
1398 DEBUG(2, " oflo=%-7d clsn=%d\n",
1399 pstats->oflo, pstats->clsn);
1400 DEBUG(2, " fram=%-7d fcs=%d\n",
1401 pstats->fram, pstats->fcs);
1402
1403 /* RFS2--Runt Packet Count (RNTPC) */
1404 /* RFS3--Receive Collision Count (RCVCC) */
1405 DEBUG(2, " rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1406 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1407
1408 /* MACE_IR */
1409 DEBUG(2, " jab=%-7d babl=%d\n",
1410 pstats->jab, pstats->babl);
1411 DEBUG(2, " cerr=%-7d rcvcco=%d\n",
1412 pstats->cerr, pstats->rcvcco);
1413 DEBUG(2, " rntpco=%-7d mpco=%d\n",
1414 pstats->rntpco, pstats->mpco);
1415
1416 /* MACE_MPC */
1417 DEBUG(2, " mpc=%d\n", pstats->mpc);
1418
1419 /* MACE_RNTPC */
1420 DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1421
1422 /* MACE_RCVCC */
1423 DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1424
1425 } /* pr_mace_stats */
1426
1427 /* ----------------------------------------------------------------------------
1428 update_stats
1429 Update statistics. We change to register window 1, so this
1430 should be run single-threaded if the device is active. This is
1431 expected to be a rare operation, and it's simpler for the rest
1432 of the driver to assume that window 0 is always valid rather
1433 than use a special window-state variable.
1434
1435 oflo & uflo should _never_ occur since it would mean the Xilinx
1436 was not able to transfer data between the MACE FIFO and the
1437 card's SRAM fast enough. If this happens, something is
1438 seriously wrong with the hardware.
1439 ---------------------------------------------------------------------------- */
update_stats(ioaddr_t ioaddr,struct net_device * dev)1440 static void update_stats(ioaddr_t ioaddr, struct net_device *dev)
1441 {
1442 mace_private *lp = (mace_private *)dev->priv;
1443
1444 lp->mace_stats.rcvcc += mace_read(ioaddr, MACE_RCVCC);
1445 lp->mace_stats.rntpc += mace_read(ioaddr, MACE_RNTPC);
1446 lp->mace_stats.mpc += mace_read(ioaddr, MACE_MPC);
1447 /* At this point, mace_stats is fully updated for this call.
1448 We may now update the linux_stats. */
1449
1450 /* The MACE has no equivalent for linux_stats field which are commented
1451 out. */
1452
1453 /* lp->linux_stats.multicast; */
1454 lp->linux_stats.collisions =
1455 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1456 /* Collision: The MACE may retry sending a packet 15 times
1457 before giving up. The retry count is in XMTRC.
1458 Does each retry constitute a collision?
1459 If so, why doesn't the RCVCC record these collisions? */
1460
1461 /* detailed rx_errors: */
1462 lp->linux_stats.rx_length_errors =
1463 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1464 /* lp->linux_stats.rx_over_errors */
1465 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1466 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1467 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1468 lp->linux_stats.rx_missed_errors =
1469 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1470
1471 /* detailed tx_errors */
1472 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1473 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1474 /* LCAR usually results from bad cabling. */
1475 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1476 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1477 /* lp->linux_stats.tx_window_errors; */
1478
1479 return;
1480 } /* update_stats */
1481
1482 /* ----------------------------------------------------------------------------
1483 mace_get_stats
1484 Gathers ethernet statistics from the MACE chip.
1485 ---------------------------------------------------------------------------- */
mace_get_stats(struct net_device * dev)1486 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1487 {
1488 mace_private *lp = (mace_private *)dev->priv;
1489
1490 update_stats(dev->base_addr, dev);
1491
1492 DEBUG(1, "%s: updating the statistics.\n", dev->name);
1493 pr_linux_stats(&lp->linux_stats);
1494 pr_mace_stats(&lp->mace_stats);
1495
1496 return &lp->linux_stats;
1497 } /* net_device_stats */
1498
1499 /* ----------------------------------------------------------------------------
1500 updateCRC
1501 Modified from Am79C90 data sheet.
1502 ---------------------------------------------------------------------------- */
1503
1504 #if BROKEN_MULTICAST
1505
updateCRC(int * CRC,int bit)1506 static void updateCRC(int *CRC, int bit)
1507 {
1508 int poly[]={
1509 1,1,1,0, 1,1,0,1,
1510 1,0,1,1, 1,0,0,0,
1511 1,0,0,0, 0,0,1,1,
1512 0,0,1,0, 0,0,0,0
1513 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1514 CRC generator polynomial. */
1515
1516 int j;
1517
1518 /* shift CRC and control bit (CRC[32]) */
1519 for (j = 32; j > 0; j--)
1520 CRC[j] = CRC[j-1];
1521 CRC[0] = 0;
1522
1523 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1524 if (bit ^ CRC[32])
1525 for (j = 0; j < 32; j++)
1526 CRC[j] ^= poly[j];
1527 } /* updateCRC */
1528
1529 /* ----------------------------------------------------------------------------
1530 BuildLAF
1531 Build logical address filter.
1532 Modified from Am79C90 data sheet.
1533
1534 Input
1535 ladrf: logical address filter (contents initialized to 0)
1536 adr: ethernet address
1537 ---------------------------------------------------------------------------- */
BuildLAF(int * ladrf,int * adr)1538 static void BuildLAF(int *ladrf, int *adr)
1539 {
1540 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1541
1542 int i, byte; /* temporary array indices */
1543 int hashcode; /* the output object */
1544
1545 CRC[32]=0;
1546
1547 for (byte = 0; byte < 6; byte++)
1548 for (i = 0; i < 8; i++)
1549 updateCRC(CRC, (adr[byte] >> i) & 1);
1550
1551 hashcode = 0;
1552 for (i = 0; i < 6; i++)
1553 hashcode = (hashcode << 1) + CRC[i];
1554
1555 byte = hashcode >> 3;
1556 ladrf[byte] |= (1 << (hashcode & 7));
1557
1558 #ifdef PCMCIA_DEBUG
1559 if (pc_debug > 2) {
1560 printk(KERN_DEBUG " adr =");
1561 for (i = 0; i < 6; i++)
1562 printk(" %02X", adr[i]);
1563 printk("\n" KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63]"
1564 " =", hashcode);
1565 for (i = 0; i < 8; i++)
1566 printk(" %02X", ladrf[i]);
1567 printk("\n");
1568 }
1569 #endif
1570 } /* BuildLAF */
1571
1572 /* ----------------------------------------------------------------------------
1573 restore_multicast_list
1574 Restores the multicast filter for MACE chip to the last
1575 set_multicast_list() call.
1576
1577 Input
1578 multicast_num_addrs
1579 multicast_ladrf[]
1580 ---------------------------------------------------------------------------- */
restore_multicast_list(struct net_device * dev)1581 static void restore_multicast_list(struct net_device *dev)
1582 {
1583 mace_private *lp = (mace_private *)dev->priv;
1584 int num_addrs = lp->multicast_num_addrs;
1585 int *ladrf = lp->multicast_ladrf;
1586 ioaddr_t ioaddr = dev->base_addr;
1587 int i;
1588
1589 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1590 dev->name, num_addrs);
1591
1592 if (num_addrs > 0) {
1593
1594 DEBUG(1, "Attempt to restore multicast list detected.\n");
1595
1596 mace_write(ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1597 /* Poll ADDRCHG bit */
1598 while (mace_read(ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1599 ;
1600 /* Set LADRF register */
1601 for (i = 0; i < MACE_LADRF_LEN; i++)
1602 mace_write(ioaddr, MACE_LADRF, ladrf[i]);
1603
1604 mace_write(ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1605 mace_write(ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1606
1607 } else if (num_addrs < 0) {
1608
1609 /* Promiscuous mode: receive all packets */
1610 mace_write(ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1611 mace_write(ioaddr, MACE_MACCC,
1612 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1613 );
1614
1615 } else {
1616
1617 /* Normal mode */
1618 mace_write(ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1619 mace_write(ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1620
1621 }
1622 } /* restore_multicast_list */
1623
1624 /* ----------------------------------------------------------------------------
1625 set_multicast_list
1626 Set or clear the multicast filter for this adaptor.
1627
1628 Input
1629 num_addrs == -1 Promiscuous mode, receive all packets
1630 num_addrs == 0 Normal mode, clear multicast list
1631 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1632 best-effort filtering.
1633 Output
1634 multicast_num_addrs
1635 multicast_ladrf[]
1636 ---------------------------------------------------------------------------- */
1637
set_multicast_list(struct net_device * dev)1638 static void set_multicast_list(struct net_device *dev)
1639 {
1640 mace_private *lp = (mace_private *)dev->priv;
1641 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1642 int i;
1643 struct dev_mc_list *dmi = dev->mc_list;
1644
1645 #ifdef PCMCIA_DEBUG
1646 if (pc_debug > 1) {
1647 static int old;
1648 if (dev->mc_count != old) {
1649 old = dev->mc_count;
1650 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1651 dev->name, old);
1652 }
1653 }
1654 #endif
1655
1656 /* Set multicast_num_addrs. */
1657 lp->multicast_num_addrs = dev->mc_count;
1658
1659 /* Set multicast_ladrf. */
1660 if (num_addrs > 0) {
1661 /* Calculate multicast logical address filter */
1662 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1663 for (i = 0; i < dev->mc_count; i++) {
1664 memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1665 dmi = dmi->next;
1666 BuildLAF(lp->multicast_ladrf, adr);
1667 }
1668 }
1669
1670 restore_multicast_list(dev);
1671
1672 } /* set_multicast_list */
1673
1674 #endif /* BROKEN_MULTICAST */
1675
restore_multicast_list(struct net_device * dev)1676 static void restore_multicast_list(struct net_device *dev)
1677 {
1678 ioaddr_t ioaddr = dev->base_addr;
1679
1680 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1681 ((mace_private *)(dev->priv))->multicast_num_addrs);
1682
1683 if (dev->flags & IFF_PROMISC) {
1684 /* Promiscuous mode: receive all packets */
1685 mace_write(ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1686 mace_write(ioaddr, MACE_MACCC,
1687 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1688 );
1689 } else {
1690 /* Normal mode */
1691 mace_write(ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1692 mace_write(ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1693 }
1694 } /* restore_multicast_list */
1695
set_multicast_list(struct net_device * dev)1696 static void set_multicast_list(struct net_device *dev)
1697 {
1698 mace_private *lp = (mace_private *)dev->priv;
1699
1700 #ifdef PCMCIA_DEBUG
1701 if (pc_debug > 1) {
1702 static int old;
1703 if (dev->mc_count != old) {
1704 old = dev->mc_count;
1705 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1706 dev->name, old);
1707 }
1708 }
1709 #endif
1710
1711 lp->multicast_num_addrs = dev->mc_count;
1712 restore_multicast_list(dev);
1713
1714 } /* set_multicast_list */
1715
1716 /* ----------------------------------------------------------------------------
1717 init_nmclan_cs
1718 ---------------------------------------------------------------------------- */
1719
init_nmclan_cs(void)1720 static int __init init_nmclan_cs(void)
1721 {
1722 servinfo_t serv;
1723 DEBUG(0, "%s\n", version);
1724 CardServices(GetCardServicesInfo, &serv);
1725 if (serv.Revision != CS_RELEASE_CODE) {
1726 printk(KERN_NOTICE "nmclan_cs: Card Services release does not match!\n");
1727 return -1;
1728 }
1729 register_pccard_driver(&dev_info, &nmclan_attach, &nmclan_detach);
1730 return 0;
1731 }
1732
1733 /* ----------------------------------------------------------------------------
1734 exit_nmclan_cs
1735 ---------------------------------------------------------------------------- */
1736
exit_nmclan_cs(void)1737 static void __exit exit_nmclan_cs(void)
1738 {
1739 DEBUG(0, "nmclan_cs: unloading\n");
1740 unregister_pccard_driver(&dev_info);
1741 while (dev_list != NULL)
1742 nmclan_detach(dev_list);
1743 }
1744
1745 module_init(init_nmclan_cs);
1746 module_exit(exit_nmclan_cs);
1747