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Searched refs:KN03_SLOT_BASE (Results 1 – 3 of 3) sorted by relevance

/linux-2.4.37.9/include/asm-mips/dec/
Dkn03.h22 #define KN03_SLOT_BASE KSEG1ADDR(0x1f800000) macro
27 #define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
28 #define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */
29 #define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */
/linux-2.4.37.9/include/asm-mips64/dec/
Dkn03.h22 #define KN03_SLOT_BASE KSEG1ADDR(0x1f800000) macro
27 #define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
28 #define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */
29 #define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */
/linux-2.4.37.9/arch/mips/dec/
Decc-berr.c251 volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR); in dec_kn03_be_init()
252 volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR); in dec_kn03_be_init()
254 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); in dec_kn03_be_init()
255 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); in dec_kn03_be_init()