1 #ifndef __ASM_SH_IRQ_SH7300_H 2 #define __ASM_SH_IRQ_SH7300_H 3 4 /* 5 * linux/include/asm-sh/irq-sh7300.h 6 * 7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> 8 */ 9 10 #include <linux/config.h> 11 #include <asm/machvec.h> 12 #include <asm/ptrace.h> /* for pt_regs */ 13 14 #define INTC_IPRA 0xA414FEE2UL 15 #define INTC_IPRB 0xA414FEE4UL 16 #define INTC_IPRC 0xA4140016UL 17 #define INTC_IPRD 0xA4140018UL 18 #define INTC_IPRE 0xA414001AUL 19 #define INTC_IPRF 0xA4080000UL 20 #define INTC_IPRG 0xA4080002UL 21 #define INTC_IPRH 0xA4080004UL 22 #define INTC_IPRI 0xA4080006UL 23 #define INTC_IPRJ 0xA4080008UL 24 25 #define INTC_IMR0 0xA4080040UL 26 #define INTC_IMR1 0xA4080042UL 27 #define INTC_IMR2 0xA4080044UL 28 #define INTC_IMR3 0xA4080046UL 29 #define INTC_IMR4 0xA4080048UL 30 #define INTC_IMR5 0xA408004AUL 31 #define INTC_IMR6 0xA408004CUL 32 #define INTC_IMR7 0xA408004EUL 33 #define INTC_IMR8 0xA4080050UL 34 #define INTC_IMR9 0xA4080052UL 35 #define INTC_IMR10 0xA4080054UL 36 37 #define INTC_IMCR0 0xA4080060UL 38 #define INTC_IMCR1 0xA4080062UL 39 #define INTC_IMCR2 0xA4080064UL 40 #define INTC_IMCR3 0xA4080066UL 41 #define INTC_IMCR4 0xA4080068UL 42 #define INTC_IMCR5 0xA408006AUL 43 #define INTC_IMCR6 0xA408006CUL 44 #define INTC_IMCR7 0xA408006EUL 45 #define INTC_IMCR8 0xA4080070UL 46 #define INTC_IMCR9 0xA4080072UL 47 #define INTC_IMCR10 0xA4080074UL 48 49 #define INTC_ICR0 0xA414FEE0UL 50 #define INTC_ICR1 0xA4140010UL 51 52 #define INTC_IRR0 0xA4140004UL 53 54 /* TMU0 */ 55 #define TMU0_IRQ 16 56 #define TMU0_IPR_ADDR INTC_IPRA 57 #define TMU0_IPR_POS 3 58 #define TMU0_PRIORITY 2 59 60 #define TIMER_IRQ 16 61 #define TIMER_IPR_ADDR INTC_IPRA 62 #define TIMER_IPR_POS 3 63 #define TIMER_PRIORITY 2 64 65 /* TMU1 */ 66 #define TMU1_IRQ 17 67 #define TMU1_IPR_ADDR INTC_IPRA 68 #define TMU1_IPR_POS 2 69 #define TMU1_PRIORITY 2 70 71 /* TMU2 */ 72 #define TMU2_IRQ 18 73 #define TMU2_IPR_ADDR INTC_IPRA 74 #define TMU2_IPR_POS 1 75 #define TMU2_PRIORITY 2 76 77 /* WDT */ 78 #define WDT_IRQ 27 79 #define WDT_IPR_ADDR INTC_IPRB 80 #define WDT_IPR_POS 3 81 #define WDT_PRIORITY 2 82 83 /* SIM (SIM Card Module) */ 84 #define SIM_ERI_IRQ 23 85 #define SIM_RXI_IRQ 24 86 #define SIM_TXI_IRQ 25 87 #define SIM_TEND_IRQ 26 88 #define SIM_IPR_ADDR INTC_IPRB 89 #define SIM_IPR_POS 1 90 #define SIM_PRIORITY 2 91 92 /* VIO (Video I/O) */ 93 #define VIO_IRQ 52 94 #define VIO_IPR_ADDR INTC_IPRE 95 #define VIO_IPR_POS 2 96 #define VIO_PRIORITY 2 97 98 /* MFI (Multi Functional Interface) */ 99 #define MFI_IRQ 56 100 #define MFI_IPR_ADDR INTC_IPRE 101 #define MFI_IPR_POS 1 102 #define MFI_PRIORITY 2 103 104 /* VPU (Video Processing Unit) */ 105 #define VPU_IRQ 60 106 #define VPU_IPR_ADDR INTC_IPRE 107 #define VPU_IPR_POS 0 108 #define VPU_PRIORITY 2 109 110 /* KEY (Key Scan Interface) */ 111 #define KEY_IRQ 79 112 #define KEY_IPR_ADDR INTC_IPRF 113 #define KEY_IPR_POS 3 114 #define KEY_PRIORITY 2 115 116 /* CMT (Compare Match Timer) */ 117 #define CMT_IRQ 104 118 #define CMT_IPR_ADDR INTC_IPRF 119 #define CMT_IPR_POS 0 120 #define CMT_PRIORITY 2 121 122 /* DMAC(1) */ 123 #define DMTE0_IRQ 48 124 #define DMTE1_IRQ 49 125 #define DMTE2_IRQ 50 126 #define DMTE3_IRQ 51 127 #define DMA1_IPR_ADDR INTC_IPRE 128 #define DMA1_IPR_POS 3 129 #define DMA1_PRIORITY 7 130 131 /* DMAC(2) */ 132 #define DMTE4_IRQ 76 133 #define DMTE5_IRQ 77 134 #define DMA2_IPR_ADDR INTC_IPRF 135 #define DMA2_IPR_POS 2 136 #define DMA2_PRIORITY 7 137 138 /* SCIF0 */ 139 #define SCIF0_IRQ 80 140 #define SCIF0_IPR_ADDR INTC_IPRG 141 #define SCIF0_IPR_POS 3 142 #define SCIF0_PRIORITY 3 143 144 /* SIOF0 */ 145 #define SIOF0_IRQ 55 146 #define SIOF0_IPR_ADDR INTC_IPRH 147 #define SIOF0_IPR_POS 3 148 #define SIOF0_PRIORITY 3 149 150 /* FLCTL (Flash Memory Controller) */ 151 #define FLSTE_IRQ 92 152 #define FLTEND_IRQ 93 153 #define FLTRQ0_IRQ 94 154 #define FLTRQ1_IRQ 95 155 #define FLCTL_IPR_ADDR INTC_IPRH 156 #define FLCTL_IPR_POS 1 157 #define FLCTL_PRIORITY 3 158 159 /* IIC (IIC Bus Interface) */ 160 #define IIC_ALI_IRQ 96 161 #define IIC_TACKI_IRQ 97 162 #define IIC_WAITI_IRQ 98 163 #define IIC_DTEI_IRQ 99 164 #define IIC_IPR_ADDR INTC_IPRH 165 #define IIC_IPR_POS 0 166 #define IIC_PRIORITY 3 167 168 /* SIO0 */ 169 #define SIO0_IRQ 88 170 #define SIO0_IPR_ADDR INTC_IPRI 171 #define SIO0_IPR_POS 3 172 #define SIO0_PRIORITY 3 173 174 /* SIU (Sound Interface Unit) */ 175 #define SIU_IRQ 108 176 #define SIU_IPR_ADDR INTC_IPRJ 177 #define SIU_IPR_POS 1 178 #define SIU_PRIORITY 3 179 180 181 /* ONCHIP_NR_IRQS */ 182 #define NR_IRQS 109 183 184 /* In a generic kernel, NR_IRQS is an upper bound, and we should use 185 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value. 186 */ 187 #define ACTUAL_NR_IRQS NR_IRQS 188 189 190 extern void disable_irq(unsigned int); 191 extern void disable_irq_nosync(unsigned int); 192 extern void enable_irq(unsigned int); 193 194 /* 195 * Simple Mask Register Support 196 */ 197 extern void make_maskreg_irq(unsigned int irq); 198 extern unsigned short *irq_mask_register; 199 200 /* 201 * Function for "on chip support modules". 202 */ 203 extern void make_ipr_irq(unsigned int irq, unsigned int addr, 204 int pos, int priority); 205 extern void make_imask_irq(unsigned int irq); 206 207 #define PORT_PACR 0xA4050100UL 208 #define PORT_PBCR 0xA4050102UL 209 #define PORT_PCCR 0xA4050104UL 210 #define PORT_PDCR 0xA4050106UL 211 #define PORT_PECR 0xA4050108UL 212 #define PORT_PFCR 0xA405010AUL 213 #define PORT_PGCR 0xA405010CUL 214 #define PORT_PHCR 0xA405010EUL 215 #define PORT_PJCR 0xA4050110UL 216 #define PORT_PKCR 0xA4050112UL 217 #define PORT_PLCR 0xA4050114UL 218 #define PORT_SCPCR 0xA4050116UL 219 #define PORT_PMCR 0xA4050118UL 220 #define PORT_PNCR 0xA405011AUL 221 #define PORT_PQCR 0xA405011CUL 222 223 #define PORT_PSELA 0xA4050140UL 224 #define PORT_PSELB 0xA4050142UL 225 #define PORT_PSELC 0xA4050144UL 226 227 #define PORT_HIZCRA 0xA4050146UL 228 #define PORT_HIZCRB 0xA4050148UL 229 #define PORT_DRVCR 0xA4050150UL 230 231 #define PORT_PADR 0xA4050120UL 232 #define PORT_PBDR 0xA4050122UL 233 #define PORT_PCDR 0xA4050124UL 234 #define PORT_PDDR 0xA4050126UL 235 #define PORT_PEDR 0xA4050128UL 236 #define PORT_PFDR 0xA405012AUL 237 #define PORT_PGDR 0xA405012CUL 238 #define PORT_PHDR 0xA405012EUL 239 #define PORT_PJDR 0xA4050130UL 240 #define PORT_PKDR 0xA4050132UL 241 #define PORT_PLDR 0xA4050134UL 242 #define PORT_SCPDR 0xA4050136UL 243 #define PORT_PMDR 0xA4050138UL 244 #define PORT_PNDR 0xA405013AUL 245 #define PORT_PQDR 0xA405013CUL 246 247 #define IRQ0_IRQ 32 248 #define IRQ1_IRQ 33 249 #define IRQ2_IRQ 34 250 #define IRQ3_IRQ 35 251 #define IRQ4_IRQ 36 252 #define IRQ5_IRQ 37 253 254 #define IRQ0_IPR_ADDR INTC_IPRC 255 #define IRQ1_IPR_ADDR INTC_IPRC 256 #define IRQ2_IPR_ADDR INTC_IPRC 257 #define IRQ3_IPR_ADDR INTC_IPRC 258 #define IRQ4_IPR_ADDR INTC_IPRD 259 #define IRQ5_IPR_ADDR INTC_IPRD 260 261 #define IRQ0_IPR_POS 0 262 #define IRQ1_IPR_POS 1 263 #define IRQ2_IPR_POS 2 264 #define IRQ3_IPR_POS 3 265 #define IRQ4_IPR_POS 0 266 #define IRQ5_IPR_POS 1 267 268 #define IRQ0_PRIORITY 1 269 #define IRQ1_PRIORITY 1 270 #define IRQ2_PRIORITY 1 271 #define IRQ3_PRIORITY 1 272 #define IRQ4_PRIORITY 1 273 #define IRQ5_PRIORITY 1 274 275 extern int ipr_irq_demux(int irq); 276 #define __irq_demux(irq) ipr_irq_demux(irq) 277 #define irq_demux(irq) __irq_demux(irq) 278 279 #endif /* __ASM_SH_IRQ_SH7300_H */ 280