1 /* 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. 8 */ 9 10 #ifndef _ASM_IA64_SN_UART16550_H 11 #define _ASM_IA64_SN_UART16550_H 12 13 14 /* 15 * Definitions for 16550 chip 16 */ 17 18 /* defined as offsets from the data register */ 19 #define REG_DAT 0 /* receive/transmit data */ 20 #define REG_ICR 1 /* interrupt control register */ 21 #define REG_ISR 2 /* interrupt status register */ 22 #define REG_FCR 2 /* fifo control register */ 23 #define REG_LCR 3 /* line control register */ 24 #define REG_MCR 4 /* modem control register */ 25 #define REG_LSR 5 /* line status register */ 26 #define REG_MSR 6 /* modem status register */ 27 #define REG_SCR 7 /* Scratch register */ 28 #define REG_DLL 0 /* divisor latch (lsb) */ 29 #define REG_DLH 1 /* divisor latch (msb) */ 30 #define REG_EFR 2 /* 16650 enhanced feature register */ 31 32 /* 33 * 16450/16550 Registers Structure. 34 */ 35 36 /* Line Control Register */ 37 #define LCR_WLS0 0x01 /*word length select bit 0 */ 38 #define LCR_WLS1 0x02 /*word length select bit 2 */ 39 #define LCR_STB 0x04 /* number of stop bits */ 40 #define LCR_PEN 0x08 /* parity enable */ 41 #define LCR_EPS 0x10 /* even parity select */ 42 #define LCR_SETBREAK 0x40 /* break key */ 43 #define LCR_DLAB 0x80 /* divisor latch access bit */ 44 #define LCR_RXLEN 0x03 /* # of data bits per received/xmitted char */ 45 #define LCR_STOP1 0x00 46 #define LCR_STOP2 0x04 47 #define LCR_PAREN 0x08 48 #define LCR_PAREVN 0x10 49 #define LCR_PARMARK 0x20 50 #define LCR_SNDBRK 0x40 51 #define LCR_DLAB 0x80 52 53 54 #define LCR_BITS5 0x00 /* 5 bits per char */ 55 #define LCR_BITS6 0x01 /* 6 bits per char */ 56 #define LCR_BITS7 0x02 /* 7 bits per char */ 57 #define LCR_BITS8 0x03 /* 8 bits per char */ 58 59 #define LCR_1_STOP_BITS 0x00 /* 1 stop bit */ 60 #define LCR_2_STOP_BITS 0x04 /* 2 stop bits */ 61 62 #define LCR_MASK_BITS_CHAR 0x03 63 #define LCR_MASK_STOP_BITS 0x04 64 #define LCR_MASK_PARITY_BITS 0x18 65 66 67 /* Line Status Register */ 68 #define LSR_RCA 0x01 /* data ready */ 69 #define LSR_OVRRUN 0x02 /* overrun error */ 70 #define LSR_PARERR 0x04 /* parity error */ 71 #define LSR_FRMERR 0x08 /* framing error */ 72 #define LSR_BRKDET 0x10 /* a break has arrived */ 73 #define LSR_XHRE 0x20 /* tx hold reg is now empty */ 74 #define LSR_XSRE 0x40 /* tx shift reg is now empty */ 75 #define LSR_RFBE 0x80 /* rx FIFO Buffer error */ 76 77 /* Interrupt Status Regisger */ 78 #define ISR_MSTATUS 0x00 79 #define ISR_TxRDY 0x02 80 #define ISR_RxRDY 0x04 81 #define ISR_ERROR_INTR 0x08 82 #define ISR_FFTMOUT 0x0c /* FIFO Timeout */ 83 #define ISR_RSTATUS 0x06 /* Receiver Line status */ 84 85 /* Interrupt Enable Register */ 86 #define ICR_RIEN 0x01 /* Received Data Ready */ 87 #define ICR_TIEN 0x02 /* Tx Hold Register Empty */ 88 #define ICR_SIEN 0x04 /* Receiver Line Status */ 89 #define ICR_MIEN 0x08 /* Modem Status */ 90 91 /* Modem Control Register */ 92 #define MCR_DTR 0x01 /* Data Terminal Ready */ 93 #define MCR_RTS 0x02 /* Request To Send */ 94 #define MCR_OUT1 0x04 /* Aux output - not used */ 95 #define MCR_OUT2 0x08 /* turns intr to 386 on/off */ 96 #define MCR_LOOP 0x10 /* loopback for diagnostics */ 97 #define MCR_AFE 0x20 /* Auto flow control enable */ 98 99 /* Modem Status Register */ 100 #define MSR_DCTS 0x01 /* Delta Clear To Send */ 101 #define MSR_DDSR 0x02 /* Delta Data Set Ready */ 102 #define MSR_DRI 0x04 /* Trail Edge Ring Indicator */ 103 #define MSR_DDCD 0x08 /* Delta Data Carrier Detect */ 104 #define MSR_CTS 0x10 /* Clear To Send */ 105 #define MSR_DSR 0x20 /* Data Set Ready */ 106 #define MSR_RI 0x40 /* Ring Indicator */ 107 #define MSR_DCD 0x80 /* Data Carrier Detect */ 108 109 #define DELTAS(x) ((x)&(MSR_DCTS|MSR_DDSR|MSR_DRI|MSR_DDCD)) 110 #define STATES(x) ((x)(MSR_CTS|MSR_DSR|MSR_RI|MSR_DCD)) 111 112 113 #define FCR_FIFOEN 0x01 /* enable receive/transmit fifo */ 114 #define FCR_RxFIFO 0x02 /* enable receive fifo */ 115 #define FCR_TxFIFO 0x04 /* enable transmit fifo */ 116 #define FCR_MODE1 0x08 /* change to mode 1 */ 117 #define RxLVL0 0x00 /* Rx fifo level at 1 */ 118 #define RxLVL1 0x40 /* Rx fifo level at 4 */ 119 #define RxLVL2 0x80 /* Rx fifo level at 8 */ 120 #define RxLVL3 0xc0 /* Rx fifo level at 14 */ 121 122 #define FIFOEN (FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO | RxLVL3 | FCR_MODE1) 123 124 #define FCT_TxMASK 0x30 /* mask for Tx trigger */ 125 #define FCT_RxMASK 0xc0 /* mask for Rx trigger */ 126 127 /* enhanced festures register */ 128 #define EFR_SFLOW 0x0f /* various S/w Flow Controls */ 129 #define EFR_EIC 0x10 /* Enhanced Interrupt Control bit */ 130 #define EFR_SCD 0x20 /* Special Character Detect */ 131 #define EFR_RTS 0x40 /* RTS flow control */ 132 #define EFR_CTS 0x80 /* CTS flow control */ 133 134 /* Rx Tx software flow controls in 16650 enhanced mode */ 135 #define SFLOW_Tx0 0x00 /* no Xmit flow control */ 136 #define SFLOW_Tx1 0x08 /* Transmit Xon1, Xoff1 */ 137 #define SFLOW_Tx2 0x04 /* Transmit Xon2, Xoff2 */ 138 #define SFLOW_Tx3 0x0c /* Transmit Xon1,Xon2, Xoff1,Xoff2 */ 139 #define SFLOW_Rx0 0x00 /* no Rcv flow control */ 140 #define SFLOW_Rx1 0x02 /* Receiver compares Xon1, Xoff1 */ 141 #define SFLOW_Rx2 0x01 /* Receiver compares Xon2, Xoff2 */ 142 143 #define ASSERT_DTR(x) (x |= MCR_DTR) 144 #define ASSERT_RTS(x) (x |= MCR_RTS) 145 #define DU_RTS_ASSERTED(x) (((x) & MCR_RTS) != 0) 146 #define DU_RTS_ASSERT(x) ((x) |= MCR_RTS) 147 #define DU_RTS_DEASSERT(x) ((x) &= ~MCR_RTS) 148 149 #define SER_DIVISOR(x, clk) (((clk) + (x) * 8) / ((x) * 16)) 150 #define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div)) 151 152 153 /* 154 * ioctl(fd, I_STR, arg) 155 * use the SIOC_RS422 and SIOC_EXTCLK combination to support MIDI 156 */ 157 #define SIOC ('z' << 8) /* z for z85130 */ 158 #define SIOC_EXTCLK (SIOC | 1) /* select/de-select external clock */ 159 #define SIOC_RS422 (SIOC | 2) /* select/de-select RS422 protocol */ 160 #define SIOC_ITIMER (SIOC | 3) /* upstream timer adjustment */ 161 #define SIOC_LOOPBACK (SIOC | 4) /* diagnostic loopback test mode */ 162 163 164 /* channel control register */ 165 #define DMA_INT_MASK 0xe0 /* ring intr mask */ 166 #define DMA_INT_TH25 0x20 /* 25% threshold */ 167 #define DMA_INT_TH50 0x40 /* 50% threshold */ 168 #define DMA_INT_TH75 0x60 /* 75% threshold */ 169 #define DMA_INT_EMPTY 0x80 /* ring buffer empty */ 170 #define DMA_INT_NEMPTY 0xa0 /* ring buffer not empty */ 171 #define DMA_INT_FULL 0xc0 /* ring buffer full */ 172 #define DMA_INT_NFULL 0xe0 /* ring buffer not full */ 173 174 #define DMA_CHANNEL_RESET 0x400 /* reset dma channel */ 175 #define DMA_ENABLE 0x200 /* enable DMA */ 176 177 /* peripheral controller intr status bits applicable to serial ports */ 178 #define ISA_SERIAL0_MASK 0x03f00000 /* mask for port #1 intrs */ 179 #define ISA_SERIAL0_DIR 0x00100000 /* device intr request */ 180 #define ISA_SERIAL0_Tx_THIR 0x00200000 /* Transmit DMA threshold */ 181 #define ISA_SERIAL0_Tx_PREQ 0x00400000 /* Transmit DMA pair req */ 182 #define ISA_SERIAL0_Tx_MEMERR 0x00800000 /* Transmit DMA memory err */ 183 #define ISA_SERIAL0_Rx_THIR 0x01000000 /* Receive DMA threshold */ 184 #define ISA_SERIAL0_Rx_OVERRUN 0x02000000 /* Receive DMA over-run */ 185 186 #define ISA_SERIAL1_MASK 0xfc000000 /* mask for port #1 intrs */ 187 #define ISA_SERIAL1_DIR 0x04000000 /* device intr request */ 188 #define ISA_SERIAL1_Tx_THIR 0x08000000 /* Transmit DMA threshold */ 189 #define ISA_SERIAL1_Tx_PREQ 0x10000000 /* Transmit DMA pair req */ 190 #define ISA_SERIAL1_Tx_MEMERR 0x20000000 /* Transmit DMA memory err */ 191 #define ISA_SERIAL1_Rx_THIR 0x40000000 /* Receive DMA threshold */ 192 #define ISA_SERIAL1_Rx_OVERRUN 0x80000000 /* Receive DMA over-run */ 193 194 #define MAX_RING_BLOCKS 128 /* 4096/32 */ 195 #define MAX_RING_SIZE 4096 196 197 /* DMA Input Control Byte */ 198 #define DMA_IC_OVRRUN 0x01 /* overrun error */ 199 #define DMA_IC_PARERR 0x02 /* parity error */ 200 #define DMA_IC_FRMERR 0x04 /* framing error */ 201 #define DMA_IC_BRKDET 0x08 /* a break has arrived */ 202 #define DMA_IC_VALID 0x80 /* pair is valid */ 203 204 /* DMA Output Control Byte */ 205 #define DMA_OC_TxINTR 0x20 /* set Tx intr after processing byte */ 206 #define DMA_OC_INVALID 0x00 /* invalid pair */ 207 #define DMA_OC_WTHR 0x40 /* Write byte to THR */ 208 #define DMA_OC_WMCR 0x80 /* Write byte to MCR */ 209 #define DMA_OC_DELAY 0xc0 /* time delay before next xmit */ 210 211 /* ring id's */ 212 #define RID_SERIAL0_TX 0x4 /* serial port 0, transmit ring buffer */ 213 #define RID_SERIAL0_RX 0x5 /* serial port 0, receive ring buffer */ 214 #define RID_SERIAL1_TX 0x6 /* serial port 1, transmit ring buffer */ 215 #define RID_SERIAL1_RX 0x7 /* serial port 1, receive ring buffer */ 216 217 #define CLOCK_XIN 22 218 #define PRESCALER_DIVISOR 3 219 #define CLOCK_ACE 7333333 220 221 /* 222 * increment the ring offset. One way to do this would be to add b'100000. 223 * this would let the offset value roll over automatically when it reaches 224 * its maximum value (127). However when we use the offset, we must use 225 * the appropriate bits only by masking with 0xfe0. 226 * The other option is to shift the offset right by 5 bits and look at its 227 * value. Then increment if required and shift back 228 * note: 127 * 2^5 = 4064 229 */ 230 #define INC_RING_POINTER(x) \ 231 ( ((x & 0xffe0) < 4064) ? (x += 32) : 0 ) 232 233 #endif /* _ASM_IA64_SN_UART16550_H */ 234