Searched refs:GG2_PCI_DRAM_BANK0 (Results 1 – 2 of 2) sorted by relevance
48 #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ macro
132 GG2_PCI_DRAM_BANK0+ in chrp_show_cpuinfo()