1 /*********************************************************************
2 *
3 * Filename: ali-ircc.h
4 * Version: 0.5
5 * Description: Driver for the ALI M1535D and M1543C FIR Controller
6 * Status: Experimental.
7 * Author: Benjamin Kong <benjamin_kong@ali.com.tw>
8 * Created at: 2000/10/16 03:46PM
9 * Modified at: 2001/1/3 02:56PM
10 * Modified by: Benjamin Kong <benjamin_kong@ali.com.tw>
11 *
12 * Copyright (c) 2000 Benjamin Kong <benjamin_kong@ali.com.tw>
13 * All Rights Reserved
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 ********************************************************************/
21
22 #ifndef ALI_IRCC_H
23 #define ALI_IRCC_H
24
25 #include <linux/time.h>
26
27 #include <linux/spinlock.h>
28 #include <linux/pm.h>
29 #include <asm/io.h>
30
31 /* SIR Register */
32 /* Usr definition of linux/serial_reg.h */
33
34 /* FIR Register */
35 #define BANK0 0x20
36 #define BANK1 0x21
37 #define BANK2 0x22
38 #define BANK3 0x23
39
40 #define FIR_MCR 0x07 /* Master Control Register */
41
42 /* Bank 0 */
43 #define FIR_DR 0x00 /* Alias 0, FIR Data Register (R/W) */
44 #define FIR_IER 0x01 /* Alias 1, FIR Interrupt Enable Register (R/W) */
45 #define FIR_IIR 0x02 /* Alias 2, FIR Interrupt Identification Register (Read only) */
46 #define FIR_LCR_A 0x03 /* Alias 3, FIR Line Control Register A (R/W) */
47 #define FIR_LCR_B 0x04 /* Alias 4, FIR Line Control Register B (R/W) */
48 #define FIR_LSR 0x05 /* Alias 5, FIR Line Status Register (R/W) */
49 #define FIR_BSR 0x06 /* Alias 6, FIR Bus Status Register (Read only) */
50
51
52 /* Alias 1 */
53 #define IER_FIFO 0x10 /* FIR FIFO Interrupt Enable */
54 #define IER_TIMER 0x20 /* Timer Interrupt Enable */
55 #define IER_EOM 0x40 /* End of Message Interrupt Enable */
56 #define IER_ACT 0x80 /* Active Frame Interrupt Enable */
57
58 /* Alias 2 */
59 #define IIR_FIFO 0x10 /* FIR FIFO Interrupt */
60 #define IIR_TIMER 0x20 /* Timer Interrupt */
61 #define IIR_EOM 0x40 /* End of Message Interrupt */
62 #define IIR_ACT 0x80 /* Active Frame Interrupt */
63
64 /* Alias 3 */
65 #define LCR_A_FIFO_RESET 0x80 /* FIFO Reset */
66
67 /* Alias 4 */
68 #define LCR_B_BW 0x10 /* Brick Wall */
69 #define LCR_B_SIP 0x20 /* SIP Enable */
70 #define LCR_B_TX_MODE 0x40 /* Transmit Mode */
71 #define LCR_B_RX_MODE 0x80 /* Receive Mode */
72
73 /* Alias 5 */
74 #define LSR_FIR_LSA 0x00 /* FIR Line Status Address */
75 #define LSR_FRAME_ABORT 0x08 /* Frame Abort */
76 #define LSR_CRC_ERROR 0x10 /* CRC Error */
77 #define LSR_SIZE_ERROR 0x20 /* Size Error */
78 #define LSR_FRAME_ERROR 0x40 /* Frame Error */
79 #define LSR_FIFO_UR 0x80 /* FIFO Underrun */
80 #define LSR_FIFO_OR 0x80 /* FIFO Overrun */
81
82 /* Alias 6 */
83 #define BSR_FIFO_NOT_EMPTY 0x80 /* FIFO Not Empty */
84
85 /* Bank 1 */
86 #define FIR_CR 0x00 /* Alias 0, FIR Configuration Register (R/W) */
87 #define FIR_FIFO_TR 0x01 /* Alias 1, FIR FIFO Threshold Register (R/W) */
88 #define FIR_DMA_TR 0x02 /* Alias 2, FIR DMA Threshold Register (R/W) */
89 #define FIR_TIMER_IIR 0x03 /* Alias 3, FIR Timer interrupt interval register (W/O) */
90 #define FIR_FIFO_FR 0x03 /* Alias 3, FIR FIFO Flag register (R/O) */
91 #define FIR_FIFO_RAR 0x04 /* Alias 4, FIR FIFO Read Address register (R/O) */
92 #define FIR_FIFO_WAR 0x05 /* Alias 5, FIR FIFO Write Address register (R/O) */
93 #define FIR_TR 0x06 /* Alias 6, Test REgister (W/O) */
94
95 /* Alias 0 */
96 #define CR_DMA_EN 0x01 /* DMA Enable */
97 #define CR_DMA_BURST 0x02 /* DMA Burst Mode */
98 #define CR_TIMER_EN 0x08 /* Timer Enable */
99
100 /* Alias 3 */
101 #define TIMER_IIR_500 0x00 /* 500 us */
102 #define TIMER_IIR_1ms 0x01 /* 1 ms */
103 #define TIMER_IIR_2ms 0x02 /* 2 ms */
104 #define TIMER_IIR_4ms 0x03 /* 4 ms */
105
106 /* Bank 2 */
107 #define FIR_IRDA_CR 0x00 /* Alias 0, IrDA Control Register (R/W) */
108 #define FIR_BOF_CR 0x01 /* Alias 1, BOF Count Register (R/W) */
109 #define FIR_BW_CR 0x02 /* Alias 2, Brick Wall Count Register (R/W) */
110 #define FIR_TX_DSR_HI 0x03 /* Alias 3, TX Data Size Register (high) (R/W) */
111 #define FIR_TX_DSR_LO 0x04 /* Alias 4, TX Data Size Register (low) (R/W) */
112 #define FIR_RX_DSR_HI 0x05 /* Alias 5, RX Data Size Register (high) (R/W) */
113 #define FIR_RX_DSR_LO 0x06 /* Alias 6, RX Data Size Register (low) (R/W) */
114
115 /* Alias 0 */
116 #define IRDA_CR_HDLC1152 0x80 /* 1.152Mbps HDLC Select */
117 #define IRDA_CR_CRC 0X40 /* CRC Select. */
118 #define IRDA_CR_HDLC 0x20 /* HDLC select. */
119 #define IRDA_CR_HP_MODE 0x10 /* HP mode (read only) */
120 #define IRDA_CR_SD_ST 0x08 /* SD/MODE State. */
121 #define IRDA_CR_FIR_SIN 0x04 /* FIR SIN Select. */
122 #define IRDA_CR_ITTX_0 0x02 /* SOUT State. IRTX force to 0 */
123 #define IRDA_CR_ITTX_1 0x03 /* SOUT State. IRTX force to 1 */
124
125 /* Bank 3 */
126 #define FIR_ID_VR 0x00 /* Alias 0, FIR ID Version Register (R/O) */
127 #define FIR_MODULE_CR 0x01 /* Alias 1, FIR Module Control Register (R/W) */
128 #define FIR_IO_BASE_HI 0x02 /* Alias 2, FIR Higher I/O Base Address Register (R/O) */
129 #define FIR_IO_BASE_LO 0x03 /* Alias 3, FIR Lower I/O Base Address Register (R/O) */
130 #define FIR_IRQ_CR 0x04 /* Alias 4, FIR IRQ Channel Register (R/O) */
131 #define FIR_DMA_CR 0x05 /* Alias 5, FIR DMA Channel Register (R/O) */
132
133 struct ali_chip {
134 char *name;
135 int cfg[2];
136 unsigned char entr1;
137 unsigned char entr2;
138 unsigned char cid_index;
139 unsigned char cid_value;
140 int (*probe)(struct ali_chip *chip, chipio_t *info);
141 int (*init)(struct ali_chip *chip, chipio_t *info);
142 };
143 typedef struct ali_chip ali_chip_t;
144
145
146 /* DMA modes needed */
147 #define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */
148 #define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */
149
150 #define MAX_TX_WINDOW 7
151 #define MAX_RX_WINDOW 7
152
153 #define TX_FIFO_Threshold 8
154 #define RX_FIFO_Threshold 1
155 #define TX_DMA_Threshold 1
156 #define RX_DMA_Threshold 1
157
158 /* For storing entries in the status FIFO */
159
160 struct st_fifo_entry {
161 int status;
162 int len;
163 };
164
165 struct st_fifo {
166 struct st_fifo_entry entries[MAX_RX_WINDOW];
167 int pending_bytes;
168 int head;
169 int tail;
170 int len;
171 };
172
173 struct frame_cb {
174 void *start; /* Start of frame in DMA mem */
175 int len; /* Lenght of frame in DMA mem */
176 };
177
178 struct tx_fifo {
179 struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */
180 int ptr; /* Currently being sent */
181 int len; /* Lenght of queue */
182 int free; /* Next free slot */
183 void *tail; /* Next free start in DMA mem */
184 };
185
186 /* Private data for each instance */
187 struct ali_ircc_cb {
188
189 struct st_fifo st_fifo; /* Info about received frames */
190 struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
191
192 struct net_device *netdev; /* Yes! we are some kind of netdevice */
193 struct net_device_stats stats;
194
195 struct irlap_cb *irlap; /* The link layer we are binded to */
196 struct qos_info qos; /* QoS capabilities for this device */
197
198 chipio_t io; /* IrDA controller information */
199 iobuff_t tx_buff; /* Transmit buffer */
200 iobuff_t rx_buff; /* Receive buffer */
201
202 __u8 ier; /* Interrupt enable register */
203
204 __u8 InterruptID; /* Interrupt ID */
205 __u8 BusStatus; /* Bus Status */
206 __u8 LineStatus; /* Line Status */
207
208 unsigned char rcvFramesOverflow;
209
210 struct timeval stamp;
211 struct timeval now;
212
213 spinlock_t lock; /* For serializing operations */
214
215 __u32 flags; /* Interface flags */
216 __u32 new_speed;
217 int index; /* Instance index */
218
219 unsigned char fifo_opti_buf;
220
221 struct pm_dev *dev;
222 };
223
switch_bank(int iobase,int bank)224 static inline void switch_bank(int iobase, int bank)
225 {
226 outb(bank, iobase+FIR_MCR);
227 }
228
229 #endif /* ALI_IRCC_H */
230