1 /* 2 * Communication Processor Module v2. 3 * 4 * This file contains structures and information for the communication 5 * processor channels found in the dual port RAM or parameter RAM. 6 * All CPM control and status is available through the CPM2 internal 7 * memory map. See immap_cpm2.h for details. 8 */ 9 #ifdef __KERNEL__ 10 #ifndef __CPM2__ 11 #define __CPM2__ 12 13 #include <asm/immap_cpm2.h> 14 15 /* CPM Command register. 16 */ 17 #define CPM_CR_RST ((uint)0x80000000) 18 #define CPM_CR_PAGE ((uint)0x7c000000) 19 #define CPM_CR_SBLOCK ((uint)0x03e00000) 20 #define CPM_CR_FLG ((uint)0x00010000) 21 #define CPM_CR_MCN ((uint)0x00003fc0) 22 #define CPM_CR_OPCODE ((uint)0x0000000f) 23 24 /* Device sub-block and page codes. 25 */ 26 #define CPM_CR_SCC1_SBLOCK (0x04) 27 #define CPM_CR_SCC2_SBLOCK (0x05) 28 #define CPM_CR_SCC3_SBLOCK (0x06) 29 #define CPM_CR_SCC4_SBLOCK (0x07) 30 #define CPM_CR_SMC1_SBLOCK (0x08) 31 #define CPM_CR_SMC2_SBLOCK (0x09) 32 #define CPM_CR_SPI_SBLOCK (0x0a) 33 #define CPM_CR_I2C_SBLOCK (0x0b) 34 #define CPM_CR_TIMER_SBLOCK (0x0f) 35 #define CPM_CR_RAND_SBLOCK (0x0e) 36 #define CPM_CR_FCC1_SBLOCK (0x10) 37 #define CPM_CR_FCC2_SBLOCK (0x11) 38 #define CPM_CR_FCC3_SBLOCK (0x12) 39 #define CPM_CR_IDMA1_SBLOCK (0x14) 40 #define CPM_CR_IDMA2_SBLOCK (0x15) 41 #define CPM_CR_IDMA3_SBLOCK (0x16) 42 #define CPM_CR_IDMA4_SBLOCK (0x17) 43 #define CPM_CR_MCC1_SBLOCK (0x1c) 44 45 #define CPM_CR_SCC1_PAGE (0x00) 46 #define CPM_CR_SCC2_PAGE (0x01) 47 #define CPM_CR_SCC3_PAGE (0x02) 48 #define CPM_CR_SCC4_PAGE (0x03) 49 #define CPM_CR_SMC1_PAGE (0x07) 50 #define CPM_CR_SMC2_PAGE (0x08) 51 #define CPM_CR_SPI_PAGE (0x09) 52 #define CPM_CR_I2C_PAGE (0x0a) 53 #define CPM_CR_TIMER_PAGE (0x0a) 54 #define CPM_CR_RAND_PAGE (0x0a) 55 #define CPM_CR_FCC1_PAGE (0x04) 56 #define CPM_CR_FCC2_PAGE (0x05) 57 #define CPM_CR_FCC3_PAGE (0x06) 58 #define CPM_CR_IDMA1_PAGE (0x07) 59 #define CPM_CR_IDMA2_PAGE (0x08) 60 #define CPM_CR_IDMA3_PAGE (0x09) 61 #define CPM_CR_IDMA4_PAGE (0x0a) 62 #define CPM_CR_MCC1_PAGE (0x07) 63 #define CPM_CR_MCC2_PAGE (0x08) 64 65 /* Some opcodes (there are more...later) 66 */ 67 #define CPM_CR_INIT_TRX ((ushort)0x0000) 68 #define CPM_CR_INIT_RX ((ushort)0x0001) 69 #define CPM_CR_INIT_TX ((ushort)0x0002) 70 #define CPM_CR_HUNT_MODE ((ushort)0x0003) 71 #define CPM_CR_STOP_TX ((ushort)0x0004) 72 #define CPM_CR_RESTART_TX ((ushort)0x0006) 73 #define CPM_CR_SET_GADDR ((ushort)0x0008) 74 #define CPM_CR_START_IDMA ((ushort)0x0009) 75 #define CPM_CR_STOP_IDMA ((ushort)0x000b) 76 77 #define mk_cr_cmd(PG, SBC, MCN, OP) \ 78 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) 79 80 /* Dual Port RAM addresses. The first 16K is available for almost 81 * any CPM use, so we put the BDs there. The first 128 bytes are 82 * used for SMC1 and SMC2 parameter RAM, so we start allocating 83 * BDs above that. All of this must change when we start 84 * downloading RAM microcode. 85 */ 86 #define CPM_DATAONLY_BASE ((uint)128) 87 #define CPM_DP_NOSPACE ((uint)0x7fffffff) 88 #ifdef CONFIG_8272 89 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) 90 #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) 91 #else 92 #define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) 93 #define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) 94 #endif 95 96 /* The number of pages of host memory we allocate for CPM. This is 97 * done early in kernel initialization to get physically contiguous 98 * pages. 99 */ 100 #define NUM_CPM_HOST_PAGES 2 101 102 103 /* Export the base address of the communication processor registers 104 * and dual port ram. 105 */ 106 extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ 107 uint cpm2_dpalloc(uint size, uint align); 108 uint cpm2_hostalloc(uint size, uint align); 109 void cpm2_setbrg(uint brg, uint rate); 110 void cpm2_fastbrg(uint brg, uint rate, int div16); 111 112 /* Buffer descriptors used by many of the CPM protocols. 113 */ 114 typedef struct cpm_buf_desc { 115 ushort cbd_sc; /* Status and Control */ 116 ushort cbd_datlen; /* Data length in buffer */ 117 uint cbd_bufaddr; /* Buffer address in host memory */ 118 } cbd_t; 119 120 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 121 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 122 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 123 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 124 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ 125 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 126 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 127 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 128 #define BD_SC_BR ((ushort)0x0020) /* Break received */ 129 #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 130 #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 131 #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 132 #define BD_SC_CD ((ushort)0x0001) /* ?? */ 133 134 /* Function code bits, usually generic to devices. 135 */ 136 #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ 137 #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ 138 #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ 139 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ 140 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ 141 142 /* Parameter RAM offsets from the base. 143 */ 144 #define PROFF_SCC1 ((uint)0x8000) 145 #define PROFF_SCC2 ((uint)0x8100) 146 #define PROFF_SCC3 ((uint)0x8200) 147 #define PROFF_SCC4 ((uint)0x8300) 148 #define PROFF_FCC1 ((uint)0x8400) 149 #define PROFF_FCC2 ((uint)0x8500) 150 #define PROFF_FCC3 ((uint)0x8600) 151 #define PROFF_MCC1 ((uint)0x8700) 152 #define PROFF_SMC1_BASE ((uint)0x87fc) 153 #define PROFF_IDMA1_BASE ((uint)0x87fe) 154 #define PROFF_MCC2 ((uint)0x8800) 155 #define PROFF_SMC2_BASE ((uint)0x88fc) 156 #define PROFF_IDMA2_BASE ((uint)0x88fe) 157 #define PROFF_SPI_BASE ((uint)0x89fc) 158 #define PROFF_IDMA3_BASE ((uint)0x89fe) 159 #define PROFF_TIMERS ((uint)0x8ae0) 160 #define PROFF_REVNUM ((uint)0x8af0) 161 #define PROFF_RAND ((uint)0x8af8) 162 #define PROFF_I2C_BASE ((uint)0x8afc) 163 #define PROFF_IDMA4_BASE ((uint)0x8afe) 164 165 /* The SMCs are relocated to any of the first eight DPRAM pages. 166 * We will fix these at the first locations of DPRAM, until we 167 * get some microcode patches :-). 168 * The parameter ram space for the SMCs is fifty-some bytes, and 169 * they are required to start on a 64 byte boundary. 170 */ 171 #define PROFF_SMC1 (0) 172 #define PROFF_SMC2 (64) 173 174 175 /* Define enough so I can at least use the serial port as a UART. 176 */ 177 typedef struct smc_uart { 178 ushort smc_rbase; /* Rx Buffer descriptor base address */ 179 ushort smc_tbase; /* Tx Buffer descriptor base address */ 180 u_char smc_rfcr; /* Rx function code */ 181 u_char smc_tfcr; /* Tx function code */ 182 ushort smc_mrblr; /* Max receive buffer length */ 183 uint smc_rstate; /* Internal */ 184 uint smc_idp; /* Internal */ 185 ushort smc_rbptr; /* Internal */ 186 ushort smc_ibc; /* Internal */ 187 uint smc_rxtmp; /* Internal */ 188 uint smc_tstate; /* Internal */ 189 uint smc_tdp; /* Internal */ 190 ushort smc_tbptr; /* Internal */ 191 ushort smc_tbc; /* Internal */ 192 uint smc_txtmp; /* Internal */ 193 ushort smc_maxidl; /* Maximum idle characters */ 194 ushort smc_tmpidl; /* Temporary idle counter */ 195 ushort smc_brklen; /* Last received break length */ 196 ushort smc_brkec; /* rcv'd break condition counter */ 197 ushort smc_brkcr; /* xmt break count register */ 198 ushort smc_rmask; /* Temporary bit mask */ 199 uint smc_stmp; /* SDMA Temp */ 200 } smc_uart_t; 201 202 /* SMC uart mode register (Internal memory map). 203 */ 204 #define SMCMR_REN ((ushort)0x0001) 205 #define SMCMR_TEN ((ushort)0x0002) 206 #define SMCMR_DM ((ushort)0x000c) 207 #define SMCMR_SM_GCI ((ushort)0x0000) 208 #define SMCMR_SM_UART ((ushort)0x0020) 209 #define SMCMR_SM_TRANS ((ushort)0x0030) 210 #define SMCMR_SM_MASK ((ushort)0x0030) 211 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 212 #define SMCMR_REVD SMCMR_PM_EVEN 213 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 214 #define SMCMR_BS SMCMR_PEN 215 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 216 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 217 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 218 219 /* SMC Event and Mask register. 220 */ 221 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 222 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 223 #define SMCM_TXE ((unsigned char)0x10) 224 #define SMCM_BSY ((unsigned char)0x04) 225 #define SMCM_TX ((unsigned char)0x02) 226 #define SMCM_RX ((unsigned char)0x01) 227 228 /* Baud rate generators. 229 */ 230 #define CPM_BRG_RST ((uint)0x00020000) 231 #define CPM_BRG_EN ((uint)0x00010000) 232 #define CPM_BRG_EXTC_INT ((uint)0x00000000) 233 #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) 234 #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) 235 #define CPM_BRG_ATB ((uint)0x00002000) 236 #define CPM_BRG_CD_MASK ((uint)0x00001ffe) 237 #define CPM_BRG_DIV16 ((uint)0x00000001) 238 239 /* SCCs. 240 */ 241 #define SCC_GSMRH_IRP ((uint)0x00040000) 242 #define SCC_GSMRH_GDE ((uint)0x00010000) 243 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 244 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 245 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 246 #define SCC_GSMRH_REVD ((uint)0x00002000) 247 #define SCC_GSMRH_TRX ((uint)0x00001000) 248 #define SCC_GSMRH_TTX ((uint)0x00000800) 249 #define SCC_GSMRH_CDP ((uint)0x00000400) 250 #define SCC_GSMRH_CTSP ((uint)0x00000200) 251 #define SCC_GSMRH_CDS ((uint)0x00000100) 252 #define SCC_GSMRH_CTSS ((uint)0x00000080) 253 #define SCC_GSMRH_TFL ((uint)0x00000040) 254 #define SCC_GSMRH_RFW ((uint)0x00000020) 255 #define SCC_GSMRH_TXSY ((uint)0x00000010) 256 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 257 #define SCC_GSMRH_SYNL8 ((uint)0x00000008) 258 #define SCC_GSMRH_SYNL4 ((uint)0x00000004) 259 #define SCC_GSMRH_RTSM ((uint)0x00000002) 260 #define SCC_GSMRH_RSYN ((uint)0x00000001) 261 262 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 263 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 264 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 265 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 266 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 267 #define SCC_GSMRL_TCI ((uint)0x10000000) 268 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 269 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 270 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 271 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 272 #define SCC_GSMRL_RINV ((uint)0x02000000) 273 #define SCC_GSMRL_TINV ((uint)0x01000000) 274 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 275 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 276 #define SCC_GSMRL_TPL_48 ((uint)0x00800000) 277 #define SCC_GSMRL_TPL_32 ((uint)0x00600000) 278 #define SCC_GSMRL_TPL_16 ((uint)0x00400000) 279 #define SCC_GSMRL_TPL_8 ((uint)0x00200000) 280 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 281 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 282 #define SCC_GSMRL_TPP_01 ((uint)0x00100000) 283 #define SCC_GSMRL_TPP_10 ((uint)0x00080000) 284 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 285 #define SCC_GSMRL_TEND ((uint)0x00040000) 286 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 287 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 288 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 289 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 290 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 291 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 292 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 293 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 294 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 295 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 296 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 297 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 298 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 299 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 300 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 301 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 302 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 303 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 304 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 305 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 306 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 307 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 308 #define SCC_GSMRL_ENR ((uint)0x00000020) 309 #define SCC_GSMRL_ENT ((uint)0x00000010) 310 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 311 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 312 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 313 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 314 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 315 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 316 #define SCC_GSMRL_MODE_UART ((uint)0x00000004) 317 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 318 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 319 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 320 321 #define SCC_TODR_TOD ((ushort)0x8000) 322 323 /* SCC Event and Mask register. 324 */ 325 #define SCCM_TXE ((unsigned char)0x10) 326 #define SCCM_BSY ((unsigned char)0x04) 327 #define SCCM_TX ((unsigned char)0x02) 328 #define SCCM_RX ((unsigned char)0x01) 329 330 typedef struct scc_param { 331 ushort scc_rbase; /* Rx Buffer descriptor base address */ 332 ushort scc_tbase; /* Tx Buffer descriptor base address */ 333 u_char scc_rfcr; /* Rx function code */ 334 u_char scc_tfcr; /* Tx function code */ 335 ushort scc_mrblr; /* Max receive buffer length */ 336 uint scc_rstate; /* Internal */ 337 uint scc_idp; /* Internal */ 338 ushort scc_rbptr; /* Internal */ 339 ushort scc_ibc; /* Internal */ 340 uint scc_rxtmp; /* Internal */ 341 uint scc_tstate; /* Internal */ 342 uint scc_tdp; /* Internal */ 343 ushort scc_tbptr; /* Internal */ 344 ushort scc_tbc; /* Internal */ 345 uint scc_txtmp; /* Internal */ 346 uint scc_rcrc; /* Internal */ 347 uint scc_tcrc; /* Internal */ 348 } sccp_t; 349 350 /* CPM Ethernet through SCC1. 351 */ 352 typedef struct scc_enet { 353 sccp_t sen_genscc; 354 uint sen_cpres; /* Preset CRC */ 355 uint sen_cmask; /* Constant mask for CRC */ 356 uint sen_crcec; /* CRC Error counter */ 357 uint sen_alec; /* alignment error counter */ 358 uint sen_disfc; /* discard frame counter */ 359 ushort sen_pads; /* Tx short frame pad character */ 360 ushort sen_retlim; /* Retry limit threshold */ 361 ushort sen_retcnt; /* Retry limit counter */ 362 ushort sen_maxflr; /* maximum frame length register */ 363 ushort sen_minflr; /* minimum frame length register */ 364 ushort sen_maxd1; /* maximum DMA1 length */ 365 ushort sen_maxd2; /* maximum DMA2 length */ 366 ushort sen_maxd; /* Rx max DMA */ 367 ushort sen_dmacnt; /* Rx DMA counter */ 368 ushort sen_maxb; /* Max BD byte count */ 369 ushort sen_gaddr1; /* Group address filter */ 370 ushort sen_gaddr2; 371 ushort sen_gaddr3; 372 ushort sen_gaddr4; 373 uint sen_tbuf0data0; /* Save area 0 - current frame */ 374 uint sen_tbuf0data1; /* Save area 1 - current frame */ 375 uint sen_tbuf0rba; /* Internal */ 376 uint sen_tbuf0crc; /* Internal */ 377 ushort sen_tbuf0bcnt; /* Internal */ 378 ushort sen_paddrh; /* physical address (MSB) */ 379 ushort sen_paddrm; 380 ushort sen_paddrl; /* physical address (LSB) */ 381 ushort sen_pper; /* persistence */ 382 ushort sen_rfbdptr; /* Rx first BD pointer */ 383 ushort sen_tfbdptr; /* Tx first BD pointer */ 384 ushort sen_tlbdptr; /* Tx last BD pointer */ 385 uint sen_tbuf1data0; /* Save area 0 - current frame */ 386 uint sen_tbuf1data1; /* Save area 1 - current frame */ 387 uint sen_tbuf1rba; /* Internal */ 388 uint sen_tbuf1crc; /* Internal */ 389 ushort sen_tbuf1bcnt; /* Internal */ 390 ushort sen_txlen; /* Tx Frame length counter */ 391 ushort sen_iaddr1; /* Individual address filter */ 392 ushort sen_iaddr2; 393 ushort sen_iaddr3; 394 ushort sen_iaddr4; 395 ushort sen_boffcnt; /* Backoff counter */ 396 397 /* NOTE: Some versions of the manual have the following items 398 * incorrectly documented. Below is the proper order. 399 */ 400 ushort sen_taddrh; /* temp address (MSB) */ 401 ushort sen_taddrm; 402 ushort sen_taddrl; /* temp address (LSB) */ 403 } scc_enet_t; 404 405 406 /* SCC Event register as used by Ethernet. 407 */ 408 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 409 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 410 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 411 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 412 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 413 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 414 415 /* SCC Mode Register (PSMR) as used by Ethernet. 416 */ 417 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ 418 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ 419 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ 420 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ 421 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 422 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ 423 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 424 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ 425 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ 426 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ 427 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ 428 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 429 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 430 431 /* Buffer descriptor control/status used by Ethernet receive. 432 * Common to SCC and FCC. 433 */ 434 #define BD_ENET_RX_EMPTY ((ushort)0x8000) 435 #define BD_ENET_RX_WRAP ((ushort)0x2000) 436 #define BD_ENET_RX_INTR ((ushort)0x1000) 437 #define BD_ENET_RX_LAST ((ushort)0x0800) 438 #define BD_ENET_RX_FIRST ((ushort)0x0400) 439 #define BD_ENET_RX_MISS ((ushort)0x0100) 440 #define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ 441 #define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ 442 #define BD_ENET_RX_LG ((ushort)0x0020) 443 #define BD_ENET_RX_NO ((ushort)0x0010) 444 #define BD_ENET_RX_SH ((ushort)0x0008) 445 #define BD_ENET_RX_CR ((ushort)0x0004) 446 #define BD_ENET_RX_OV ((ushort)0x0002) 447 #define BD_ENET_RX_CL ((ushort)0x0001) 448 #define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ 449 450 /* Buffer descriptor control/status used by Ethernet transmit. 451 * Common to SCC and FCC. 452 */ 453 #define BD_ENET_TX_READY ((ushort)0x8000) 454 #define BD_ENET_TX_PAD ((ushort)0x4000) 455 #define BD_ENET_TX_WRAP ((ushort)0x2000) 456 #define BD_ENET_TX_INTR ((ushort)0x1000) 457 #define BD_ENET_TX_LAST ((ushort)0x0800) 458 #define BD_ENET_TX_TC ((ushort)0x0400) 459 #define BD_ENET_TX_DEF ((ushort)0x0200) 460 #define BD_ENET_TX_HB ((ushort)0x0100) 461 #define BD_ENET_TX_LC ((ushort)0x0080) 462 #define BD_ENET_TX_RL ((ushort)0x0040) 463 #define BD_ENET_TX_RCMASK ((ushort)0x003c) 464 #define BD_ENET_TX_UN ((ushort)0x0002) 465 #define BD_ENET_TX_CSL ((ushort)0x0001) 466 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 467 468 /* SCC as UART 469 */ 470 typedef struct scc_uart { 471 sccp_t scc_genscc; 472 uint scc_res1; /* Reserved */ 473 uint scc_res2; /* Reserved */ 474 ushort scc_maxidl; /* Maximum idle chars */ 475 ushort scc_idlc; /* temp idle counter */ 476 ushort scc_brkcr; /* Break count register */ 477 ushort scc_parec; /* receive parity error counter */ 478 ushort scc_frmec; /* receive framing error counter */ 479 ushort scc_nosec; /* receive noise counter */ 480 ushort scc_brkec; /* receive break condition counter */ 481 ushort scc_brkln; /* last received break length */ 482 ushort scc_uaddr1; /* UART address character 1 */ 483 ushort scc_uaddr2; /* UART address character 2 */ 484 ushort scc_rtemp; /* Temp storage */ 485 ushort scc_toseq; /* Transmit out of sequence char */ 486 ushort scc_char1; /* control character 1 */ 487 ushort scc_char2; /* control character 2 */ 488 ushort scc_char3; /* control character 3 */ 489 ushort scc_char4; /* control character 4 */ 490 ushort scc_char5; /* control character 5 */ 491 ushort scc_char6; /* control character 6 */ 492 ushort scc_char7; /* control character 7 */ 493 ushort scc_char8; /* control character 8 */ 494 ushort scc_rccm; /* receive control character mask */ 495 ushort scc_rccr; /* receive control character register */ 496 ushort scc_rlbc; /* receive last break character */ 497 } scc_uart_t; 498 499 /* SCC Event and Mask registers when it is used as a UART. 500 */ 501 #define UART_SCCM_GLR ((ushort)0x1000) 502 #define UART_SCCM_GLT ((ushort)0x0800) 503 #define UART_SCCM_AB ((ushort)0x0200) 504 #define UART_SCCM_IDL ((ushort)0x0100) 505 #define UART_SCCM_GRA ((ushort)0x0080) 506 #define UART_SCCM_BRKE ((ushort)0x0040) 507 #define UART_SCCM_BRKS ((ushort)0x0020) 508 #define UART_SCCM_CCR ((ushort)0x0008) 509 #define UART_SCCM_BSY ((ushort)0x0004) 510 #define UART_SCCM_TX ((ushort)0x0002) 511 #define UART_SCCM_RX ((ushort)0x0001) 512 513 /* The SCC PSMR when used as a UART. 514 */ 515 #define SCU_PSMR_FLC ((ushort)0x8000) 516 #define SCU_PSMR_SL ((ushort)0x4000) 517 #define SCU_PSMR_CL ((ushort)0x3000) 518 #define SCU_PSMR_UM ((ushort)0x0c00) 519 #define SCU_PSMR_FRZ ((ushort)0x0200) 520 #define SCU_PSMR_RZS ((ushort)0x0100) 521 #define SCU_PSMR_SYN ((ushort)0x0080) 522 #define SCU_PSMR_DRT ((ushort)0x0040) 523 #define SCU_PSMR_PEN ((ushort)0x0010) 524 #define SCU_PSMR_RPM ((ushort)0x000c) 525 #define SCU_PSMR_REVP ((ushort)0x0008) 526 #define SCU_PSMR_TPM ((ushort)0x0003) 527 #define SCU_PSMR_TEVP ((ushort)0x0003) 528 529 /* CPM Transparent mode SCC. 530 */ 531 typedef struct scc_trans { 532 sccp_t st_genscc; 533 uint st_cpres; /* Preset CRC */ 534 uint st_cmask; /* Constant mask for CRC */ 535 } scc_trans_t; 536 537 #define BD_SCC_TX_LAST ((ushort)0x0800) 538 539 /* How about some FCCs..... 540 */ 541 #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) 542 #define FCC_GFMR_DIAG_LE ((uint)0x40000000) 543 #define FCC_GFMR_DIAG_AE ((uint)0x80000000) 544 #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) 545 #define FCC_GFMR_TCI ((uint)0x20000000) 546 #define FCC_GFMR_TRX ((uint)0x10000000) 547 #define FCC_GFMR_TTX ((uint)0x08000000) 548 #define FCC_GFMR_TTX ((uint)0x08000000) 549 #define FCC_GFMR_CDP ((uint)0x04000000) 550 #define FCC_GFMR_CTSP ((uint)0x02000000) 551 #define FCC_GFMR_CDS ((uint)0x01000000) 552 #define FCC_GFMR_CTSS ((uint)0x00800000) 553 #define FCC_GFMR_SYNL_NONE ((uint)0x00000000) 554 #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) 555 #define FCC_GFMR_SYNL_8 ((uint)0x00008000) 556 #define FCC_GFMR_SYNL_16 ((uint)0x0000c000) 557 #define FCC_GFMR_RTSM ((uint)0x00002000) 558 #define FCC_GFMR_RENC_NRZ ((uint)0x00000000) 559 #define FCC_GFMR_RENC_NRZI ((uint)0x00000800) 560 #define FCC_GFMR_REVD ((uint)0x00000400) 561 #define FCC_GFMR_TENC_NRZ ((uint)0x00000000) 562 #define FCC_GFMR_TENC_NRZI ((uint)0x00000100) 563 #define FCC_GFMR_TCRC_16 ((uint)0x00000000) 564 #define FCC_GFMR_TCRC_32 ((uint)0x00000080) 565 #define FCC_GFMR_ENR ((uint)0x00000020) 566 #define FCC_GFMR_ENT ((uint)0x00000010) 567 #define FCC_GFMR_MODE_ENET ((uint)0x0000000c) 568 #define FCC_GFMR_MODE_ATM ((uint)0x0000000a) 569 #define FCC_GFMR_MODE_HDLC ((uint)0x00000000) 570 571 /* Generic FCC parameter ram. 572 */ 573 typedef struct fcc_param { 574 ushort fcc_riptr; /* Rx Internal temp pointer */ 575 ushort fcc_tiptr; /* Tx Internal temp pointer */ 576 ushort fcc_res1; 577 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ 578 uint fcc_rstate; /* Upper byte is Func code, must be set */ 579 uint fcc_rbase; /* Receive BD base */ 580 ushort fcc_rbdstat; /* RxBD status */ 581 ushort fcc_rbdlen; /* RxBD down counter */ 582 uint fcc_rdptr; /* RxBD internal data pointer */ 583 uint fcc_tstate; /* Upper byte is Func code, must be set */ 584 uint fcc_tbase; /* Transmit BD base */ 585 ushort fcc_tbdstat; /* TxBD status */ 586 ushort fcc_tbdlen; /* TxBD down counter */ 587 uint fcc_tdptr; /* TxBD internal data pointer */ 588 uint fcc_rbptr; /* Rx BD Internal buf pointer */ 589 uint fcc_tbptr; /* Tx BD Internal buf pointer */ 590 uint fcc_rcrc; /* Rx temp CRC */ 591 uint fcc_res2; 592 uint fcc_tcrc; /* Tx temp CRC */ 593 } fccp_t; 594 595 596 /* Ethernet controller through FCC. 597 */ 598 typedef struct fcc_enet { 599 fccp_t fen_genfcc; 600 uint fen_statbuf; /* Internal status buffer */ 601 uint fen_camptr; /* CAM address */ 602 uint fen_cmask; /* Constant mask for CRC */ 603 uint fen_cpres; /* Preset CRC */ 604 uint fen_crcec; /* CRC Error counter */ 605 uint fen_alec; /* alignment error counter */ 606 uint fen_disfc; /* discard frame counter */ 607 ushort fen_retlim; /* Retry limit */ 608 ushort fen_retcnt; /* Retry counter */ 609 ushort fen_pper; /* Persistence */ 610 ushort fen_boffcnt; /* backoff counter */ 611 uint fen_gaddrh; /* Group address filter, high 32-bits */ 612 uint fen_gaddrl; /* Group address filter, low 32-bits */ 613 ushort fen_tfcstat; /* out of sequence TxBD */ 614 ushort fen_tfclen; 615 uint fen_tfcptr; 616 ushort fen_mflr; /* Maximum frame length (1518) */ 617 ushort fen_paddrh; /* MAC address */ 618 ushort fen_paddrm; 619 ushort fen_paddrl; 620 ushort fen_ibdcount; /* Internal BD counter */ 621 ushort fen_ibdstart; /* Internal BD start pointer */ 622 ushort fen_ibdend; /* Internal BD end pointer */ 623 ushort fen_txlen; /* Internal Tx frame length counter */ 624 uint fen_ibdbase[8]; /* Internal use */ 625 uint fen_iaddrh; /* Individual address filter */ 626 uint fen_iaddrl; 627 ushort fen_minflr; /* Minimum frame length (64) */ 628 ushort fen_taddrh; /* Filter transfer MAC address */ 629 ushort fen_taddrm; 630 ushort fen_taddrl; 631 ushort fen_padptr; /* Pointer to pad byte buffer */ 632 ushort fen_cftype; /* control frame type */ 633 ushort fen_cfrange; /* control frame range */ 634 ushort fen_maxb; /* maximum BD count */ 635 ushort fen_maxd1; /* Max DMA1 length (1520) */ 636 ushort fen_maxd2; /* Max DMA2 length (1520) */ 637 ushort fen_maxd; /* internal max DMA count */ 638 ushort fen_dmacnt; /* internal DMA counter */ 639 uint fen_octc; /* Total octect counter */ 640 uint fen_colc; /* Total collision counter */ 641 uint fen_broc; /* Total broadcast packet counter */ 642 uint fen_mulc; /* Total multicast packet count */ 643 uint fen_uspc; /* Total packets < 64 bytes */ 644 uint fen_frgc; /* Total packets < 64 bytes with errors */ 645 uint fen_ospc; /* Total packets > 1518 */ 646 uint fen_jbrc; /* Total packets > 1518 with errors */ 647 uint fen_p64c; /* Total packets == 64 bytes */ 648 uint fen_p65c; /* Total packets 64 < bytes <= 127 */ 649 uint fen_p128c; /* Total packets 127 < bytes <= 255 */ 650 uint fen_p256c; /* Total packets 256 < bytes <= 511 */ 651 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ 652 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ 653 uint fen_cambuf; /* Internal CAM buffer poiner */ 654 ushort fen_rfthr; /* Received frames threshold */ 655 ushort fen_rfcnt; /* Received frames count */ 656 } fcc_enet_t; 657 658 /* FCC Event/Mask register as used by Ethernet. 659 */ 660 #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 661 #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ 662 #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ 663 #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 664 #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ 665 #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ 666 #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 667 #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 668 669 /* FCC Mode Register (FPSMR) as used by Ethernet. 670 */ 671 #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ 672 #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ 673 #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ 674 #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ 675 #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ 676 #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ 677 #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ 678 #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ 679 #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ 680 #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ 681 #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ 682 #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ 683 #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ 684 685 /* IIC parameter RAM. 686 */ 687 typedef struct iic { 688 ushort iic_rbase; /* Rx Buffer descriptor base address */ 689 ushort iic_tbase; /* Tx Buffer descriptor base address */ 690 u_char iic_rfcr; /* Rx function code */ 691 u_char iic_tfcr; /* Tx function code */ 692 ushort iic_mrblr; /* Max receive buffer length */ 693 uint iic_rstate; /* Internal */ 694 uint iic_rdp; /* Internal */ 695 ushort iic_rbptr; /* Internal */ 696 ushort iic_rbc; /* Internal */ 697 uint iic_rxtmp; /* Internal */ 698 uint iic_tstate; /* Internal */ 699 uint iic_tdp; /* Internal */ 700 ushort iic_tbptr; /* Internal */ 701 ushort iic_tbc; /* Internal */ 702 uint iic_txtmp; /* Internal */ 703 } iic_t; 704 705 /* SPI parameter RAM. 706 */ 707 typedef struct spi { 708 ushort spi_rbase; /* Rx Buffer descriptor base address */ 709 ushort spi_tbase; /* Tx Buffer descriptor base address */ 710 u_char spi_rfcr; /* Rx function code */ 711 u_char spi_tfcr; /* Tx function code */ 712 ushort spi_mrblr; /* Max receive buffer length */ 713 uint spi_rstate; /* Internal */ 714 uint spi_rdp; /* Internal */ 715 ushort spi_rbptr; /* Internal */ 716 ushort spi_rbc; /* Internal */ 717 uint spi_rxtmp; /* Internal */ 718 uint spi_tstate; /* Internal */ 719 uint spi_tdp; /* Internal */ 720 ushort spi_tbptr; /* Internal */ 721 ushort spi_tbc; /* Internal */ 722 uint spi_txtmp; /* Internal */ 723 uint spi_res; /* Tx temp. */ 724 uint spi_res1[4]; /* SDMA temp. */ 725 } spi_t; 726 727 /* SPI Mode register. 728 */ 729 #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ 730 #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ 731 #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ 732 #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ 733 #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ 734 #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ 735 #define SPMODE_EN ((ushort)0x0100) /* Enable */ 736 #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ 737 #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ 738 739 #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) 740 #define SPMODE_PM(x) ((x) &0xF) 741 742 #define SPI_EB ((u_char)0x10) /* big endian byte order */ 743 744 #define BD_IIC_START ((ushort)0x0400) 745 746 /* IDMA parameter RAM 747 */ 748 typedef struct idma { 749 ushort ibase; /* IDMA buffer descriptor table base address */ 750 ushort dcm; /* DMA channel mode */ 751 ushort ibdptr; /* IDMA current buffer descriptor pointer */ 752 ushort dpr_buf; /* IDMA transfer buffer base address */ 753 ushort buf_inv; /* internal buffer inventory */ 754 ushort ss_max; /* steady-state maximum transfer size */ 755 ushort dpr_in_ptr; /* write pointer inside the internal buffer */ 756 ushort sts; /* source transfer size */ 757 ushort dpr_out_ptr; /* read pointer inside the internal buffer */ 758 ushort seob; /* source end of burst */ 759 ushort deob; /* destination end of burst */ 760 ushort dts; /* destination transfer size */ 761 ushort ret_add; /* return address when working in ERM=1 mode */ 762 ushort res0; /* reserved */ 763 uint bd_cnt; /* internal byte count */ 764 uint s_ptr; /* source internal data pointer */ 765 uint d_ptr; /* destination internal data pointer */ 766 uint istate; /* internal state */ 767 u_char res1[20]; /* pad to 64-byte length */ 768 } idma_t; 769 770 /* DMA channel mode bit fields 771 */ 772 #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */ 773 #define IDMA_DCM_LP ((ushort)0x4000) /* low priority */ 774 #define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */ 775 #define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */ 776 #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */ 777 #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */ 778 #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */ 779 #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */ 780 #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */ 781 #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */ 782 #define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */ 783 #define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */ 784 #define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */ 785 #define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */ 786 #define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */ 787 #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */ 788 #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */ 789 #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */ 790 791 /* IDMA Buffer Descriptors 792 */ 793 typedef struct idma_bd { 794 uint flags; 795 uint len; /* data length */ 796 uint src; /* source data buffer pointer */ 797 uint dst; /* destination data buffer pointer */ 798 } idma_bd_t; 799 800 /* IDMA buffer descriptor flag bit fields 801 */ 802 #define IDMA_BD_V ((uint)0x80000000) /* valid */ 803 #define IDMA_BD_W ((uint)0x20000000) /* wrap */ 804 #define IDMA_BD_I ((uint)0x10000000) /* interrupt */ 805 #define IDMA_BD_L ((uint)0x08000000) /* last */ 806 #define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */ 807 #define IDMA_BD_SDN ((uint)0x00400000) /* source done */ 808 #define IDMA_BD_DDN ((uint)0x00200000) /* destination done */ 809 #define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */ 810 #define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */ 811 #define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */ 812 #define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */ 813 #define IDMA_BD_SGBL ((uint)0x00002000) /* source global */ 814 #define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */ 815 #define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */ 816 #define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */ 817 818 /* per-channel IDMA registers 819 */ 820 typedef struct im_idma { 821 u_char idsr; /* IDMAn event status register */ 822 u_char res0[3]; 823 u_char idmr; /* IDMAn event mask register */ 824 u_char res1[3]; 825 } im_idma_t; 826 827 /* IDMA event register bit fields 828 */ 829 #define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */ 830 #define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */ 831 #define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */ 832 #define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */ 833 834 /* RISC Controller Configuration Register (RCCR) bit fields 835 */ 836 #define RCCR_TIME ((uint)0x80000000) /* timer enable */ 837 #define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */ 838 #define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */ 839 #define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */ 840 #define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */ 841 #define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */ 842 #define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */ 843 #define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */ 844 #define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */ 845 #define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */ 846 #define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */ 847 #define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */ 848 #define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */ 849 #define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */ 850 #define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */ 851 #define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */ 852 #define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */ 853 #define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */ 854 #define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */ 855 #define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */ 856 #define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */ 857 #define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */ 858 #define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */ 859 #define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */ 860 #define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */ 861 #define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */ 862 #define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */ 863 #define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */ 864 #define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */ 865 #define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */ 866 #define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */ 867 #define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */ 868 #define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */ 869 #define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */ 870 #define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */ 871 #define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */ 872 #define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */ 873 #define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */ 874 875 /*----------------------------------------------------------------------- 876 * CMXFCR - CMX FCC Clock Route Register 877 */ 878 #define CMXFCR_FC1 0x40000000 /* FCC1 connection */ 879 #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ 880 #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ 881 #define CMXFCR_FC2 0x00400000 /* FCC2 connection */ 882 #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ 883 #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ 884 #define CMXFCR_FC3 0x00004000 /* FCC3 connection */ 885 #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ 886 #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ 887 888 #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ 889 #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ 890 #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ 891 #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ 892 #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ 893 #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ 894 #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ 895 #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ 896 897 #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ 898 #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ 899 #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ 900 #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ 901 #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ 902 #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ 903 #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ 904 #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ 905 906 #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ 907 #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ 908 #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ 909 #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ 910 #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ 911 #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ 912 #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ 913 #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ 914 915 #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ 916 #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ 917 #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ 918 #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ 919 #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ 920 #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ 921 #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ 922 #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ 923 924 #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ 925 #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ 926 #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ 927 #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ 928 #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ 929 #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ 930 #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ 931 #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ 932 933 #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ 934 #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ 935 #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ 936 #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ 937 #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ 938 #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ 939 #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ 940 #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ 941 942 /*----------------------------------------------------------------------- 943 * CMXSCR - CMX SCC Clock Route Register 944 */ 945 #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ 946 #define CMXSCR_SC1 0x40000000 /* SCC1 connection */ 947 #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ 948 #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ 949 #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ 950 #define CMXSCR_SC2 0x00400000 /* SCC2 connection */ 951 #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ 952 #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ 953 #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ 954 #define CMXSCR_SC3 0x00004000 /* SCC3 connection */ 955 #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ 956 #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ 957 #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ 958 #define CMXSCR_SC4 0x00000040 /* SCC4 connection */ 959 #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ 960 #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ 961 962 #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ 963 #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ 964 #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ 965 #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ 966 #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ 967 #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ 968 #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ 969 #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ 970 971 #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ 972 #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ 973 #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ 974 #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ 975 #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ 976 #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ 977 #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ 978 #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ 979 980 #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ 981 #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ 982 #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ 983 #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ 984 #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ 985 #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ 986 #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ 987 #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ 988 989 #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ 990 #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ 991 #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ 992 #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ 993 #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ 994 #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ 995 #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ 996 #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ 997 998 #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ 999 #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ 1000 #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ 1001 #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ 1002 #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ 1003 #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ 1004 #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ 1005 #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ 1006 1007 #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ 1008 #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ 1009 #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ 1010 #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ 1011 #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ 1012 #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ 1013 #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ 1014 #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ 1015 1016 #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ 1017 #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ 1018 #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ 1019 #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ 1020 #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ 1021 #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ 1022 #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ 1023 #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ 1024 1025 #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ 1026 #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ 1027 #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ 1028 #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ 1029 #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ 1030 #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ 1031 #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ 1032 #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ 1033 1034 #endif /* __CPM2__ */ 1035 #endif /* __KERNEL__ */ 1036 1037 1038