1 /* 2 * ibm_emac.h 3 * 4 * 5 * Armin Kuster akuster@mvista.com 6 * June, 2002 7 * 8 * Copyright 2002 MontaVista Softare Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * You should have received a copy of the GNU General Public License along 27 * with this program; if not, write to the Free Software Foundation, Inc., 28 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 * 30 * Version: 1.0: 06/02/02 - armin 31 * pulled all emac defined out od enet.h 32 * 33 */ 34 35 #ifndef _IBM_OCP_EMAC_H_ 36 #define _IBM_OCP_EMAC_H_ 37 /* General defines needed for the driver */ 38 39 /* Emac */ 40 typedef struct emac_regs { 41 u32 em0mr0; 42 u32 em0mr1; 43 u32 em0tmr0; 44 u32 em0tmr1; 45 u32 em0rmr; 46 u32 em0isr; 47 u32 em0iser; 48 u32 em0iahr; 49 u32 em0ialr; 50 u32 em0vtpid; 51 u32 em0vtci; 52 u32 em0ptr; 53 u32 em0iaht1; 54 u32 em0iaht2; 55 u32 em0iaht3; 56 u32 em0iaht4; 57 u32 em0gaht1; 58 u32 em0gaht2; 59 u32 em0gaht3; 60 u32 em0gaht4; 61 u32 em0lsah; 62 u32 em0lsal; 63 u32 em0ipgvr; 64 u32 em0stacr; 65 u32 em0trtr; 66 u32 em0rwmr; 67 } emac_t; 68 69 70 /* MODE REG 0 */ 71 #define EMAC_M0_RXI 0x80000000 72 #define EMAC_M0_TXI 0x40000000 73 #define EMAC_M0_SRST 0x20000000 74 #define EMAC_M0_TXE 0x10000000 75 #define EMAC_M0_RXE 0x08000000 76 #define EMAC_M0_WKE 0x04000000 77 78 /* MODE Reg 1 */ 79 #define EMAC_M1_FDE 0x80000000 80 #define EMAC_M1_ILE 0x40000000 81 #define EMAC_M1_VLE 0x20000000 82 #define EMAC_M1_EIFC 0x10000000 83 #define EMAC_M1_APP 0x08000000 84 #define EMAC_M1_AEMI 0x02000000 85 #define EMAC_M1_IST 0x01000000 86 #define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ 87 #define EMAC_M1_MF_100MBPS 0x00400000 88 #define EMAC_M1_TR 0x00008000 89 #ifdef CONFIG_IBM_EMAC4 90 #define EMAC_M1_RFS_16K 0x00280000 /* 000 for 512 byte */ 91 #define EMAC_M1_RFS_8K 0x00200000 92 #define EMAC_M1_RFS_4K 0x00180000 93 #define EMAC_M1_RFS_2K 0x00100000 94 #define EMAC_M1_RFS_1K 0x00080000 95 #define EMAC_M1_TX_FIFO_16K 0x00050000 /* 0's for 512 byte */ 96 #define EMAC_M1_TX_FIFO_8K 0x00040000 97 #define EMAC_M1_TX_FIFO_4K 0x00030000 98 #define EMAC_M1_TX_FIFO_2K 0x00020000 99 #define EMAC_M1_TX_FIFO_1K 0x00010000 100 #define EMAC_M1_TX_MWSW 0x00001000 /* 0 wait for status */ 101 #define EMAC_M1_JUMBO_ENABLE 0x00000800 /* Upt to 9Kr status */ 102 #define EMAC_M1_OPB_CLK_66 0x00000008 /* 66Mhz */ 103 #define EMAC_M1_OPB_CLK_83 0x00000010 /* 83Mhz */ 104 #define EMAC_M1_OPB_CLK_100 0x00000018 /* 100Mhz */ 105 #define EMAC_M1_OPB_CLK_100P 0x00000020 /* 100Mhz+ */ 106 #else /* CONFIG_IBM_EMAC4 */ 107 #define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ 108 #define EMAC_M1_RFS_2K 0x00200000 109 #define EMAC_M1_RFS_1K 0x00100000 110 #define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ 111 #define EMAC_M1_TX_FIFO_1K 0x00040000 112 #define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ 113 #define EMAC_M1_TR1_DEPEND 0x00004000 114 #define EMAC_M1_TR1_MULTI 0x00002000 115 #define EMAC_M1_JUMBO_ENABLE 0x00001000 116 #endif /* CONFIG_IBM_EMAC4 */ 117 #define EMAC_M1_BASE (EMAC_M1_RFS_4K | \ 118 EMAC_M1_TX_FIFO_2K | \ 119 EMAC_M1_APP | \ 120 EMAC_M1_TR) 121 122 /* Transmit Mode Register 0 */ 123 #define EMAC_TMR0_GNP0 0x80000000 124 #define EMAC_TMR0_GNP1 0x40000000 125 #define EMAC_TMR0_GNPD 0x20000000 126 #define EMAC_TMR0_FC 0x10000000 127 #define EMAC_TMR0_TFAE_2_32 0x00000001 128 #define EMAC_TMR0_TFAE_4_64 0x00000002 129 #define EMAC_TMR0_TFAE_8_128 0x00000003 130 #define EMAC_TMR0_TFAE_16_256 0x00000004 131 #define EMAC_TMR0_TFAE_32_512 0x00000005 132 #define EMAC_TMR0_TFAE_64_1024 0x00000006 133 #define EMAC_TMR0_TFAE_128_2048 0x00000007 134 135 /* Receive Mode Register */ 136 #define EMAC_RMR_SP 0x80000000 137 #define EMAC_RMR_SFCS 0x40000000 138 #define EMAC_RMR_ARRP 0x20000000 139 #define EMAC_RMR_ARP 0x10000000 140 #define EMAC_RMR_AROP 0x08000000 141 #define EMAC_RMR_ARPI 0x04000000 142 #define EMAC_RMR_PPP 0x02000000 143 #define EMAC_RMR_PME 0x01000000 144 #define EMAC_RMR_PMME 0x00800000 145 #define EMAC_RMR_IAE 0x00400000 146 #define EMAC_RMR_MIAE 0x00200000 147 #define EMAC_RMR_BAE 0x00100000 148 #define EMAC_RMR_MAE 0x00080000 149 #define EMAC_RMR_RFAF_2_32 0x00000001 150 #define EMAC_RMR_RFAF_4_64 0x00000002 151 #define EMAC_RMR_RFAF_8_128 0x00000003 152 #define EMAC_RMR_RFAF_16_256 0x00000004 153 #define EMAC_RMR_RFAF_32_512 0x00000005 154 #define EMAC_RMR_RFAF_64_1024 0x00000006 155 #define EMAC_RMR_RFAF_128_2048 0x00000007 156 #define EMAC_RMR_BASE (EMAC_RMR_IAE | EMAC_RMR_BAE) 157 158 /* Interrupt Status & enable Regs */ 159 #define EMAC_ISR_OVR 0x02000000 160 #define EMAC_ISR_PP 0x01000000 161 #define EMAC_ISR_BP 0x00800000 162 #define EMAC_ISR_RP 0x00400000 163 #define EMAC_ISR_SE 0x00200000 164 #define EMAC_ISR_ALE 0x00100000 165 #define EMAC_ISR_BFCS 0x00080000 166 #define EMAC_ISR_PTLE 0x00040000 167 #define EMAC_ISR_ORE 0x00020000 168 #define EMAC_ISR_IRE 0x00010000 169 #define EMAC_ISR_DBDM 0x00000200 170 #define EMAC_ISR_DB0 0x00000100 171 #define EMAC_ISR_SE0 0x00000080 172 #define EMAC_ISR_TE0 0x00000040 173 #define EMAC_ISR_DB1 0x00000020 174 #define EMAC_ISR_SE1 0x00000010 175 #define EMAC_ISR_TE1 0x00000008 176 #define EMAC_ISR_MOS 0x00000002 177 #define EMAC_ISR_MOF 0x00000001 178 179 /* STA CONTROL REG */ 180 #define EMAC_STACR_OC 0x00008000 181 #define EMAC_STACR_PHYE 0x00004000 182 #define EMAC_STACR_WRITE 0x00002000 183 #define EMAC_STACR_READ 0x00001000 184 #define EMAC_STACR_CLK_83MHZ 0x00000800 /* 0's for 50Mhz */ 185 #define EMAC_STACR_CLK_66MHZ 0x00000400 186 #define EMAC_STACR_CLK_100MHZ 0x00000C00 187 188 /* Transmit Request Threshold Register */ 189 #define EMAC_TRTR_1600 0x18000000 /* 0's for 64 Bytes */ 190 #define EMAC_TRTR_256 0x03000000 191 #define EMAC_TRTR_192 0x10000000 192 #define EMAC_TRTR_128 0x01000000 193 194 #define EMAC_TX_CTRL_GFCS 0x0200 195 #define EMAC_TX_CTRL_GP 0x0100 196 #define EMAC_TX_CTRL_ISA 0x0080 197 #define EMAC_TX_CTRL_RSA 0x0040 198 #define EMAC_TX_CTRL_IVT 0x0020 199 #define EMAC_TX_CTRL_RVT 0x0010 200 201 #define EMAC_TX_CTRL_DFLT ( \ 202 MAL_TX_CTRL_LAST | MAL_TX_CTRL_READY | MAL_TX_CTRL_INTR | \ 203 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP ) 204 205 /* madmal transmit status / Control bits */ 206 #define EMAC_TX_ST_BFCS 0x0200 207 #define EMAC_TX_ST_BPP 0x0100 208 #define EMAC_TX_ST_LCS 0x0080 209 #define EMAC_TX_ST_ED 0x0040 210 #define EMAC_TX_ST_EC 0x0020 211 #define EMAC_TX_ST_LC 0x0010 212 #define EMAC_TX_ST_MC 0x0008 213 #define EMAC_TX_ST_SC 0x0004 214 #define EMAC_TX_ST_UR 0x0002 215 #define EMAC_TX_ST_SQE 0x0001 216 217 /* madmal receive status / Control bits */ 218 #define EMAC_RX_ST_OE 0x0200 219 #define EMAC_RX_ST_PP 0x0100 220 #define EMAC_RX_ST_BP 0x0080 221 #define EMAC_RX_ST_RP 0x0040 222 #define EMAC_RX_ST_SE 0x0020 223 #define EMAC_RX_ST_AE 0x0010 224 #define EMAC_RX_ST_BFCS 0x0008 225 #define EMAC_RX_ST_PTL 0x0004 226 #define EMAC_RX_ST_ORE 0x0002 227 #define EMAC_RX_ST_IRE 0x0001 228 #define EMAC_BAD_RX_PACKET 0x02ff 229 230 /* Revision specific EMAC register defaults */ 231 #ifdef CONFIG_IBM_EMAC4 232 #define EMAC_M1_DEFAULT (EMAC_M1_BASE | \ 233 EMAC_M1_OPB_CLK_66 | \ 234 EMAC_M1_TX_MWSW) 235 #define EMAC_RMR_DEFAULT (EMAC_RMR_BASE | \ 236 EMAC_RMR_RFAF_128_2048) 237 #define EMAC_TMR0_XMIT (EMAC_TMR0_GNP0 | \ 238 EMAC_TMR0_TFAE_128_2048) 239 #define EMAC_TRTR_DEFAULT EMAC_TRTR_256 240 #else /* !CONFIG_IBM_EMAC4 */ 241 #define EMAC_M1_DEFAULT EMAC_M1_BASE 242 #define EMAC_RMR_DEFAULT EMAC_RMR_BASE 243 #define EMAC_TMR0_XMIT EMAC_TMR0_GNP0 244 #define EMAC_TRTR_DEFAULT EMAC_TRTR_1600 245 #endif /* CONFIG_IBM_EMAC4 */ 246 247 /* SoC implementation specific EMAC register defaults */ 248 #if defined(CONFIG_440GP) 249 #define EMAC_RWMR_DEFAULT 0x80009000 250 #define EMAC_TMR0_DEFAULT 0x00000000 251 #define EMAC_TMR1_DEFAULT 0xf8640000 252 #elif defined(CONFIG_440GX) 253 #define EMAC_RWMR_DEFAULT 0x1000a200 254 #define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_128_2048 255 #define EMAC_TMR1_DEFAULT 0x88810000 256 #else 257 #define EMAC_RWMR_DEFAULT 0x0f002000 258 #define EMAC_TMR0_DEFAULT 0x00000000 259 #define EMAC_TMR1_DEFAULT 0x380f0000 260 #endif /* CONFIG_440GP */ 261 262 #endif 263