1 /*
2 * PReP pci functions.
3 * Originally by Gary Thomas
4 * rewritten and updated by Cort Dougan (cort@cs.nmt.edu)
5 *
6 * The motherboard routes/maps will disappear shortly. -- Cort
7 */
8
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14
15 #include <asm/sections.h>
16 #include <asm/byteorder.h>
17 #include <asm/io.h>
18 #include <asm/ptrace.h>
19 #include <asm/prom.h>
20 #include <asm/pci-bridge.h>
21 #include <asm/residual.h>
22 #include <asm/processor.h>
23 #include <asm/irq.h>
24 #include <asm/machdep.h>
25 #include <asm/open_pic.h>
26
27 #define MAX_DEVNR 22
28
29 extern void (*setup_ibm_pci)(char *irq_lo, char *irq_hi);
30
31 /* Which PCI interrupt line does a given device [slot] use? */
32 /* Note: This really should be two dimensional based in slot/pin used */
33 static unsigned char *Motherboard_map;
34 unsigned char *Motherboard_map_name;
35
36 /* How is the 82378 PIRQ mapping setup? */
37 static unsigned char *Motherboard_routes;
38
39 static void (*Motherboard_non0)(struct pci_dev *);
40
41 static void Powerplus_Map_Non0(struct pci_dev *);
42
43 /* Used for Motorola to store system config register */
44 static unsigned long *ProcInfo;
45
46 /* Tables for known hardware */
47
48 /* Motorola PowerStackII - Utah */
49 static char Utah_pci_IRQ_map[23] __prepdata =
50 {
51 0, /* Slot 0 - unused */
52 0, /* Slot 1 - unused */
53 5, /* Slot 2 - SCSI - NCR825A */
54 0, /* Slot 3 - unused */
55 1, /* Slot 4 - Ethernet - DEC2114x */
56 0, /* Slot 5 - unused */
57 3, /* Slot 6 - PCI Card slot #1 */
58 4, /* Slot 7 - PCI Card slot #2 */
59 5, /* Slot 8 - PCI Card slot #3 */
60 5, /* Slot 9 - PCI Bridge */
61 /* added here in case we ever support PCI bridges */
62 /* Secondary PCI bus cards are at slot-9,6 & slot-9,7 */
63 0, /* Slot 10 - unused */
64 0, /* Slot 11 - unused */
65 5, /* Slot 12 - SCSI - NCR825A */
66 0, /* Slot 13 - unused */
67 3, /* Slot 14 - enet */
68 0, /* Slot 15 - unused */
69 2, /* Slot 16 - unused */
70 3, /* Slot 17 - unused */
71 5, /* Slot 18 - unused */
72 0, /* Slot 19 - unused */
73 0, /* Slot 20 - unused */
74 0, /* Slot 21 - unused */
75 0, /* Slot 22 - unused */
76 };
77
78 static char Utah_pci_IRQ_routes[] __prepdata =
79 {
80 0, /* Line 0 - Unused */
81 9, /* Line 1 */
82 10, /* Line 2 */
83 11, /* Line 3 */
84 14, /* Line 4 */
85 15, /* Line 5 */
86 };
87
88 /* Motorola PowerStackII - Omaha */
89 /* no integrated SCSI or ethernet */
90 static char Omaha_pci_IRQ_map[23] __prepdata =
91 {
92 0, /* Slot 0 - unused */
93 0, /* Slot 1 - unused */
94 3, /* Slot 2 - Winbond EIDE */
95 0, /* Slot 3 - unused */
96 0, /* Slot 4 - unused */
97 0, /* Slot 5 - unused */
98 1, /* Slot 6 - PCI slot 1 */
99 2, /* Slot 7 - PCI slot 2 */
100 3, /* Slot 8 - PCI slot 3 */
101 4, /* Slot 9 - PCI slot 4 */ /* needs indirect access */
102 0, /* Slot 10 - unused */
103 0, /* Slot 11 - unused */
104 0, /* Slot 12 - unused */
105 0, /* Slot 13 - unused */
106 0, /* Slot 14 - unused */
107 0, /* Slot 15 - unused */
108 1, /* Slot 16 - PCI slot 1 */
109 2, /* Slot 17 - PCI slot 2 */
110 3, /* Slot 18 - PCI slot 3 */
111 4, /* Slot 19 - PCI slot 4 */ /* needs indirect access */
112 0,
113 0,
114 0,
115 };
116
117 static char Omaha_pci_IRQ_routes[] __prepdata =
118 {
119 0, /* Line 0 - Unused */
120 9, /* Line 1 */
121 11, /* Line 2 */
122 14, /* Line 3 */
123 15 /* Line 4 */
124 };
125
126 /* Motorola PowerStack */
127 static char Blackhawk_pci_IRQ_map[19] __prepdata =
128 {
129 0, /* Slot 0 - unused */
130 0, /* Slot 1 - unused */
131 0, /* Slot 2 - unused */
132 0, /* Slot 3 - unused */
133 0, /* Slot 4 - unused */
134 0, /* Slot 5 - unused */
135 0, /* Slot 6 - unused */
136 0, /* Slot 7 - unused */
137 0, /* Slot 8 - unused */
138 0, /* Slot 9 - unused */
139 0, /* Slot 10 - unused */
140 0, /* Slot 11 - unused */
141 3, /* Slot 12 - SCSI */
142 0, /* Slot 13 - unused */
143 1, /* Slot 14 - Ethernet */
144 0, /* Slot 15 - unused */
145 1, /* Slot P7 */
146 2, /* Slot P6 */
147 3, /* Slot P5 */
148 };
149
150 static char Blackhawk_pci_IRQ_routes[] __prepdata =
151 {
152 0, /* Line 0 - Unused */
153 9, /* Line 1 */
154 11, /* Line 2 */
155 15, /* Line 3 */
156 15 /* Line 4 */
157 };
158
159 /* Motorola Mesquite */
160 static char Mesquite_pci_IRQ_map[23] __prepdata =
161 {
162 0, /* Slot 0 - unused */
163 0, /* Slot 1 - unused */
164 0, /* Slot 2 - unused */
165 0, /* Slot 3 - unused */
166 0, /* Slot 4 - unused */
167 0, /* Slot 5 - unused */
168 0, /* Slot 6 - unused */
169 0, /* Slot 7 - unused */
170 0, /* Slot 8 - unused */
171 0, /* Slot 9 - unused */
172 0, /* Slot 10 - unused */
173 0, /* Slot 11 - unused */
174 0, /* Slot 12 - unused */
175 0, /* Slot 13 - unused */
176 2, /* Slot 14 - Ethernet */
177 0, /* Slot 15 - unused */
178 3, /* Slot 16 - PMC */
179 0, /* Slot 17 - unused */
180 0, /* Slot 18 - unused */
181 0, /* Slot 19 - unused */
182 0, /* Slot 20 - unused */
183 0, /* Slot 21 - unused */
184 0, /* Slot 22 - unused */
185 };
186
187 /* Motorola Sitka */
188 static char Sitka_pci_IRQ_map[21] __prepdata =
189 {
190 0, /* Slot 0 - unused */
191 0, /* Slot 1 - unused */
192 0, /* Slot 2 - unused */
193 0, /* Slot 3 - unused */
194 0, /* Slot 4 - unused */
195 0, /* Slot 5 - unused */
196 0, /* Slot 6 - unused */
197 0, /* Slot 7 - unused */
198 0, /* Slot 8 - unused */
199 0, /* Slot 9 - unused */
200 0, /* Slot 10 - unused */
201 0, /* Slot 11 - unused */
202 0, /* Slot 12 - unused */
203 0, /* Slot 13 - unused */
204 2, /* Slot 14 - Ethernet */
205 0, /* Slot 15 - unused */
206 9, /* Slot 16 - PMC 1 */
207 12, /* Slot 17 - PMC 2 */
208 0, /* Slot 18 - unused */
209 0, /* Slot 19 - unused */
210 4, /* Slot 20 - NT P2P bridge */
211 };
212
213 /* Motorola MTX */
214 static char MTX_pci_IRQ_map[23] __prepdata =
215 {
216 0, /* Slot 0 - unused */
217 0, /* Slot 1 - unused */
218 0, /* Slot 2 - unused */
219 0, /* Slot 3 - unused */
220 0, /* Slot 4 - unused */
221 0, /* Slot 5 - unused */
222 0, /* Slot 6 - unused */
223 0, /* Slot 7 - unused */
224 0, /* Slot 8 - unused */
225 0, /* Slot 9 - unused */
226 0, /* Slot 10 - unused */
227 0, /* Slot 11 - unused */
228 3, /* Slot 12 - SCSI */
229 0, /* Slot 13 - unused */
230 2, /* Slot 14 - Ethernet */
231 0, /* Slot 15 - unused */
232 9, /* Slot 16 - PCI/PMC slot 1 */
233 10, /* Slot 17 - PCI/PMC slot 2 */
234 11, /* Slot 18 - PCI slot 3 */
235 0, /* Slot 19 - unused */
236 0, /* Slot 20 - unused */
237 0, /* Slot 21 - unused */
238 0, /* Slot 22 - unused */
239 };
240
241 /* Motorola MTX Plus */
242 /* Secondary bus interrupt routing is not supported yet */
243 static char MTXplus_pci_IRQ_map[23] __prepdata =
244 {
245 0, /* Slot 0 - unused */
246 0, /* Slot 1 - unused */
247 0, /* Slot 2 - unused */
248 0, /* Slot 3 - unused */
249 0, /* Slot 4 - unused */
250 0, /* Slot 5 - unused */
251 0, /* Slot 6 - unused */
252 0, /* Slot 7 - unused */
253 0, /* Slot 8 - unused */
254 0, /* Slot 9 - unused */
255 0, /* Slot 10 - unused */
256 0, /* Slot 11 - unused */
257 3, /* Slot 12 - SCSI */
258 0, /* Slot 13 - unused */
259 2, /* Slot 14 - Ethernet 1 */
260 0, /* Slot 15 - unused */
261 9, /* Slot 16 - PCI slot 1P */
262 10, /* Slot 17 - PCI slot 2P */
263 11, /* Slot 18 - PCI slot 3P */
264 10, /* Slot 19 - Ethernet 2 */
265 0, /* Slot 20 - P2P Bridge */
266 0, /* Slot 21 - unused */
267 0, /* Slot 22 - unused */
268 };
269
270 static char Raven_pci_IRQ_routes[] __prepdata =
271 {
272 0, /* This is a dummy structure */
273 };
274
275 /* Motorola MVME16xx */
276 static char Genesis_pci_IRQ_map[16] __prepdata =
277 {
278 0, /* Slot 0 - unused */
279 0, /* Slot 1 - unused */
280 0, /* Slot 2 - unused */
281 0, /* Slot 3 - unused */
282 0, /* Slot 4 - unused */
283 0, /* Slot 5 - unused */
284 0, /* Slot 6 - unused */
285 0, /* Slot 7 - unused */
286 0, /* Slot 8 - unused */
287 0, /* Slot 9 - unused */
288 0, /* Slot 10 - unused */
289 0, /* Slot 11 - unused */
290 3, /* Slot 12 - SCSI */
291 0, /* Slot 13 - unused */
292 1, /* Slot 14 - Ethernet */
293 0, /* Slot 15 - unused */
294 };
295
296 static char Genesis_pci_IRQ_routes[] __prepdata =
297 {
298 0, /* Line 0 - Unused */
299 10, /* Line 1 */
300 11, /* Line 2 */
301 14, /* Line 3 */
302 15 /* Line 4 */
303 };
304
305 static char Genesis2_pci_IRQ_map[23] __prepdata =
306 {
307 0, /* Slot 0 - unused */
308 0, /* Slot 1 - unused */
309 0, /* Slot 2 - unused */
310 0, /* Slot 3 - unused */
311 0, /* Slot 4 - unused */
312 0, /* Slot 5 - unused */
313 0, /* Slot 6 - unused */
314 0, /* Slot 7 - unused */
315 0, /* Slot 8 - unused */
316 0, /* Slot 9 - unused */
317 0, /* Slot 10 - Ethernet */
318 0, /* Slot 11 - Universe PCI - VME Bridge */
319 3, /* Slot 12 - unused */
320 0, /* Slot 13 - unused */
321 2, /* Slot 14 - SCSI */
322 0, /* Slot 15 - unused */
323 9, /* Slot 16 - PMC 1 */
324 12, /* Slot 17 - pci */
325 11, /* Slot 18 - pci */
326 10, /* Slot 19 - pci */
327 0, /* Slot 20 - pci */
328 0, /* Slot 21 - unused */
329 0, /* Slot 22 - unused */
330 };
331
332 /* Motorola Series-E */
333 static char Comet_pci_IRQ_map[23] __prepdata =
334 {
335 0, /* Slot 0 - unused */
336 0, /* Slot 1 - unused */
337 0, /* Slot 2 - unused */
338 0, /* Slot 3 - unused */
339 0, /* Slot 4 - unused */
340 0, /* Slot 5 - unused */
341 0, /* Slot 6 - unused */
342 0, /* Slot 7 - unused */
343 0, /* Slot 8 - unused */
344 0, /* Slot 9 - unused */
345 0, /* Slot 10 - unused */
346 0, /* Slot 11 - unused */
347 3, /* Slot 12 - SCSI */
348 0, /* Slot 13 - unused */
349 1, /* Slot 14 - Ethernet */
350 0, /* Slot 15 - unused */
351 1, /* Slot 16 - PCI slot 1 */
352 2, /* Slot 17 - PCI slot 2 */
353 3, /* Slot 18 - PCI slot 3 */
354 4, /* Slot 19 - PCI bridge */
355 0,
356 0,
357 0,
358 };
359
360 static char Comet_pci_IRQ_routes[] __prepdata =
361 {
362 0, /* Line 0 - Unused */
363 10, /* Line 1 */
364 11, /* Line 2 */
365 14, /* Line 3 */
366 15 /* Line 4 */
367 };
368
369 /* Motorola Series-EX */
370 static char Comet2_pci_IRQ_map[23] __prepdata =
371 {
372 0, /* Slot 0 - unused */
373 0, /* Slot 1 - unused */
374 3, /* Slot 2 - SCSI - NCR825A */
375 0, /* Slot 3 - unused */
376 1, /* Slot 4 - Ethernet - DEC2104X */
377 0, /* Slot 5 - unused */
378 1, /* Slot 6 - PCI slot 1 */
379 2, /* Slot 7 - PCI slot 2 */
380 3, /* Slot 8 - PCI slot 3 */
381 4, /* Slot 9 - PCI bridge */
382 0, /* Slot 10 - unused */
383 0, /* Slot 11 - unused */
384 3, /* Slot 12 - SCSI - NCR825A */
385 0, /* Slot 13 - unused */
386 1, /* Slot 14 - Ethernet - DEC2104X */
387 0, /* Slot 15 - unused */
388 1, /* Slot 16 - PCI slot 1 */
389 2, /* Slot 17 - PCI slot 2 */
390 3, /* Slot 18 - PCI slot 3 */
391 4, /* Slot 19 - PCI bridge */
392 0,
393 0,
394 0,
395 };
396
397 static char Comet2_pci_IRQ_routes[] __prepdata =
398 {
399 0, /* Line 0 - Unused */
400 10, /* Line 1 */
401 11, /* Line 2 */
402 14, /* Line 3 */
403 15, /* Line 4 */
404 };
405
406 /*
407 * ibm 830 (and 850?).
408 * This is actually based on the Carolina motherboard
409 * -- Cort
410 */
411 static char ibm8xx_pci_IRQ_map[23] __prepdata = {
412 0, /* Slot 0 - unused */
413 0, /* Slot 1 - unused */
414 0, /* Slot 2 - unused */
415 0, /* Slot 3 - unused */
416 0, /* Slot 4 - unused */
417 0, /* Slot 5 - unused */
418 0, /* Slot 6 - unused */
419 0, /* Slot 7 - unused */
420 0, /* Slot 8 - unused */
421 0, /* Slot 9 - unused */
422 0, /* Slot 10 - unused */
423 0, /* Slot 11 - FireCoral */
424 4, /* Slot 12 - Ethernet PCIINTD# */
425 2, /* Slot 13 - PCI Slot #2 */
426 2, /* Slot 14 - S3 Video PCIINTD# */
427 0, /* Slot 15 - onboard SCSI (INDI) [1] */
428 3, /* Slot 16 - NCR58C810 RS6000 Only PCIINTC# */
429 0, /* Slot 17 - unused */
430 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */
431 0, /* Slot 19 - unused */
432 0, /* Slot 20 - unused */
433 0, /* Slot 21 - unused */
434 2, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
435 };
436
437 static char ibm8xx_pci_IRQ_routes[] __prepdata = {
438 0, /* Line 0 - unused */
439 15, /* Line 1 */
440 15, /* Line 2 */
441 15, /* Line 3 */
442 15, /* Line 4 */
443 };
444
445 /*
446 * a 6015 ibm board
447 * -- Cort
448 */
449 static char ibm6015_pci_IRQ_map[23] __prepdata = {
450 0, /* Slot 0 - unused */
451 0, /* Slot 1 - unused */
452 0, /* Slot 2 - unused */
453 0, /* Slot 3 - unused */
454 0, /* Slot 4 - unused */
455 0, /* Slot 5 - unused */
456 0, /* Slot 6 - unused */
457 0, /* Slot 7 - unused */
458 0, /* Slot 8 - unused */
459 0, /* Slot 9 - unused */
460 0, /* Slot 10 - unused */
461 0, /* Slot 11 - */
462 1, /* Slot 12 - SCSI */
463 2, /* Slot 13 - */
464 2, /* Slot 14 - */
465 1, /* Slot 15 - */
466 1, /* Slot 16 - */
467 0, /* Slot 17 - */
468 2, /* Slot 18 - */
469 0, /* Slot 19 - */
470 0, /* Slot 20 - */
471 0, /* Slot 21 - */
472 2, /* Slot 22 - */
473 };
474
475 static char ibm6015_pci_IRQ_routes[] __prepdata = {
476 0, /* Line 0 - unused */
477 13, /* Line 1 */
478 15, /* Line 2 */
479 15, /* Line 3 */
480 15, /* Line 4 */
481 };
482
483
484 /* IBM Nobis and Thinkpad 850 */
485 static char Nobis_pci_IRQ_map[23] __prepdata ={
486 0, /* Slot 0 - unused */
487 0, /* Slot 1 - unused */
488 0, /* Slot 2 - unused */
489 0, /* Slot 3 - unused */
490 0, /* Slot 4 - unused */
491 0, /* Slot 5 - unused */
492 0, /* Slot 6 - unused */
493 0, /* Slot 7 - unused */
494 0, /* Slot 8 - unused */
495 0, /* Slot 9 - unused */
496 0, /* Slot 10 - unused */
497 0, /* Slot 11 - unused */
498 3, /* Slot 12 - SCSI */
499 0, /* Slot 13 - unused */
500 0, /* Slot 14 - unused */
501 0, /* Slot 15 - unused */
502 };
503
504 static char Nobis_pci_IRQ_routes[] __prepdata = {
505 0, /* Line 0 - Unused */
506 13, /* Line 1 */
507 13, /* Line 2 */
508 13, /* Line 3 */
509 13 /* Line 4 */
510 };
511
512 /*
513 * IBM RS/6000 43p/140 -- paulus
514 * XXX we should get all this from the residual data
515 */
516 static char ibm43p_pci_IRQ_map[23] __prepdata = {
517 0, /* Slot 0 - unused */
518 0, /* Slot 1 - unused */
519 0, /* Slot 2 - unused */
520 0, /* Slot 3 - unused */
521 0, /* Slot 4 - unused */
522 0, /* Slot 5 - unused */
523 0, /* Slot 6 - unused */
524 0, /* Slot 7 - unused */
525 0, /* Slot 8 - unused */
526 0, /* Slot 9 - unused */
527 0, /* Slot 10 - unused */
528 0, /* Slot 11 - FireCoral ISA bridge */
529 6, /* Slot 12 - Ethernet */
530 0, /* Slot 13 - openpic */
531 0, /* Slot 14 - unused */
532 0, /* Slot 15 - unused */
533 7, /* Slot 16 - NCR58C825a onboard scsi */
534 0, /* Slot 17 - unused */
535 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */
536 0, /* Slot 19 - unused */
537 0, /* Slot 20 - unused */
538 0, /* Slot 21 - unused */
539 1, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
540 };
541
542 static char ibm43p_pci_IRQ_routes[] __prepdata = {
543 0, /* Line 0 - unused */
544 15, /* Line 1 */
545 15, /* Line 2 */
546 15, /* Line 3 */
547 15, /* Line 4 */
548 };
549
550 /* Motorola PowerPlus architecture PCI IRQ tables */
551 /* Interrupt line values for INTA-D on primary/secondary MPIC inputs */
552
553 struct powerplus_irq_list
554 {
555 unsigned char primary[4]; /* INT A-D */
556 unsigned char secondary[4]; /* INT A-D */
557 };
558
559 /*
560 * For standard PowerPlus boards, bus 0 PCI INTs A-D are routed to
561 * OpenPIC inputs 9-12. PCI INTs A-D from the on board P2P bridge
562 * are routed to OpenPIC inputs 5-8. These values are offset by
563 * 16 in the table to reflect the Linux kernel interrupt value.
564 */
565 struct powerplus_irq_list Powerplus_pci_IRQ_list __prepdata =
566 {
567 {25, 26, 27, 28},
568 {21, 22, 23, 24}
569 };
570
571 /*
572 * For the MCP750 (system slot board), cPCI INTs A-D are routed to
573 * OpenPIC inputs 8-11 and the PMC INTs A-D are routed to OpenPIC
574 * input 3. On a hot swap MCP750, the companion card PCI INTs A-D
575 * are routed to OpenPIC inputs 12-15. These values are offset by
576 * 16 in the table to reflect the Linux kernel interrupt value.
577 */
578 struct powerplus_irq_list Mesquite_pci_IRQ_list __prepdata =
579 {
580 {24, 25, 26, 27},
581 {28, 29, 30, 31}
582 };
583
584 /*
585 * This table represents the standard PCI swizzle defined in the
586 * PCI bus specification.
587 */
588 static unsigned char prep_pci_intpins[4][4] __prepdata =
589 {
590 { 1, 2, 3, 4}, /* Buses 0, 4, 8, ... */
591 { 2, 3, 4, 1}, /* Buses 1, 5, 9, ... */
592 { 3, 4, 1, 2}, /* Buses 2, 6, 10 ... */
593 { 4, 1, 2, 3}, /* Buses 3, 7, 11 ... */
594 };
595
596 /* We have to turn on LEVEL mode for changed IRQ's */
597 /* All PCI IRQ's need to be level mode, so this should be something
598 * other than hard-coded as well... IRQ's are individually mappable
599 * to either edge or level.
600 */
601
602 /*
603 * 8259 edge/level control definitions
604 */
605 #define ISA8259_M_ELCR 0x4d0
606 #define ISA8259_S_ELCR 0x4d1
607
608 #define ELCRS_INT15_LVL 0x80
609 #define ELCRS_INT14_LVL 0x40
610 #define ELCRS_INT12_LVL 0x10
611 #define ELCRS_INT11_LVL 0x08
612 #define ELCRS_INT10_LVL 0x04
613 #define ELCRS_INT9_LVL 0x02
614 #define ELCRS_INT8_LVL 0x01
615 #define ELCRM_INT7_LVL 0x80
616 #define ELCRM_INT5_LVL 0x20
617
618 #define CFGPTR(dev) (0x80800000 | (1<<(dev>>3)) | ((dev&7)<<8) | offset)
619 #define DEVNO(dev) (dev>>3)
620
621 #define cfg_read(val, addr, type, op) *val = op((type)(addr))
622 #define cfg_write(val, addr, type, op) op((type *)(addr), (val))
623
624 #define cfg_read_bad(val, size) *val = bad_##size;
625 #define cfg_write_bad(val, size)
626
627 #define bad_byte 0xff
628 #define bad_word 0xffff
629 #define bad_dword 0xffffffffU
630
631 #define PREP_PCI_OP(rw, size, type, op) \
632 static int __prep \
633 prep_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
634 { \
635 if ((dev->bus->number != 0) || (DEVNO(dev->devfn) > MAX_DEVNR)) \
636 { \
637 cfg_##rw##_bad(val, size) \
638 return PCIBIOS_DEVICE_NOT_FOUND; \
639 } \
640 cfg_##rw(val, CFGPTR(dev->devfn), type, op); \
641 return PCIBIOS_SUCCESSFUL; \
642 }
643
644 PREP_PCI_OP(read, byte, u8 *, in_8)
645 PREP_PCI_OP(read, word, u16 *, in_le16)
646 PREP_PCI_OP(read, dword, u32 *, in_le32)
647 PREP_PCI_OP(write, byte, u8, out_8)
648 PREP_PCI_OP(write, word, u16, out_le16)
649 PREP_PCI_OP(write, dword, u32, out_le32)
650
651 static struct pci_ops prep_pci_ops =
652 {
653 prep_read_config_byte,
654 prep_read_config_word,
655 prep_read_config_dword,
656 prep_write_config_byte,
657 prep_write_config_word,
658 prep_write_config_dword
659 };
660
661 #define MOTOROLA_CPUTYPE_REG 0x800
662 #define MOTOROLA_BASETYPE_REG 0x803
663 #define MPIC_RAVEN_ID 0x48010000
664 #define MPIC_HAWK_ID 0x48030000
665 #define MOT_PROC2_BIT 0x800
666
667 static u_char prep_openpic_initsenses[] __initdata = {
668 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
669 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_FALCN_ECC_ERR */
670 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_ETHERNET */
671 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
672 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_GRAPHICS */
673 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
674 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
675 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
676 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
677 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
678 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
679 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
680 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
681 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
682 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
683 };
684
685 #define MOT_RAVEN_PRESENT 0x1
686 #define MOT_HAWK_PRESENT 0x2
687
688 int mot_entry = -1;
689 int prep_keybd_present = 1;
690 int MotMPIC;
691 int mot_multi;
692
693 int __init
raven_init(void)694 raven_init(void)
695 {
696 unsigned int devid;
697 unsigned int pci_membase;
698 unsigned char base_mod;
699
700 /* Check to see if the Raven chip exists. */
701 if ( _prep_type != _PREP_Motorola) {
702 OpenPIC_Addr = NULL;
703 return 0;
704 }
705
706 /* Check to see if this board is a type that might have a Raven. */
707 if ((inb(MOTOROLA_CPUTYPE_REG) & 0xF0) != 0xE0) {
708 OpenPIC_Addr = NULL;
709 return 0;
710 }
711
712 /* Check the first PCI device to see if it is a Raven. */
713 early_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &devid);
714
715 switch (devid & 0xffff0000) {
716 case MPIC_RAVEN_ID:
717 MotMPIC = MOT_RAVEN_PRESENT;
718 break;
719 case MPIC_HAWK_ID:
720 MotMPIC = MOT_HAWK_PRESENT;
721 break;
722 default:
723 OpenPIC_Addr = NULL;
724 return 0;
725 }
726
727
728 /* Read the memory base register. */
729 early_read_config_dword(0, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
730
731 if (pci_membase == 0) {
732 OpenPIC_Addr = NULL;
733 return 0;
734 }
735
736 /* Map the Raven MPIC registers to virtual memory. */
737 OpenPIC_Addr = ioremap(pci_membase+0xC0000000, 0x22000);
738
739 OpenPIC_InitSenses = prep_openpic_initsenses;
740 OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses);
741
742 ppc_md.get_irq = openpic_get_irq;
743
744 /* If raven is present on Motorola store the system config register
745 * for later use.
746 */
747 ProcInfo = (unsigned long *)ioremap(0xfef80400, 4);
748
749 /* Indicate to system if this is a multiprocessor board */
750 if (!(*ProcInfo & MOT_PROC2_BIT)) {
751 mot_multi = 1;
752 }
753
754 /* This is a hack. If this is a 2300 or 2400 mot board then there is
755 * no keyboard controller and we have to indicate that.
756 */
757 base_mod = inb(MOTOROLA_BASETYPE_REG);
758 if ((MotMPIC == MOT_HAWK_PRESENT) || (base_mod == 0xF9) ||
759 (base_mod == 0xFA) || (base_mod == 0xE1))
760 prep_keybd_present = 0;
761
762 return 1;
763 }
764
765 struct mot_info {
766 int cpu_type; /* 0x100 mask assumes for Raven and Hawk boards that the level/edge are set */
767 /* 0x200 if this board has a Hawk chip. */
768 int base_type;
769 int max_cpu; /* ored with 0x80 if this board should be checked for multi CPU */
770 const char *name;
771 unsigned char *map;
772 unsigned char *routes;
773 void (*map_non0_bus)(struct pci_dev *); /* For boards with more than bus 0 devices. */
774 struct powerplus_irq_list *pci_irq_list; /* List of PCI MPIC inputs */
775 unsigned char secondary_bridge_devfn; /* devfn of secondary bus transparent bridge */
776 } mot_info[] __prepdata = {
777 {0x300, 0x00, 0x00, "MVME 2400", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
778 {0x010, 0x00, 0x00, "Genesis", Genesis_pci_IRQ_map, Genesis_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
779 {0x020, 0x00, 0x00, "Powerstack (Series E)", Comet_pci_IRQ_map, Comet_pci_IRQ_routes, NULL, NULL, 0x00},
780 {0x040, 0x00, 0x00, "Blackhawk (Powerstack)", Blackhawk_pci_IRQ_map, Blackhawk_pci_IRQ_routes, NULL, NULL, 0x00},
781 {0x050, 0x00, 0x00, "Omaha (PowerStack II Pro3000)", Omaha_pci_IRQ_map, Omaha_pci_IRQ_routes, NULL, NULL, 0x00},
782 {0x060, 0x00, 0x00, "Utah (Powerstack II Pro4000)", Utah_pci_IRQ_map, Utah_pci_IRQ_routes, NULL, NULL, 0x00},
783 {0x0A0, 0x00, 0x00, "Powerstack (Series EX)", Comet2_pci_IRQ_map, Comet2_pci_IRQ_routes, NULL, NULL, 0x00},
784 {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xFF},
785 {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", Sitka_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
786 {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xC0},
787 {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0},
788 {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0},
789 {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
790 {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
791 {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
792 {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
793 {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
794 {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
795 {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
796 {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
797 {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
798 {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
799 {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
800 {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
801 {0x1E0, 0xFF, 0x00, "MVME 1600-001 or 1600-011", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
802 {0x000, 0x00, 0x00, "", NULL, NULL, NULL, NULL, 0x00}
803 };
804
805 void __init
ibm_prep_init(void)806 ibm_prep_init(void)
807 {
808 #ifdef CONFIG_PREP_RESIDUAL
809 u32 addr, real_addr, len;
810 PPC_DEVICE *mpic;
811 PnP_TAG_PACKET *pkt;
812
813 /* Use the PReP residual data to determine if an OpenPIC is
814 * present. If so, get the large vendor packet which will
815 * tell us the base address and length in memory.
816 * If we are successful, ioremap the memory area and set
817 * OpenPIC_Addr (this indicates that the OpenPIC was found).
818 */
819 mpic = residual_find_device(-1, NULL, SystemPeripheral,
820 ProgrammableInterruptController, MPIC, 0);
821 if (!mpic)
822 return;
823
824 pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap +
825 mpic->AllocatedOffset, 9, 0);
826
827 if (!pkt)
828 return;
829
830 #define p pkt->L4_Pack.L4_Data.L4_PPCPack
831 if (!((p.PPCData[0] == 2) && (p.PPCData[1] == 32)))
832 return; /* not a 32-bit memory address */
833
834 real_addr = ld_le32((unsigned int *) (p.PPCData + 4));
835 if (real_addr == 0xffffffff)
836 return;
837
838 /* Adjust address to be as seen by CPU */
839 addr = real_addr + PREP_ISA_MEM_BASE;
840
841 len = ld_le32((unsigned int *) (p.PPCData + 12));
842 if (!len)
843 return;
844 #undef p
845 OpenPIC_Addr = ioremap(addr, len);
846 ppc_md.get_irq = openpic_get_irq;
847
848 OpenPIC_InitSenses = prep_openpic_initsenses;
849 OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses);
850
851 printk(KERN_INFO "MPIC at 0x%08x (0x%08x), length 0x%08x "
852 "mapped to 0x%p\n", addr, real_addr, len, OpenPIC_Addr);
853 #endif
854 }
855
856 static void __init
ibm43p_pci_map_non0(struct pci_dev * dev)857 ibm43p_pci_map_non0(struct pci_dev *dev)
858 {
859 unsigned char intpin;
860 static unsigned char bridge_intrs[4] = { 3, 4, 5, 8 };
861
862 if (dev == NULL)
863 return;
864 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin);
865 if (intpin < 1 || intpin > 4)
866 return;
867 intpin = (PCI_SLOT(dev->devfn) + intpin - 1) & 3;
868 dev->irq = openpic_to_irq(bridge_intrs[intpin]);
869 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
870 }
871
872 void __init
prep_sandalfoot_setup_pci(char * irq_edge_mask_lo,char * irq_edge_mask_hi)873 prep_sandalfoot_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
874 {
875 Motherboard_map_name = "IBM 6015/7020 (Sandalfoot/Sandalbow)";
876 Motherboard_map = ibm6015_pci_IRQ_map;
877 Motherboard_routes = ibm6015_pci_IRQ_routes;
878 *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
879 *irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */
880 }
881
882 void __init
prep_thinkpad_setup_pci(char * irq_edge_mask_lo,char * irq_edge_mask_hi)883 prep_thinkpad_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
884 {
885 Motherboard_map_name = "IBM Thinkpad 850/860";
886 Motherboard_map = Nobis_pci_IRQ_map;
887 Motherboard_routes = Nobis_pci_IRQ_routes;
888 *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
889 *irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */
890 }
891
892 void __init
prep_carolina_setup_pci(char * irq_edge_mask_lo,char * irq_edge_mask_hi)893 prep_carolina_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
894 {
895 Motherboard_map_name = "IBM 7248, PowerSeries 830/850 (Carolina)";
896 Motherboard_map = ibm8xx_pci_IRQ_map;
897 Motherboard_routes = ibm8xx_pci_IRQ_routes;
898 *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
899 *irq_edge_mask_hi = 0xA4; /* irq's 10, 13, 15 level-triggered */
900 }
901
902 void __init
prep_tiger1_setup_pci(char * irq_edge_mask_lo,char * irq_edge_mask_hi)903 prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
904 {
905 Motherboard_map_name = "IBM 43P-140 (Tiger1)";
906 Motherboard_map = ibm43p_pci_IRQ_map;
907 Motherboard_routes = ibm43p_pci_IRQ_routes;
908 Motherboard_non0 = ibm43p_pci_map_non0;
909 *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
910 *irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */
911 }
912
913 void __init
prep_route_pci_interrupts(void)914 prep_route_pci_interrupts(void)
915 {
916 unsigned char *ibc_pirq = (unsigned char *)0x80800860;
917 unsigned char *ibc_pcicon = (unsigned char *)0x80800840;
918 int i;
919
920 if ( _prep_type == _PREP_Motorola)
921 {
922 unsigned short irq_mode;
923 unsigned char cpu_type;
924 unsigned char base_mod;
925 int entry;
926
927 cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
928 base_mod = inb(MOTOROLA_BASETYPE_REG);
929
930 for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
931 if (mot_info[entry].cpu_type & 0x200) { /* Check for Hawk chip */
932 if (!(MotMPIC & MOT_HAWK_PRESENT))
933 continue;
934 } else { /* Check non hawk boards */
935 if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
936 continue;
937
938 if (mot_info[entry].base_type == 0) {
939 mot_entry = entry;
940 break;
941 }
942
943 if (mot_info[entry].base_type != base_mod)
944 continue;
945 }
946
947 if (!(mot_info[entry].max_cpu & 0x80)) {
948 mot_entry = entry;
949 break;
950 }
951
952 /* processor 1 not present and max processor zero indicated */
953 if ((*ProcInfo & MOT_PROC2_BIT) && !(mot_info[entry].max_cpu & 0x7f)) {
954 mot_entry = entry;
955 break;
956 }
957
958 /* processor 1 present and max processor zero indicated */
959 if (!(*ProcInfo & MOT_PROC2_BIT) && (mot_info[entry].max_cpu & 0x7f)) {
960 mot_entry = entry;
961 break;
962 }
963 }
964
965 if (mot_entry == -1) /* No particular cpu type found - assume Blackhawk */
966 mot_entry = 3;
967
968 Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
969 Motherboard_map = mot_info[mot_entry].map;
970 Motherboard_routes = mot_info[mot_entry].routes;
971 Motherboard_non0 = mot_info[mot_entry].map_non0_bus;
972
973 if (!(mot_info[entry].cpu_type & 0x100)) {
974 /* AJF adjust level/edge control according to routes */
975 irq_mode = 0;
976 for (i = 1; i <= 4; i++)
977 irq_mode |= ( 1 << Motherboard_routes[i] );
978 outb( irq_mode & 0xff, 0x4d0 );
979 outb( (irq_mode >> 8) & 0xff, 0x4d1 );
980 }
981 } else if ( _prep_type == _PREP_IBM ) {
982 unsigned char irq_edge_mask_lo, irq_edge_mask_hi;
983
984 setup_ibm_pci(&irq_edge_mask_lo, &irq_edge_mask_hi);
985
986 outb(inb(0x04d0)|irq_edge_mask_lo, 0x4d0); /* primary 8259 */
987 outb(inb(0x04d1)|irq_edge_mask_hi, 0x4d1); /* cascaded 8259 */
988 } else {
989 printk("No known machine pci routing!\n");
990 return;
991 }
992
993 /* Set up mapping from slots */
994 for (i = 1; i <= 4; i++)
995 ibc_pirq[i-1] = Motherboard_routes[i];
996 /* Enable PCI interrupts */
997 *ibc_pcicon |= 0x20;
998 }
999
1000 void __init
prep_pib_init(void)1001 prep_pib_init(void)
1002 {
1003 unsigned char reg;
1004 unsigned short short_reg;
1005
1006 struct pci_dev *dev = NULL;
1007
1008 if (( _prep_type == _PREP_Motorola) && (OpenPIC_Addr)) {
1009 /*
1010 * Perform specific configuration for the Via Tech or
1011 * or Winbond PCI-ISA-Bridge part.
1012 */
1013 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
1014 PCI_DEVICE_ID_VIA_82C586_1, dev))) {
1015 /*
1016 * PPCBUG does not set the enable bits
1017 * for the IDE device. Force them on here.
1018 */
1019 pci_read_config_byte(dev, 0x40, ®);
1020
1021 reg |= 0x03; /* IDE: Chip Enable Bits */
1022 pci_write_config_byte(dev, 0x40, reg);
1023 }
1024 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
1025 PCI_DEVICE_ID_VIA_82C586_2,
1026 dev)) && (dev->devfn = 0x5a)) {
1027 /* Force correct USB interrupt */
1028 dev->irq = 11;
1029 pci_write_config_byte(dev,
1030 PCI_INTERRUPT_LINE,
1031 dev->irq);
1032 }
1033 if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
1034 PCI_DEVICE_ID_WINBOND_83C553, dev))) {
1035 /* Clear PCI Interrupt Routing Control Register. */
1036 short_reg = 0x0000;
1037 pci_write_config_word(dev, 0x44, short_reg);
1038 if (OpenPIC_Addr){
1039 /* Route IDE interrupts to IRQ 14 */
1040 reg = 0xEE;
1041 pci_write_config_byte(dev, 0x43, reg);
1042 }
1043 }
1044 }
1045
1046 if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
1047 PCI_DEVICE_ID_WINBOND_82C105, dev))){
1048 if (OpenPIC_Addr){
1049 /*
1050 * Disable LEGIRQ mode so PCI INTS are routed
1051 * directly to the 8259 and enable both channels
1052 */
1053 pci_write_config_dword(dev, 0x40, 0x10ff0033);
1054
1055 /* Force correct IDE interrupt */
1056 dev->irq = 14;
1057 pci_write_config_byte(dev,
1058 PCI_INTERRUPT_LINE,
1059 dev->irq);
1060 } else {
1061 /* Enable LEGIRQ for PCI INT -> 8259 IRQ routing */
1062 pci_write_config_dword(dev, 0x40, 0x10ff08a1);
1063 }
1064 }
1065 }
1066
1067 static void __init
Powerplus_Map_Non0(struct pci_dev * dev)1068 Powerplus_Map_Non0(struct pci_dev *dev)
1069 {
1070 struct pci_bus *pbus; /* Parent bus structure pointer */
1071 struct pci_dev *tdev = dev; /* Temporary device structure */
1072 unsigned int devnum; /* Accumulated device number */
1073 unsigned char intline; /* Linux interrupt value */
1074 unsigned char intpin; /* PCI interrupt pin */
1075
1076 /* Check for valid PCI dev pointer */
1077 if (dev == NULL) return;
1078
1079 /* Initialize bridge IDSEL variable */
1080 devnum = PCI_SLOT(tdev->devfn);
1081
1082 /* Read the interrupt pin of the device and adjust for indexing */
1083 pcibios_read_config_byte(dev->bus->number, dev->devfn,
1084 PCI_INTERRUPT_PIN, &intpin);
1085
1086 /* If device doesn't request an interrupt, return */
1087 if ( (intpin < 1) || (intpin > 4) )
1088 return;
1089
1090 intpin--;
1091
1092 /*
1093 * Walk up to bus 0, adjusting the interrupt pin for the standard
1094 * PCI bus swizzle.
1095 */
1096 do {
1097 intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1;
1098 pbus = tdev->bus; /* up one level */
1099 tdev = pbus->self;
1100 devnum = PCI_SLOT(tdev->devfn);
1101 } while(tdev->bus->number);
1102
1103 /* Use the primary interrupt inputs by default */
1104 intline = mot_info[mot_entry].pci_irq_list->primary[intpin];
1105
1106 /*
1107 * If the board has secondary interrupt inputs, walk the bus and
1108 * note the devfn of the bridge from bus 0. If it is the same as
1109 * the devfn of the bus bridge with secondary inputs, use those.
1110 * Otherwise, assume it's a PMC site and get the interrupt line
1111 * value from the interrupt routing table.
1112 */
1113 if (mot_info[mot_entry].secondary_bridge_devfn) {
1114 pbus = dev->bus;
1115
1116 while (pbus->primary != 0)
1117 pbus = pbus->parent;
1118
1119 if ((pbus->self)->devfn != 0xA0) {
1120 if ((pbus->self)->devfn == mot_info[mot_entry].secondary_bridge_devfn)
1121 intline = mot_info[mot_entry].pci_irq_list->secondary[intpin];
1122 else {
1123 if ((char *)(mot_info[mot_entry].map) == (char *)Mesquite_pci_IRQ_map)
1124 intline = mot_info[mot_entry].map[((pbus->self)->devfn)/8] + 16;
1125 else {
1126 int i;
1127 for (i=0;i<3;i++)
1128 intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1;
1129 intline = mot_info[mot_entry].pci_irq_list->primary[intpin];
1130 }
1131 }
1132 }
1133 }
1134
1135 /* Write calculated interrupt value to header and device list */
1136 dev->irq = intline;
1137 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, (u8)dev->irq);
1138 }
1139
1140 void __init
prep_pcibios_fixup(void)1141 prep_pcibios_fixup(void)
1142 {
1143 struct pci_dev *dev;
1144
1145 prep_route_pci_interrupts();
1146
1147 printk("Setting PCI interrupts for a \"%s\"\n", Motherboard_map_name);
1148 if (OpenPIC_Addr) {
1149 /* PCI interrupts are controlled by the OpenPIC */
1150 pci_for_each_dev(dev) {
1151 if (dev->bus->number == 0) {
1152 dev->irq = openpic_to_irq(Motherboard_map[PCI_SLOT(dev->devfn)]);
1153 pcibios_write_config_byte(dev->bus->number, dev->devfn, PCI_INTERRUPT_LINE, dev->irq);
1154 } else {
1155 if (Motherboard_non0 != NULL)
1156 Motherboard_non0(dev);
1157 }
1158 }
1159
1160 /* Setup the Winbond or Via PIB */
1161 prep_pib_init();
1162
1163 return;
1164 }
1165
1166 pci_for_each_dev(dev) {
1167 /*
1168 * Use our old hard-coded kludge to figure out what
1169 * irq this device uses. This is necessary on things
1170 * without residual data. -- Cort
1171 */
1172 unsigned char d = PCI_SLOT(dev->devfn);
1173 dev->irq = Motherboard_routes[Motherboard_map[d]];
1174 #if 0
1175 for ( i = 0 ; i <= 5 ; i++ ) {
1176 /*
1177 * Relocate PCI I/O resources if necessary so the
1178 * standard 256MB BAT covers them.
1179 */
1180 if ( (pci_resource_flags(dev, i) & IORESOURCE_IO) &&
1181 (dev->resource[i].start > 0x10000000)) {
1182 printk("Relocating PCI address %lx -> %lx\n",
1183 dev->resource[i].start,
1184 (dev->resource[i].start &
1185 0x00FFFFFF)| 0x01000000);
1186 dev->resource[i].start =
1187 (dev->resource[i].start & 0x00FFFFFF)
1188 | 0x01000000;
1189 pci_write_config_dword(dev,
1190 PCI_BASE_ADDRESS_0 + (i*0x4),
1191 dev->resource[i].start);
1192 dev->resource[i].end =
1193 (dev->resource[i].end & 0x00FFFFFF)
1194 | 0x01000000;
1195 }
1196 }
1197 #endif
1198 #if 0
1199 /*
1200 * If we have residual data and if it knows about this
1201 * device ask it what the irq is.
1202 * -- Cort
1203 */
1204 ppcd = residual_find_device_id( ~0L, dev->device,
1205 -1,-1,-1, 0);
1206 #endif
1207 }
1208 }
1209
1210 static void __init
prep_pcibios_after_init(void)1211 prep_pcibios_after_init(void)
1212 {
1213 struct pci_dev *dev;
1214
1215 /* If there is a WD 90C, reset the IO BAR to 0x0 (it started that
1216 * way, but the PCI layer relocated it because it thought 0x0 was
1217 * invalid for a BAR).
1218 * If you don't do this, the card's VGA base will be <IO BAR>+0xc0000
1219 * instead of 0xc0000. vgacon.c (for example) is completely unaware of
1220 * this little quirk.
1221 */
1222 dev = pci_find_device(PCI_VENDOR_ID_WD, PCI_DEVICE_ID_WD_90C, NULL);
1223 if (dev) {
1224 dev->resource[1].end -= dev->resource[1].start;
1225 dev->resource[1].start = 0;
1226 /* tell the hardware */
1227 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x0);
1228 }
1229 }
1230
1231 static void __init
prep_init_resource(struct resource * res,unsigned long start,unsigned long end,int flags)1232 prep_init_resource(struct resource *res, unsigned long start,
1233 unsigned long end, int flags)
1234 {
1235 res->flags = flags;
1236 res->start = start;
1237 res->end = end;
1238 res->name = "PCI host bridge";
1239 res->parent = NULL;
1240 res->sibling = NULL;
1241 res->child = NULL;
1242 }
1243
1244 void __init
prep_find_bridges(void)1245 prep_find_bridges(void)
1246 {
1247 struct pci_controller* hose;
1248
1249 hose = pcibios_alloc_controller();
1250 if (!hose)
1251 return;
1252
1253 hose->first_busno = 0;
1254 hose->last_busno = 0xff;
1255 hose->pci_mem_offset = PREP_ISA_MEM_BASE;
1256 hose->io_base_phys = PREP_ISA_IO_BASE;
1257 hose->io_base_virt = (void *)0x80000000; /* see prep_map_io() */
1258 prep_init_resource(&hose->io_resource, 0, 0x007fffff, IORESOURCE_IO);
1259 prep_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfeffffff,
1260 IORESOURCE_MEM);
1261 hose->ops = &prep_pci_ops;
1262
1263 printk("PReP architecture\n");
1264 #ifdef CONFIG_PREP_RESIDUAL
1265 {
1266 PPC_DEVICE *hostbridge;
1267
1268 hostbridge = residual_find_device(PROCESSORDEVICE, NULL,
1269 BridgeController, PCIBridge, -1, 0);
1270 if (hostbridge &&
1271 hostbridge->DeviceId.Interface == PCIBridgeIndirect) {
1272 PnP_TAG_PACKET * pkt;
1273 pkt = PnP_find_large_vendor_packet(
1274 res->DevicePnPHeap+hostbridge->AllocatedOffset,
1275 3, 0);
1276 if(pkt) {
1277 #define p pkt->L4_Pack.L4_Data.L4_PPCPack
1278 setup_indirect_pci(hose,
1279 ld_le32((unsigned *) (p.PPCData)),
1280 ld_le32((unsigned *) (p.PPCData+8)));
1281 #undef p
1282 } else
1283 setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc);
1284 }
1285 }
1286 #endif /* CONFIG_PREP_RESIDUAL */
1287
1288 ppc_md.pcibios_fixup = prep_pcibios_fixup;
1289 ppc_md.pcibios_after_init = prep_pcibios_after_init;
1290 }
1291