1 #ifndef _B44_H 2 #define _B44_H 3 4 /* Register layout. */ 5 #define B44_DEVCTRL 0x0000UL /* Device Control */ 6 #define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */ 7 #define DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */ 8 #define DEVCTRL_EPR 0x00008000 /* EPHY Reset */ 9 #define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */ 10 #define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */ 11 #define DEVCTRL_PADDR 0x0007c000 /* PHY Address */ 12 #define DEVCTRL_PADDR_SHIFT 18 13 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */ 14 #define B44_WKUP_LEN 0x0010UL /* Wakeup Length */ 15 #define WKUP_LEN_P0_MASK 0x0000007f /* Pattern 0 */ 16 #define WKUP_LEN_D0 0x00000080 17 #define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */ 18 #define WKUP_LEN_P1_SHIFT 8 19 #define WKUP_LEN_D1 0x00008000 20 #define WKUP_LEN_P2_MASK 0x007f0000 /* Pattern 2 */ 21 #define WKUP_LEN_P2_SHIFT 16 22 #define WKUP_LEN_D2 0x00000000 23 #define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */ 24 #define WKUP_LEN_P3_SHIFT 24 25 #define WKUP_LEN_D3 0x80000000 26 #define B44_ISTAT 0x0020UL /* Interrupt Status */ 27 #define ISTAT_PME 0x00000040 /* Power Management Event */ 28 #define ISTAT_TO 0x00000080 /* General Purpose Timeout */ 29 #define ISTAT_DSCE 0x00000400 /* Descriptor Error */ 30 #define ISTAT_DATAE 0x00000800 /* Data Error */ 31 #define ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ 32 #define ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ 33 #define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ 34 #define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ 35 #define ISTAT_RX 0x00010000 /* RX Interrupt */ 36 #define ISTAT_TX 0x01000000 /* TX Interrupt */ 37 #define ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ 38 #define ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ 39 #define ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ 40 #define ISTAT_ERRORS (ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|ISTAT_RDU|ISTAT_RFO|ISTAT_TFU) 41 #define B44_IMASK 0x0024UL /* Interrupt Mask */ 42 #define IMASK_DEF (ISTAT_ERRORS | ISTAT_TO | ISTAT_RX | ISTAT_TX) 43 #define B44_GPTIMER 0x0028UL /* General Purpose Timer */ 44 #define B44_FILT_ADDR 0x0090UL /* ENET Filter Address */ 45 #define B44_FILT_DATA 0x0094UL /* ENET Filter Data */ 46 #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */ 47 #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */ 48 #define B44_MAC_CTRL 0x00A8UL /* MAC Control */ 49 #define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ 50 #define MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ 51 #define MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected */ 52 #define MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */ 53 #define MAC_CTRL_PHY_LEDCTRL_SHIFT 5 54 #define B44_MAC_FLOW 0x00ACUL /* MAC Flow Control */ 55 #define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */ 56 #define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */ 57 #define B44_RCV_LAZY 0x0100UL /* Lazy Interrupt Control */ 58 #define RCV_LAZY_TO_MASK 0x00ffffff /* Timeout */ 59 #define RCV_LAZY_FC_MASK 0xff000000 /* Frame Count */ 60 #define RCV_LAZY_FC_SHIFT 24 61 #define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */ 62 #define DMATX_CTRL_ENABLE 0x00000001 /* Enable */ 63 #define DMATX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ 64 #define DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ 65 #define DMATX_CTRL_FAIRPRIOR 0x00000008 /* Fair Priority */ 66 #define DMATX_CTRL_FLUSH 0x00000010 /* Flush Request */ 67 #define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Address */ 68 #define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Descriptor */ 69 #define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */ 70 #define DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 71 #define DMATX_STAT_SMASK 0x0000f000 /* State Mask */ 72 #define DMATX_STAT_SDISABLED 0x00000000 /* State Disabled */ 73 #define DMATX_STAT_SACTIVE 0x00001000 /* State Active */ 74 #define DMATX_STAT_SIDLE 0x00002000 /* State Idle Wait */ 75 #define DMATX_STAT_SSTOPPED 0x00003000 /* State Stopped */ 76 #define DMATX_STAT_SSUSP 0x00004000 /* State Suspend Pending */ 77 #define DMATX_STAT_EMASK 0x000f0000 /* Error Mask */ 78 #define DMATX_STAT_ENONE 0x00000000 /* Error None */ 79 #define DMATX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 80 #define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ 81 #define DMATX_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ 82 #define DMATX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 83 #define DMATX_STAT_FLUSHED 0x00100000 /* Flushed */ 84 #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */ 85 #define DMARX_CTRL_ENABLE 0x00000001 /* Enable */ 86 #define DMARX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ 87 #define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ 88 #define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */ 89 #define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Descriptor */ 90 #define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */ 91 #define DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 92 #define DMARX_STAT_SMASK 0x0000f000 /* State Mask */ 93 #define DMARX_STAT_SDISABLED 0x00000000 /* State Disbaled */ 94 #define DMARX_STAT_SACTIVE 0x00001000 /* State Active */ 95 #define DMARX_STAT_SIDLE 0x00002000 /* State Idle Wait */ 96 #define DMARX_STAT_SSTOPPED 0x00003000 /* State Stopped */ 97 #define DMARX_STAT_EMASK 0x000f0000 /* Error Mask */ 98 #define DMARX_STAT_ENONE 0x00000000 /* Error None */ 99 #define DMARX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 100 #define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */ 101 #define DMARX_STAT_EBEBW 0x00030000 /* Error Bus Error on Buffer Write */ 102 #define DMARX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 103 #define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */ 104 #define DMAFIFO_AD_OMASK 0x0000ffff /* Offset Mask */ 105 #define DMAFIFO_AD_SMASK 0x000f0000 /* Select Mask */ 106 #define DMAFIFO_AD_SXDD 0x00000000 /* Select Transmit DMA Data */ 107 #define DMAFIFO_AD_SXDP 0x00010000 /* Select Transmit DMA Pointers */ 108 #define DMAFIFO_AD_SRDD 0x00040000 /* Select Receive DMA Data */ 109 #define DMAFIFO_AD_SRDP 0x00050000 /* Select Receive DMA Pointers */ 110 #define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */ 111 #define DMAFIFO_AD_SXFP 0x00090000 /* Select Transmit FIFO Pointers */ 112 #define DMAFIFO_AD_SRFD 0x000c0000 /* Select Receive FIFO Data */ 113 #define DMAFIFO_AD_SRFP 0x000c0000 /* Select Receive FIFO Pointers */ 114 #define B44_DMAFIFO_LO 0x0224UL /* DMA FIFO Diag Low Data */ 115 #define B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */ 116 #define B44_RXCONFIG 0x0400UL /* EMAC RX Config */ 117 #define RXCONFIG_DBCAST 0x00000001 /* Disable Broadcast */ 118 #define RXCONFIG_ALLMULTI 0x00000002 /* Accept All Multicast */ 119 #define RXCONFIG_NORX_WHILE_TX 0x00000004 /* Receive Disable While Transmitting */ 120 #define RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */ 121 #define RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */ 122 #define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */ 123 #define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ 124 #define RXCONFIG_RFILT 0x00000080 /* Reject Filter */ 125 #define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */ 126 #define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */ 127 #define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */ 128 #define MDIO_CTRL_MAXF_MASK 0x0000007f /* MDC Frequency */ 129 #define MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */ 130 #define B44_MDIO_DATA 0x0414UL /* EMAC MDIO Data */ 131 #define MDIO_DATA_DATA 0x0000ffff /* R/W Data */ 132 #define MDIO_DATA_TA_MASK 0x00030000 /* Turnaround Value */ 133 #define MDIO_DATA_TA_SHIFT 16 134 #define MDIO_TA_VALID 2 135 #define MDIO_DATA_RA_MASK 0x007c0000 /* Register Address */ 136 #define MDIO_DATA_RA_SHIFT 18 137 #define MDIO_DATA_PMD_MASK 0x0f800000 /* Physical Media Device */ 138 #define MDIO_DATA_PMD_SHIFT 23 139 #define MDIO_DATA_OP_MASK 0x30000000 /* Opcode */ 140 #define MDIO_DATA_OP_SHIFT 28 141 #define MDIO_OP_WRITE 1 142 #define MDIO_OP_READ 2 143 #define MDIO_DATA_SB_MASK 0xc0000000 /* Start Bits */ 144 #define MDIO_DATA_SB_SHIFT 30 145 #define MDIO_DATA_SB_START 0x40000000 /* Start Of Frame */ 146 #define B44_EMAC_IMASK 0x0418UL /* EMAC Interrupt Mask */ 147 #define B44_EMAC_ISTAT 0x041CUL /* EMAC Interrupt Status */ 148 #define EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ 149 #define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ 150 #define EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ 151 #define B44_CAM_DATA_LO 0x0420UL /* EMAC CAM Data Low */ 152 #define B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */ 153 #define CAM_DATA_HI_VALID 0x00010000 /* Valid Bit */ 154 #define B44_CAM_CTRL 0x0428UL /* EMAC CAM Control */ 155 #define CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */ 156 #define CAM_CTRL_MSEL 0x00000002 /* Mask Select */ 157 #define CAM_CTRL_READ 0x00000004 /* Read */ 158 #define CAM_CTRL_WRITE 0x00000008 /* Read */ 159 #define CAM_CTRL_INDEX_MASK 0x003f0000 /* Index Mask */ 160 #define CAM_CTRL_INDEX_SHIFT 16 161 #define CAM_CTRL_BUSY 0x80000000 /* CAM Busy */ 162 #define B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */ 163 #define ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */ 164 #define ENET_CTRL_DISABLE 0x00000002 /* EMAC Disable */ 165 #define ENET_CTRL_SRST 0x00000004 /* EMAC Soft Reset */ 166 #define ENET_CTRL_EPSEL 0x00000008 /* External PHY Select */ 167 #define B44_TX_CTRL 0x0430UL /* EMAC TX Control */ 168 #define TX_CTRL_DUPLEX 0x00000001 /* Full Duplex */ 169 #define TX_CTRL_FMODE 0x00000002 /* Flow Mode */ 170 #define TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */ 171 #define TX_CTRL_SMALL_SLOT 0x00000008 /* Small Slottime */ 172 #define B44_TX_WMARK 0x0434UL /* EMAC TX Watermark */ 173 #define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */ 174 #define MIB_CTRL_CLR_ON_READ 0x00000001 /* Autoclear on Read */ 175 #define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */ 176 #define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */ 177 #define B44_TX_O 0x0508UL /* MIB TX Octets */ 178 #define B44_TX_P 0x050CUL /* MIB TX Packets */ 179 #define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */ 180 #define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */ 181 #define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */ 182 #define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Packets */ 183 #define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Packets */ 184 #define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Packets */ 185 #define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Packets */ 186 #define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Packets */ 187 #define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */ 188 #define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */ 189 #define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */ 190 #define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */ 191 #define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */ 192 #define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */ 193 #define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */ 194 #define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */ 195 #define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */ 196 #define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */ 197 #define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */ 198 #define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */ 199 #define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */ 200 #define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */ 201 #define B44_RX_O 0x0588UL /* MIB RX Octets */ 202 #define B44_RX_P 0x058CUL /* MIB RX Packets */ 203 #define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */ 204 #define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */ 205 #define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */ 206 #define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Packets */ 207 #define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Packets */ 208 #define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Packets */ 209 #define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Packets */ 210 #define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Packets */ 211 #define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */ 212 #define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */ 213 #define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */ 214 #define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */ 215 #define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */ 216 #define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */ 217 #define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */ 218 #define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */ 219 #define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */ 220 #define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */ 221 #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */ 222 #define B44_SBIPSFLAG 0x0F08UL /* SB Initiator Port OCP Slave Flag */ 223 #define SBIPSFLAG_IMASK1 0x0000003f /* Which sbflags --> mips interrupt 1 */ 224 #define SBIPSFLAG_ISHIFT1 0 225 #define SBIPSFLAG_IMASK2 0x00003f00 /* Which sbflags --> mips interrupt 2 */ 226 #define SBIPSFLAG_ISHIFT2 8 227 #define SBIPSFLAG_IMASK3 0x003f0000 /* Which sbflags --> mips interrupt 3 */ 228 #define SBIPSFLAG_ISHIFT3 16 229 #define SBIPSFLAG_IMASK4 0x3f000000 /* Which sbflags --> mips interrupt 4 */ 230 #define SBIPSFLAG_ISHIFT4 24 231 #define B44_SBTPSFLAG 0x0F18UL /* SB Target Port OCP Slave Flag */ 232 #define SBTPS_NUM0_MASK 0x0000003f 233 #define SBTPS_F0EN0 0x00000040 234 #define B44_SBADMATCH3 0x0F60UL /* SB Address Match 3 */ 235 #define B44_SBADMATCH2 0x0F68UL /* SB Address Match 2 */ 236 #define B44_SBADMATCH1 0x0F70UL /* SB Address Match 1 */ 237 #define B44_SBIMSTATE 0x0F90UL /* SB Initiator Agent State */ 238 #define SBIMSTATE_PC 0x0000000f /* Pipe Count */ 239 #define SBIMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */ 240 #define SBIMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */ 241 #define SBIMSTATE_AP_TS 0x00000010 /* Use timeslices only */ 242 #define SBIMSTATE_AP_TK 0x00000020 /* Use token only */ 243 #define SBIMSTATE_AP_RSV 0x00000030 /* Reserved */ 244 #define SBIMSTATE_IBE 0x00020000 /* In Band Error */ 245 #define SBIMSTATE_TO 0x00040000 /* Timeout */ 246 #define B44_SBINTVEC 0x0F94UL /* SB Interrupt Mask */ 247 #define SBINTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ 248 #define SBINTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ 249 #define SBINTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ 250 #define SBINTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ 251 #define SBINTVEC_USB 0x00000010 /* Enable interrupts for usb */ 252 #define SBINTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ 253 #define SBINTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ 254 #define B44_SBTMSLOW 0x0F98UL /* SB Target State Low */ 255 #define SBTMSLOW_RESET 0x00000001 /* Reset */ 256 #define SBTMSLOW_REJECT 0x00000002 /* Reject */ 257 #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ 258 #define SBTMSLOW_FGC 0x00020000 /* Force Gated Clocks On */ 259 #define SBTMSLOW_PE 0x40000000 /* Power Management Enable */ 260 #define SBTMSLOW_BE 0x80000000 /* BIST Enable */ 261 #define B44_SBTMSHIGH 0x0F9CUL /* SB Target State High */ 262 #define SBTMSHIGH_SERR 0x00000001 /* S-error */ 263 #define SBTMSHIGH_INT 0x00000002 /* Interrupt */ 264 #define SBTMSHIGH_BUSY 0x00000004 /* Busy */ 265 #define SBTMSHIGH_GCR 0x20000000 /* Gated Clock Request */ 266 #define SBTMSHIGH_BISTF 0x40000000 /* BIST Failed */ 267 #define SBTMSHIGH_BISTD 0x80000000 /* BIST Done */ 268 #define B44_SBBWA0 0x0FA0UL /* SB Bandwidth Allocation Table 0 */ 269 #define SBBWA0_TAB0_MASK 0x0000ffff /* Lookup Table 0 */ 270 #define SBBWA0_TAB0_SHIFT 0 271 #define SBBWA0_TAB1_MASK 0xffff0000 /* Lookup Table 0 */ 272 #define SBBWA0_TAB1_SHIFT 16 273 #define B44_SBIMCFGLOW 0x0FA8UL /* SB Initiator Configuration Low */ 274 #define SBIMCFGLOW_STO_MASK 0x00000003 /* Service Timeout */ 275 #define SBIMCFGLOW_RTO_MASK 0x00000030 /* Request Timeout */ 276 #define SBIMCFGLOW_RTO_SHIFT 4 277 #define SBIMCFGLOW_CID_MASK 0x00ff0000 /* Connection ID */ 278 #define SBIMCFGLOW_CID_SHIFT 16 279 #define B44_SBIMCFGHIGH 0x0FACUL /* SB Initiator Configuration High */ 280 #define SBIMCFGHIGH_IEM_MASK 0x0000000c /* Inband Error Mode */ 281 #define SBIMCFGHIGH_TEM_MASK 0x00000030 /* Timeout Error Mode */ 282 #define SBIMCFGHIGH_TEM_SHIFT 4 283 #define SBIMCFGHIGH_BEM_MASK 0x000000c0 /* Bus Error Mode */ 284 #define SBIMCFGHIGH_BEM_SHIFT 6 285 #define B44_SBADMATCH0 0x0FB0UL /* SB Address Match 0 */ 286 #define SBADMATCH0_TYPE_MASK 0x00000003 /* Address Type */ 287 #define SBADMATCH0_AD64 0x00000004 /* Reserved */ 288 #define SBADMATCH0_AI0_MASK 0x000000f8 /* Type0 Size */ 289 #define SBADMATCH0_AI0_SHIFT 3 290 #define SBADMATCH0_AI1_MASK 0x000001f8 /* Type1 Size */ 291 #define SBADMATCH0_AI1_SHIFT 3 292 #define SBADMATCH0_AI2_MASK 0x000001f8 /* Type2 Size */ 293 #define SBADMATCH0_AI2_SHIFT 3 294 #define SBADMATCH0_ADEN 0x00000400 /* Enable */ 295 #define SBADMATCH0_ADNEG 0x00000800 /* Negative Decode */ 296 #define SBADMATCH0_BS0_MASK 0xffffff00 /* Type0 Base Address */ 297 #define SBADMATCH0_BS0_SHIFT 8 298 #define SBADMATCH0_BS1_MASK 0xfffff000 /* Type1 Base Address */ 299 #define SBADMATCH0_BS1_SHIFT 12 300 #define SBADMATCH0_BS2_MASK 0xffff0000 /* Type2 Base Address */ 301 #define SBADMATCH0_BS2_SHIFT 16 302 #define B44_SBTMCFGLOW 0x0FB8UL /* SB Target Configuration Low */ 303 #define SBTMCFGLOW_CD_MASK 0x000000ff /* Clock Divide Mask */ 304 #define SBTMCFGLOW_CO_MASK 0x0000f800 /* Clock Offset Mask */ 305 #define SBTMCFGLOW_CO_SHIFT 11 306 #define SBTMCFGLOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */ 307 #define SBTMCFGLOW_IF_SHIFT 18 308 #define SBTMCFGLOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */ 309 #define SBTMCFGLOW_IM_SHIFT 24 310 #define B44_SBTMCFGHIGH 0x0FBCUL /* SB Target Configuration High */ 311 #define SBTMCFGHIGH_BM_MASK 0x00000003 /* Busy Mode */ 312 #define SBTMCFGHIGH_RM_MASK 0x0000000C /* Retry Mode */ 313 #define SBTMCFGHIGH_RM_SHIFT 2 314 #define SBTMCFGHIGH_SM_MASK 0x00000030 /* Stop Mode */ 315 #define SBTMCFGHIGH_SM_SHIFT 4 316 #define SBTMCFGHIGH_EM_MASK 0x00000300 /* Error Mode */ 317 #define SBTMCFGHIGH_EM_SHIFT 8 318 #define SBTMCFGHIGH_IM_MASK 0x00000c00 /* Interrupt Mode */ 319 #define SBTMCFGHIGH_IM_SHIFT 10 320 #define B44_SBBCFG 0x0FC0UL /* SB Broadcast Configuration */ 321 #define SBBCFG_LAT_MASK 0x00000003 /* SB Latency */ 322 #define SBBCFG_MAX0_MASK 0x000f0000 /* MAX Counter 0 */ 323 #define SBBCFG_MAX0_SHIFT 16 324 #define SBBCFG_MAX1_MASK 0x00f00000 /* MAX Counter 1 */ 325 #define SBBCFG_MAX1_SHIFT 20 326 #define B44_SBBSTATE 0x0FC8UL /* SB Broadcast State */ 327 #define SBBSTATE_SRD 0x00000001 /* ST Reg Disable */ 328 #define SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */ 329 #define B44_SBACTCNFG 0x0FD8UL /* SB Activate Configuration */ 330 #define B44_SBFLAGST 0x0FE8UL /* SB Current SBFLAGS */ 331 #define B44_SBIDLOW 0x0FF8UL /* SB Identification Low */ 332 #define SBIDLOW_CS_MASK 0x00000003 /* Config Space Mask */ 333 #define SBIDLOW_AR_MASK 0x00000038 /* Num Address Ranges Supported */ 334 #define SBIDLOW_AR_SHIFT 3 335 #define SBIDLOW_SYNCH 0x00000040 /* Sync */ 336 #define SBIDLOW_INIT 0x00000080 /* Initiator */ 337 #define SBIDLOW_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */ 338 #define SBIDLOW_MINLAT_SHIFT 8 339 #define SBIDLOW_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */ 340 #define SBIDLOW_MAXLAT_SHIFT 12 341 #define SBIDLOW_FIRST 0x00010000 /* This Initiator is First */ 342 #define SBIDLOW_CW_MASK 0x000c0000 /* Cycle Counter Width */ 343 #define SBIDLOW_CW_SHIFT 18 344 #define SBIDLOW_TP_MASK 0x00f00000 /* Target Ports */ 345 #define SBIDLOW_TP_SHIFT 20 346 #define SBIDLOW_IP_MASK 0x0f000000 /* Initiator Ports */ 347 #define SBIDLOW_IP_SHIFT 24 348 #define B44_SBIDHIGH 0x0FFCUL /* SB Identification High */ 349 #define SBIDHIGH_RC_MASK 0x0000000f /* Revision Code */ 350 #define SBIDHIGH_CC_MASK 0x0000fff0 /* Core Code */ 351 #define SBIDHIGH_CC_SHIFT 4 352 #define SBIDHIGH_VC_MASK 0xffff0000 /* Vendor Code */ 353 #define SBIDHIGH_VC_SHIFT 16 354 355 #define CORE_CODE_ILINE20 0x801 356 #define CORE_CODE_SDRAM 0x803 357 #define CORE_CODE_PCI 0x804 358 #define CORE_CODE_MIPS 0x805 359 #define CORE_CODE_ENET 0x806 360 #define CORE_CODE_CODEC 0x807 361 #define CORE_CODE_USB 0x808 362 #define CORE_CODE_ILINE100 0x80a 363 #define CORE_CODE_EXTIF 0x811 364 365 /* SSB PCI config space registers. */ 366 #define SSB_BAR0_WIN 0x80 367 #define SSB_BAR1_WIN 0x84 368 #define SSB_SPROM_CONTROL 0x88 369 #define SSB_BAR1_CONTROL 0x8c 370 371 /* SSB core and hsot control registers. */ 372 #define SSB_CONTROL 0x0000UL 373 #define SSB_ARBCONTROL 0x0010UL 374 #define SSB_ISTAT 0x0020UL 375 #define SSB_IMASK 0x0024UL 376 #define SSB_MBOX 0x0028UL 377 #define SSB_BCAST_ADDR 0x0050UL 378 #define SSB_BCAST_DATA 0x0054UL 379 #define SSB_PCI_TRANS_0 0x0100UL 380 #define SSB_PCI_TRANS_1 0x0104UL 381 #define SSB_PCI_TRANS_2 0x0108UL 382 #define SSB_SPROM 0x0800UL 383 384 #define SSB_PCI_MEM 0x00000000 385 #define SSB_PCI_IO 0x00000001 386 #define SSB_PCI_CFG0 0x00000002 387 #define SSB_PCI_CFG1 0x00000003 388 #define SSB_PCI_PREF 0x00000004 389 #define SSB_PCI_BURST 0x00000008 390 #define SSB_PCI_MASK0 0xfc000000 391 #define SSB_PCI_MASK1 0xfc000000 392 #define SSB_PCI_MASK2 0xc0000000 393 394 #define br32(REG) readl(bp->regs + (REG)) 395 #define bw32(REG,VAL) writel((VAL), bp->regs + (REG)) 396 397 /* 4400 PHY registers */ 398 #define B44_MII_AUXCTRL 24 /* Auxiliary Control */ 399 #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */ 400 #define MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */ 401 #define MII_AUXCTRL_FORCED 0x0004 /* Forced 10/100 */ 402 #define B44_MII_ALEDCTRL 26 /* Activity LED */ 403 #define MII_ALEDCTRL_ALLMSK 0x7fff 404 #define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */ 405 #define MII_TLEDCTRL_ENABLE 0x0040 406 407 /* XXX Add this to mii.h */ 408 #ifndef ADVERTISE_PAUSE 409 #define ADVERTISE_PAUSE_CAP 0x0400 410 #endif 411 #ifndef ADVERTISE_PAUSE_ASYM 412 #define ADVERTISE_PAUSE_ASYM 0x0800 413 #endif 414 #ifndef LPA_PAUSE 415 #define LPA_PAUSE_CAP 0x0400 416 #endif 417 #ifndef LPA_PAUSE_ASYM 418 #define LPA_PAUSE_ASYM 0x0800 419 #endif 420 421 struct dma_desc { 422 u32 ctrl; 423 u32 addr; 424 }; 425 426 /* There are only 12 bits in the DMA engine for descriptor offsetting 427 * so the table must be aligned on a boundary of this. 428 */ 429 #define DMA_TABLE_BYTES 4096 430 431 #define DESC_CTRL_LEN 0x00001fff 432 #define DESC_CTRL_CMASK 0x0ff00000 /* Core specific bits */ 433 #define DESC_CTRL_EOT 0x10000000 /* End of Table */ 434 #define DESC_CTRL_IOC 0x20000000 /* Interrupt On Completion */ 435 #define DESC_CTRL_EOF 0x40000000 /* End of Frame */ 436 #define DESC_CTRL_SOF 0x80000000 /* Start of Frame */ 437 438 #define RX_COPY_THRESHOLD 256 439 440 struct rx_header { 441 u16 len; 442 u16 flags; 443 u16 pad[12]; 444 }; 445 #define RX_HEADER_LEN 28 446 447 #define RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ 448 #define RX_FLAG_CRCERR 0x00000002 /* CRC Error */ 449 #define RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ 450 #define RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ 451 #define RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ 452 #define RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ 453 #define RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ 454 #define RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ 455 #define RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ 456 #define RX_FLAG_ERRORS (RX_FLAG_ODD | RX_FLAG_SERR | RX_FLAG_CRCERR | RX_FLAG_OFIFO) 457 458 struct ring_info { 459 struct sk_buff *skb; 460 DECLARE_PCI_UNMAP_ADDR(mapping); 461 }; 462 463 #define B44_MCAST_TABLE_SIZE 32 464 465 /* SW copy of device statistics, kept up to date by periodic timer 466 * which probes HW values. Must have same relative layout as HW 467 * register above, because b44_stats_update depends upon this. 468 */ 469 struct b44_hw_stats { 470 u32 tx_good_octets, tx_good_pkts, tx_octets; 471 u32 tx_pkts, tx_broadcast_pkts, tx_multicast_pkts; 472 u32 tx_len_64, tx_len_65_to_127, tx_len_128_to_255; 473 u32 tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max; 474 u32 tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts; 475 u32 tx_underruns, tx_total_cols, tx_single_cols; 476 u32 tx_multiple_cols, tx_excessive_cols, tx_late_cols; 477 u32 tx_defered, tx_carrier_lost, tx_pause_pkts; 478 u32 __pad1[8]; 479 480 u32 rx_good_octets, rx_good_pkts, rx_octets; 481 u32 rx_pkts, rx_broadcast_pkts, rx_multicast_pkts; 482 u32 rx_len_64, rx_len_65_to_127, rx_len_128_to_255; 483 u32 rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max; 484 u32 rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts; 485 u32 rx_missed_pkts, rx_crc_align_errs, rx_undersize; 486 u32 rx_crc_errs, rx_align_errs, rx_symbol_errs; 487 u32 rx_pause_pkts, rx_nonpause_pkts; 488 }; 489 490 struct b44 { 491 spinlock_t lock; 492 493 u32 imask, istat; 494 495 struct dma_desc *rx_ring, *tx_ring; 496 497 u32 tx_prod, tx_cons; 498 u32 rx_prod, rx_cons; 499 500 struct ring_info *rx_buffers; 501 struct ring_info *tx_buffers; 502 503 u32 dma_offset; 504 u32 flags; 505 #define B44_FLAG_INIT_COMPLETE 0x00000001 506 #define B44_FLAG_BUGGY_TXPTR 0x00000002 507 #define B44_FLAG_REORDER_BUG 0x00000004 508 #define B44_FLAG_PAUSE_AUTO 0x00008000 509 #define B44_FLAG_FULL_DUPLEX 0x00010000 510 #define B44_FLAG_100_BASE_T 0x00020000 511 #define B44_FLAG_TX_PAUSE 0x00040000 512 #define B44_FLAG_RX_PAUSE 0x00080000 513 #define B44_FLAG_FORCE_LINK 0x00100000 514 #define B44_FLAG_ADV_10HALF 0x01000000 515 #define B44_FLAG_ADV_10FULL 0x02000000 516 #define B44_FLAG_ADV_100HALF 0x04000000 517 #define B44_FLAG_ADV_100FULL 0x08000000 518 #define B44_FLAG_INTERNAL_PHY 0x10000000 519 520 u32 rx_offset; 521 522 u32 msg_enable; 523 524 struct timer_list timer; 525 526 struct net_device_stats stats; 527 struct b44_hw_stats hw_stats; 528 529 unsigned long regs; 530 struct pci_dev *pdev; 531 struct net_device *dev; 532 533 dma_addr_t rx_ring_dma, tx_ring_dma; 534 535 u32 rx_pending; 536 u32 tx_pending; 537 u32 pci_cfg_state[64 / sizeof(u32)]; 538 u8 phy_addr; 539 u8 mdc_port; 540 u8 core_unit; 541 }; 542 543 #endif /* _B44_H */ 544