1 #ifndef _RADEON_H 2 #define _RADEON_H 3 4 5 #define RADEON_REGSIZE 0x4000 6 7 8 #define MM_INDEX 0x0000 9 #define MM_DATA 0x0004 10 #define BUS_CNTL 0x0030 11 #define HI_STAT 0x004C 12 #define BUS_CNTL1 0x0034 13 #define I2C_CNTL_1 0x0094 14 #define CONFIG_CNTL 0x00E0 15 #define CONFIG_MEMSIZE 0x00F8 16 #define CONFIG_APER_0_BASE 0x0100 17 #define CONFIG_APER_1_BASE 0x0104 18 #define CONFIG_APER_SIZE 0x0108 19 #define CONFIG_REG_1_BASE 0x010C 20 #define CONFIG_REG_APER_SIZE 0x0110 21 #define PAD_AGPINPUT_DELAY 0x0164 22 #define PAD_CTLR_STRENGTH 0x0168 23 #define PAD_CTLR_UPDATE 0x016C 24 #define AGP_CNTL 0x0174 25 #define BM_STATUS 0x0160 26 #define CAP0_TRIG_CNTL 0x0950 27 #define VIPH_CONTROL 0x0C40 28 #define VENDOR_ID 0x0F00 29 #define DEVICE_ID 0x0F02 30 #define COMMAND 0x0F04 31 #define STATUS 0x0F06 32 #define REVISION_ID 0x0F08 33 #define REGPROG_INF 0x0F09 34 #define SUB_CLASS 0x0F0A 35 #define BASE_CODE 0x0F0B 36 #define CACHE_LINE 0x0F0C 37 #define LATENCY 0x0F0D 38 #define HEADER 0x0F0E 39 #define BIST 0x0F0F 40 #define REG_MEM_BASE 0x0F10 41 #define REG_IO_BASE 0x0F14 42 #define REG_REG_BASE 0x0F18 43 #define ADAPTER_ID 0x0F2C 44 #define BIOS_ROM 0x0F30 45 #define CAPABILITIES_PTR 0x0F34 46 #define INTERRUPT_LINE 0x0F3C 47 #define INTERRUPT_PIN 0x0F3D 48 #define MIN_GRANT 0x0F3E 49 #define MAX_LATENCY 0x0F3F 50 #define ADAPTER_ID_W 0x0F4C 51 #define PMI_CAP_ID 0x0F50 52 #define PMI_NXT_CAP_PTR 0x0F51 53 #define PMI_PMC_REG 0x0F52 54 #define PM_STATUS 0x0F54 55 #define PMI_DATA 0x0F57 56 #define AGP_CAP_ID 0x0F58 57 #define AGP_STATUS 0x0F5C 58 #define AGP_COMMAND 0x0F60 59 #define AIC_CTRL 0x01D0 60 #define AIC_STAT 0x01D4 61 #define AIC_PT_BASE 0x01D8 62 #define AIC_LO_ADDR 0x01DC 63 #define AIC_HI_ADDR 0x01E0 64 #define AIC_TLB_ADDR 0x01E4 65 #define AIC_TLB_DATA 0x01E8 66 #define DAC_CNTL 0x0058 67 #define DAC_CNTL2 0x007c 68 #define CRTC_GEN_CNTL 0x0050 69 #define MEM_CNTL 0x0140 70 #define EXT_MEM_CNTL 0x0144 71 #define MC_AGP_LOCATION 0x014C 72 #define MEM_IO_CNTL_A0 0x0178 73 #define MEM_INIT_LATENCY_TIMER 0x0154 74 #define MEM_SDRAM_MODE_REG 0x0158 75 #define AGP_BASE 0x0170 76 #define MEM_IO_CNTL_A1 0x017C 77 #define MEM_IO_CNTL_B0 0x0180 78 #define MEM_IO_CNTL_B1 0x0184 79 #define MC_DEBUG 0x0188 80 #define MC_STATUS 0x0150 81 #define MEM_IO_OE_CNTL 0x018C 82 #define MC_FB_LOCATION 0x0148 83 #define HOST_PATH_CNTL 0x0130 84 #define MEM_VGA_WP_SEL 0x0038 85 #define MEM_VGA_RP_SEL 0x003C 86 #define HDP_DEBUG 0x0138 87 #define SW_SEMAPHORE 0x013C 88 #define CRTC2_GEN_CNTL 0x03f8 89 #define CRTC2_DISPLAY_BASE_ADDR 0x033c 90 #define SURFACE_CNTL 0x0B00 91 #define SURFACE0_LOWER_BOUND 0x0B04 92 #define SURFACE1_LOWER_BOUND 0x0B14 93 #define SURFACE2_LOWER_BOUND 0x0B24 94 #define SURFACE3_LOWER_BOUND 0x0B34 95 #define SURFACE4_LOWER_BOUND 0x0B44 96 #define SURFACE5_LOWER_BOUND 0x0B54 97 #define SURFACE6_LOWER_BOUND 0x0B64 98 #define SURFACE7_LOWER_BOUND 0x0B74 99 #define SURFACE0_UPPER_BOUND 0x0B08 100 #define SURFACE1_UPPER_BOUND 0x0B18 101 #define SURFACE2_UPPER_BOUND 0x0B28 102 #define SURFACE3_UPPER_BOUND 0x0B38 103 #define SURFACE4_UPPER_BOUND 0x0B48 104 #define SURFACE5_UPPER_BOUND 0x0B58 105 #define SURFACE6_UPPER_BOUND 0x0B68 106 #define SURFACE7_UPPER_BOUND 0x0B78 107 #define SURFACE0_INFO 0x0B0C 108 #define SURFACE1_INFO 0x0B1C 109 #define SURFACE2_INFO 0x0B2C 110 #define SURFACE3_INFO 0x0B3C 111 #define SURFACE4_INFO 0x0B4C 112 #define SURFACE5_INFO 0x0B5C 113 #define SURFACE6_INFO 0x0B6C 114 #define SURFACE7_INFO 0x0B7C 115 #define SURFACE_ACCESS_FLAGS 0x0BF8 116 #define SURFACE_ACCESS_CLR 0x0BFC 117 #define GEN_INT_CNTL 0x0040 118 #define GEN_INT_STATUS 0x0044 119 #define CRTC_EXT_CNTL 0x0054 120 #define RB3D_CNTL 0x1C3C 121 #define WAIT_UNTIL 0x1720 122 #define ISYNC_CNTL 0x1724 123 #define RBBM_GUICNTL 0x172C 124 #define RBBM_STATUS 0x0E40 125 #define RBBM_STATUS_alt_1 0x1740 126 #define RBBM_CNTL 0x00EC 127 #define RBBM_CNTL_alt_1 0x0E44 128 #define RBBM_SOFT_RESET 0x00F0 129 #define RBBM_SOFT_RESET_alt_1 0x0E48 130 #define NQWAIT_UNTIL 0x0E50 131 #define RBBM_DEBUG 0x0E6C 132 #define RBBM_CMDFIFO_ADDR 0x0E70 133 #define RBBM_CMDFIFO_DATAL 0x0E74 134 #define RBBM_CMDFIFO_DATAH 0x0E78 135 #define RBBM_CMDFIFO_STAT 0x0E7C 136 #define CRTC_STATUS 0x005C 137 #define GPIO_VGA_DDC 0x0060 138 #define GPIO_DVI_DDC 0x0064 139 #define GPIO_MONID 0x0068 140 #define GPIO_CRT2_DDC 0x006c 141 #define PALETTE_INDEX 0x00B0 142 #define PALETTE_DATA 0x00B4 143 #define PALETTE_30_DATA 0x00B8 144 #define CRTC_H_TOTAL_DISP 0x0200 145 #define CRTC_H_SYNC_STRT_WID 0x0204 146 #define CRTC_V_TOTAL_DISP 0x0208 147 #define CRTC_V_SYNC_STRT_WID 0x020C 148 #define CRTC_VLINE_CRNT_VLINE 0x0210 149 #define CRTC_CRNT_FRAME 0x0214 150 #define CRTC_GUI_TRIG_VLINE 0x0218 151 #define CRTC_DEBUG 0x021C 152 #define CRTC_OFFSET_RIGHT 0x0220 153 #define CRTC_OFFSET 0x0224 154 #define CRTC_OFFSET_CNTL 0x0228 155 #define CRTC_PITCH 0x022C 156 #define OVR_CLR 0x0230 157 #define OVR_WID_LEFT_RIGHT 0x0234 158 #define OVR_WID_TOP_BOTTOM 0x0238 159 #define DISPLAY_BASE_ADDR 0x023C 160 #define SNAPSHOT_VH_COUNTS 0x0240 161 #define SNAPSHOT_F_COUNT 0x0244 162 #define N_VIF_COUNT 0x0248 163 #define SNAPSHOT_VIF_COUNT 0x024C 164 #define FP_CRTC_H_TOTAL_DISP 0x0250 165 #define FP_CRTC_V_TOTAL_DISP 0x0254 166 #define CRT_CRTC_H_SYNC_STRT_WID 0x0258 167 #define CRT_CRTC_V_SYNC_STRT_WID 0x025C 168 #define CUR_OFFSET 0x0260 169 #define CUR_HORZ_VERT_POSN 0x0264 170 #define CUR_HORZ_VERT_OFF 0x0268 171 #define CUR_CLR0 0x026C 172 #define CUR_CLR1 0x0270 173 #define FP_HORZ_VERT_ACTIVE 0x0278 174 #define CRTC_MORE_CNTL 0x027C 175 #define DAC_EXT_CNTL 0x0280 176 #define FP_GEN_CNTL 0x0284 177 #define FP2_GEN_CNTL 0x0288 178 #define FP_HORZ_STRETCH 0x028C 179 #define FP_VERT_STRETCH 0x0290 180 #define FP_H_SYNC_STRT_WID 0x02C4 181 #define FP_V_SYNC_STRT_WID 0x02C8 182 #define AUX_WINDOW_HORZ_CNTL 0x02D8 183 #define AUX_WINDOW_VERT_CNTL 0x02DC 184 //#define DDA_CONFIG 0x02e0 185 //#define DDA_ON_OFF 0x02e4 186 #define DVI_I2C_CNTL_1 0x02e4 187 #define GRPH_BUFFER_CNTL 0x02F0 188 #define VGA_BUFFER_CNTL 0x02F4 189 #define OV0_Y_X_START 0x0400 190 #define OV0_Y_X_END 0x0404 191 #define OV0_PIPELINE_CNTL 0x0408 192 #define OV0_REG_LOAD_CNTL 0x0410 193 #define OV0_SCALE_CNTL 0x0420 194 #define OV0_V_INC 0x0424 195 #define OV0_P1_V_ACCUM_INIT 0x0428 196 #define OV0_P23_V_ACCUM_INIT 0x042C 197 #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 198 #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 199 #define OV0_BASE_ADDR 0x043C 200 #define OV0_VID_BUF0_BASE_ADRS 0x0440 201 #define OV0_VID_BUF1_BASE_ADRS 0x0444 202 #define OV0_VID_BUF2_BASE_ADRS 0x0448 203 #define OV0_VID_BUF3_BASE_ADRS 0x044C 204 #define OV0_VID_BUF4_BASE_ADRS 0x0450 205 #define OV0_VID_BUF5_BASE_ADRS 0x0454 206 #define OV0_VID_BUF_PITCH0_VALUE 0x0460 207 #define OV0_VID_BUF_PITCH1_VALUE 0x0464 208 #define OV0_AUTO_FLIP_CNTRL 0x0470 209 #define OV0_DEINTERLACE_PATTERN 0x0474 210 #define OV0_SUBMIT_HISTORY 0x0478 211 #define OV0_H_INC 0x0480 212 #define OV0_STEP_BY 0x0484 213 #define OV0_P1_H_ACCUM_INIT 0x0488 214 #define OV0_P23_H_ACCUM_INIT 0x048C 215 #define OV0_P1_X_START_END 0x0494 216 #define OV0_P2_X_START_END 0x0498 217 #define OV0_P3_X_START_END 0x049C 218 #define OV0_FILTER_CNTL 0x04A0 219 #define OV0_FOUR_TAP_COEF_0 0x04B0 220 #define OV0_FOUR_TAP_COEF_1 0x04B4 221 #define OV0_FOUR_TAP_COEF_2 0x04B8 222 #define OV0_FOUR_TAP_COEF_3 0x04BC 223 #define OV0_FOUR_TAP_COEF_4 0x04C0 224 #define OV0_FLAG_CNTRL 0x04DC 225 #define OV0_SLICE_CNTL 0x04E0 226 #define OV0_VID_KEY_CLR_LOW 0x04E4 227 #define OV0_VID_KEY_CLR_HIGH 0x04E8 228 #define OV0_GRPH_KEY_CLR_LOW 0x04EC 229 #define OV0_GRPH_KEY_CLR_HIGH 0x04F0 230 #define OV0_KEY_CNTL 0x04F4 231 #define OV0_TEST 0x04F8 232 #define SUBPIC_CNTL 0x0540 233 #define SUBPIC_DEFCOLCON 0x0544 234 #define SUBPIC_Y_X_START 0x054C 235 #define SUBPIC_Y_X_END 0x0550 236 #define SUBPIC_V_INC 0x0554 237 #define SUBPIC_H_INC 0x0558 238 #define SUBPIC_BUF0_OFFSET 0x055C 239 #define SUBPIC_BUF1_OFFSET 0x0560 240 #define SUBPIC_LC0_OFFSET 0x0564 241 #define SUBPIC_LC1_OFFSET 0x0568 242 #define SUBPIC_PITCH 0x056C 243 #define SUBPIC_BTN_HLI_COLCON 0x0570 244 #define SUBPIC_BTN_HLI_Y_X_START 0x0574 245 #define SUBPIC_BTN_HLI_Y_X_END 0x0578 246 #define SUBPIC_PALETTE_INDEX 0x057C 247 #define SUBPIC_PALETTE_DATA 0x0580 248 #define SUBPIC_H_ACCUM_INIT 0x0584 249 #define SUBPIC_V_ACCUM_INIT 0x0588 250 #define DISP_MISC_CNTL 0x0D00 251 #define DAC_MACRO_CNTL 0x0D04 252 #define DISP_PWR_MAN 0x0D08 253 #define DISP_TEST_DEBUG_CNTL 0x0D10 254 #define DISP_HW_DEBUG 0x0D14 255 #define DAC_CRC_SIG1 0x0D18 256 #define DAC_CRC_SIG2 0x0D1C 257 #define OV0_LIN_TRANS_A 0x0D20 258 #define OV0_LIN_TRANS_B 0x0D24 259 #define OV0_LIN_TRANS_C 0x0D28 260 #define OV0_LIN_TRANS_D 0x0D2C 261 #define OV0_LIN_TRANS_E 0x0D30 262 #define OV0_LIN_TRANS_F 0x0D34 263 #define OV0_GAMMA_0_F 0x0D40 264 #define OV0_GAMMA_10_1F 0x0D44 265 #define OV0_GAMMA_20_3F 0x0D48 266 #define OV0_GAMMA_40_7F 0x0D4C 267 #define OV0_GAMMA_380_3BF 0x0D50 268 #define OV0_GAMMA_3C0_3FF 0x0D54 269 #define DISP_MERGE_CNTL 0x0D60 270 #define DISP_OUTPUT_CNTL 0x0D64 271 #define DISP_LIN_TRANS_GRPH_A 0x0D80 272 #define DISP_LIN_TRANS_GRPH_B 0x0D84 273 #define DISP_LIN_TRANS_GRPH_C 0x0D88 274 #define DISP_LIN_TRANS_GRPH_D 0x0D8C 275 #define DISP_LIN_TRANS_GRPH_E 0x0D90 276 #define DISP_LIN_TRANS_GRPH_F 0x0D94 277 #define DISP_LIN_TRANS_VID_A 0x0D98 278 #define DISP_LIN_TRANS_VID_B 0x0D9C 279 #define DISP_LIN_TRANS_VID_C 0x0DA0 280 #define DISP_LIN_TRANS_VID_D 0x0DA4 281 #define DISP_LIN_TRANS_VID_E 0x0DA8 282 #define DISP_LIN_TRANS_VID_F 0x0DAC 283 #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 284 #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 285 #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 286 #define RMX_HORZ_PHASE 0x0DBC 287 #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 288 #define DAC_BROAD_PULSE 0x0DC4 289 #define DAC_SKEW_CLKS 0x0DC8 290 #define DAC_INCR 0x0DCC 291 #define DAC_NEG_SYNC_LEVEL 0x0DD0 292 #define DAC_POS_SYNC_LEVEL 0x0DD4 293 #define DAC_BLANK_LEVEL 0x0DD8 294 #define CLOCK_CNTL_INDEX 0x0008 295 #define CLOCK_CNTL_DATA 0x000C 296 #define CP_RB_CNTL 0x0704 297 #define CP_RB_BASE 0x0700 298 #define CP_RB_RPTR_ADDR 0x070C 299 #define CP_RB_RPTR 0x0710 300 #define CP_RB_WPTR 0x0714 301 #define CP_RB_WPTR_DELAY 0x0718 302 #define CP_IB_BASE 0x0738 303 #define CP_IB_BUFSZ 0x073C 304 #define SCRATCH_REG0 0x15E0 305 #define GUI_SCRATCH_REG0 0x15E0 306 #define SCRATCH_REG1 0x15E4 307 #define GUI_SCRATCH_REG1 0x15E4 308 #define SCRATCH_REG2 0x15E8 309 #define GUI_SCRATCH_REG2 0x15E8 310 #define SCRATCH_REG3 0x15EC 311 #define GUI_SCRATCH_REG3 0x15EC 312 #define SCRATCH_REG4 0x15F0 313 #define GUI_SCRATCH_REG4 0x15F0 314 #define SCRATCH_REG5 0x15F4 315 #define GUI_SCRATCH_REG5 0x15F4 316 #define SCRATCH_UMSK 0x0770 317 #define SCRATCH_ADDR 0x0774 318 #define DP_BRUSH_FRGD_CLR 0x147C 319 #define DP_BRUSH_BKGD_CLR 0x1478 320 #define DST_LINE_START 0x1600 321 #define DST_LINE_END 0x1604 322 #define SRC_OFFSET 0x15AC 323 #define SRC_PITCH 0x15B0 324 #define SRC_TILE 0x1704 325 #define SRC_PITCH_OFFSET 0x1428 326 #define SRC_X 0x1414 327 #define SRC_Y 0x1418 328 #define SRC_X_Y 0x1590 329 #define SRC_Y_X 0x1434 330 #define DST_Y_X 0x1438 331 #define DST_WIDTH_HEIGHT 0x1598 332 #define DST_HEIGHT_WIDTH 0x143c 333 #define DST_OFFSET 0x1404 334 #define SRC_CLUT_ADDRESS 0x1780 335 #define SRC_CLUT_DATA 0x1784 336 #define SRC_CLUT_DATA_RD 0x1788 337 #define HOST_DATA0 0x17C0 338 #define HOST_DATA1 0x17C4 339 #define HOST_DATA2 0x17C8 340 #define HOST_DATA3 0x17CC 341 #define HOST_DATA4 0x17D0 342 #define HOST_DATA5 0x17D4 343 #define HOST_DATA6 0x17D8 344 #define HOST_DATA7 0x17DC 345 #define HOST_DATA_LAST 0x17E0 346 #define DP_SRC_ENDIAN 0x15D4 347 #define DP_SRC_FRGD_CLR 0x15D8 348 #define DP_SRC_BKGD_CLR 0x15DC 349 #define SC_LEFT 0x1640 350 #define SC_RIGHT 0x1644 351 #define SC_TOP 0x1648 352 #define SC_BOTTOM 0x164C 353 #define SRC_SC_RIGHT 0x1654 354 #define SRC_SC_BOTTOM 0x165C 355 #define DP_CNTL 0x16C0 356 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 357 #define DP_DATATYPE 0x16C4 358 #define DP_MIX 0x16C8 359 #define DP_WRITE_MSK 0x16CC 360 #define DP_XOP 0x17F8 361 #define CLR_CMP_CLR_SRC 0x15C4 362 #define CLR_CMP_CLR_DST 0x15C8 363 #define CLR_CMP_CNTL 0x15C0 364 #define CLR_CMP_MSK 0x15CC 365 #define DSTCACHE_MODE 0x1710 366 #define DSTCACHE_CTLSTAT 0x1714 367 #define SRC_PITCH_OFFSET 0x1428 368 #define DST_PITCH_OFFSET 0x142C 369 #define DEFAULT_PITCH_OFFSET 0x16E0 370 #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 371 #define DP_GUI_MASTER_CNTL 0x146C 372 #define SC_TOP_LEFT 0x16EC 373 #define SC_BOTTOM_RIGHT 0x16F0 374 #define SRC_SC_BOTTOM_RIGHT 0x16F4 375 #define RB2D_DSTCACHE_MODE 0x3428 376 #define RB2D_DSTCACHE_CTLSTAT 0x342C 377 #define LVDS_GEN_CNTL 0x02d0 378 #define LVDS_PLL_CNTL 0x02d4 379 #define TMDS_CNTL 0x0294 380 #define TMDS_CRC 0x02a0 381 #define TMDS_TRANSMITTER_CNTL 0x02a4 382 383 #define RADEON_BASE_CODE 0x0f0b 384 #define RADEON_BIOS_0_SCRATCH 0x0010 385 #define RADEON_BIOS_1_SCRATCH 0x0014 386 #define RADEON_BIOS_2_SCRATCH 0x0018 387 #define RADEON_BIOS_3_SCRATCH 0x001c 388 #define RADEON_BIOS_4_SCRATCH 0x0020 389 #define RADEON_BIOS_5_SCRATCH 0x0024 390 #define RADEON_BIOS_6_SCRATCH 0x0028 391 #define RADEON_BIOS_7_SCRATCH 0x002c 392 393 #define TV_DAC_CNTL 0x088c 394 #define GPIOPAD_MASK 0x0198 395 #define GPIOPAD_A 0x019c 396 #define GPIOPAD_EN 0x01a0 397 #define GPIOPAD_Y 0x01a4 398 #define ZV_LCDPAD_MASK 0x01a8 399 #define ZV_LCDPAD_A 0x01ac 400 #define ZV_LCDPAD_EN 0x01b0 401 #define ZV_LCDPAD_Y 0x01b4 402 403 /* PLL Registers */ 404 #define CLK_PIN_CNTL 0x0001 405 #define PPLL_CNTL 0x0002 406 #define PPLL_REF_DIV 0x0003 407 #define PPLL_DIV_0 0x0004 408 #define PPLL_DIV_1 0x0005 409 #define PPLL_DIV_2 0x0006 410 #define PPLL_DIV_3 0x0007 411 #define VCLK_ECP_CNTL 0x0008 412 #define HTOTAL_CNTL 0x0009 413 #define M_SPLL_REF_FB_DIV 0x000a 414 #define AGP_PLL_CNTL 0x000b 415 #define SPLL_CNTL 0x000c 416 #define SCLK_CNTL 0x000d 417 #define MPLL_CNTL 0x000e 418 #define MDLL_CKO 0x000f 419 #define MDLL_RDCKA 0x0010 420 #define MCLK_CNTL 0x0012 421 #define AGP_PLL_CNTL 0x000b 422 #define PLL_TEST_CNTL 0x0013 423 #define SCLK_MORE_CNTL 0x0035 424 #define CLK_PWRMGT_CNTL 0x0014 425 #define PLL_PWRMGT_CNTL 0x0015 426 #define MCLK_MISC 0x001f 427 #define P2PLL_CNTL 0x002a 428 #define P2PLL_REF_DIV 0x002b 429 #define PIXCLKS_CNTL 0x002d 430 431 /* MCLK_CNTL bit constants */ 432 #define FORCEON_MCLKA (1 << 16) 433 #define FORCEON_MCLKB (1 << 17) 434 #define FORCEON_YCLKA (1 << 18) 435 #define FORCEON_YCLKB (1 << 19) 436 #define FORCEON_MC (1 << 20) 437 #define FORCEON_AIC (1 << 21) 438 439 /* SCLK_CNTL bit constants */ 440 #define DYN_STOP_LAT_MASK 0x00007ff8 441 #define CP_MAX_DYN_STOP_LAT 0x0008 442 #define SCLK_FORCEON_MASK 0xffff8000 443 444 /* SCLK_MORE_CNTL bit constants */ 445 #define SCLK_MORE_FORCEON 0x0700 446 447 /* BUS_CNTL bit constants */ 448 #define BUS_DBL_RESYNC 0x00000001 449 #define BUS_MSTR_RESET 0x00000002 450 #define BUS_FLUSH_BUF 0x00000004 451 #define BUS_STOP_REQ_DIS 0x00000008 452 #define BUS_ROTATION_DIS 0x00000010 453 #define BUS_MASTER_DIS 0x00000040 454 #define BUS_ROM_WRT_EN 0x00000080 455 #define BUS_DIS_ROM 0x00001000 456 #define BUS_PCI_READ_RETRY_EN 0x00002000 457 #define BUS_AGP_AD_STEPPING_EN 0x00004000 458 #define BUS_PCI_WRT_RETRY_EN 0x00008000 459 #define BUS_MSTR_RD_MULT 0x00100000 460 #define BUS_MSTR_RD_LINE 0x00200000 461 #define BUS_SUSPEND 0x00400000 462 #define LAT_16X 0x00800000 463 #define BUS_RD_DISCARD_EN 0x01000000 464 #define BUS_RD_ABORT_EN 0x02000000 465 #define BUS_MSTR_WS 0x04000000 466 #define BUS_PARKING_DIS 0x08000000 467 #define BUS_MSTR_DISCONNECT_EN 0x10000000 468 #define BUS_WRT_BURST 0x20000000 469 #define BUS_READ_BURST 0x40000000 470 #define BUS_RDY_READ_DLY 0x80000000 471 472 473 /* CLOCK_CNTL_INDEX bit constants */ 474 #define PLL_WR_EN 0x00000080 475 476 /* CONFIG_CNTL bit constants */ 477 #define CFG_VGA_RAM_EN 0x00000100 478 479 /* CRTC_EXT_CNTL bit constants */ 480 #define VGA_ATI_LINEAR 0x00000008 481 #define VGA_128KAP_PAGING 0x00000010 482 #define XCRT_CNT_EN (1 << 6) 483 #define CRTC_HSYNC_DIS (1 << 8) 484 #define CRTC_VSYNC_DIS (1 << 9) 485 #define CRTC_DISPLAY_DIS (1 << 10) 486 #define CRTC_CRT_ON (1 << 15) 487 488 489 /* DSTCACHE_CTLSTAT bit constants */ 490 #define RB2D_DC_FLUSH (3 << 0) 491 #define RB2D_DC_FLUSH_ALL 0xf 492 #define RB2D_DC_BUSY (1 << 31) 493 494 495 /* CRTC_GEN_CNTL bit constants */ 496 #define CRTC_DBL_SCAN_EN 0x00000001 497 #define CRTC_CUR_EN 0x00010000 498 #define CRTC_INTERLACE_EN (1 << 1) 499 #define CRTC_BYPASS_LUT_EN (1 << 14) 500 #define CRTC_EXT_DISP_EN (1 << 24) 501 #define CRTC_EN (1 << 25) 502 #define CRTC_DISP_REQ_EN_B (1 << 26) 503 504 /* CRTC_STATUS bit constants */ 505 #define CRTC_VBLANK 0x00000001 506 507 /* CRTC2_GEN_CNTL bit constants */ 508 #define CRT2_ON (1 << 7) 509 #define CRTC2_DISPLAY_DIS (1 << 23) 510 #define CRTC2_EN (1 << 25) 511 #define CRTC2_DISP_REQ_EN_B (1 << 26) 512 513 /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ 514 #define CUR_LOCK 0x80000000 515 516 517 /* FP bit constants */ 518 #define FP_CRTC_H_TOTAL_MASK 0x000003ff 519 #define FP_CRTC_H_DISP_MASK 0x01ff0000 520 #define FP_CRTC_V_TOTAL_MASK 0x00000fff 521 #define FP_CRTC_V_DISP_MASK 0x0fff0000 522 #define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 523 #define FP_H_SYNC_WID_MASK 0x003f0000 524 #define FP_V_SYNC_STRT_MASK 0x00000fff 525 #define FP_V_SYNC_WID_MASK 0x001f0000 526 #define FP_CRTC_H_TOTAL_SHIFT 0x00000000 527 #define FP_CRTC_H_DISP_SHIFT 0x00000010 528 #define FP_CRTC_V_TOTAL_SHIFT 0x00000000 529 #define FP_CRTC_V_DISP_SHIFT 0x00000010 530 #define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 531 #define FP_H_SYNC_WID_SHIFT 0x00000010 532 #define FP_V_SYNC_STRT_SHIFT 0x00000000 533 #define FP_V_SYNC_WID_SHIFT 0x00000010 534 535 /* FP_GEN_CNTL bit constants */ 536 #define FP_FPON (1 << 0) 537 #define FP_TMDS_EN (1 << 2) 538 #define FP_EN_TMDS (1 << 7) 539 #define FP_DETECT_SENSE (1 << 8) 540 #define FP_SEL_CRTC2 (1 << 13) 541 #define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) 542 #define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 543 #define FP_CRTC_DONT_SHADOW_HEND (1 << 17) 544 #define FP_CRTC_USE_SHADOW_VEND (1 << 18) 545 #define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) 546 #define FP_DFP_SYNC_SEL (1 << 21) 547 #define FP_CRTC_LOCK_8DOT (1 << 22) 548 #define FP_CRT_SYNC_SEL (1 << 23) 549 #define FP_USE_SHADOW_EN (1 << 24) 550 #define FP_CRT_SYNC_ALT (1 << 26) 551 552 /* LVDS_GEN_CNTL bit constants */ 553 #define LVDS_ON (1 << 0) 554 #define LVDS_DISPLAY_DIS (1 << 1) 555 #define LVDS_PANEL_TYPE (1 << 2) 556 #define LVDS_PANEL_FORMAT (1 << 3) 557 #define LVDS_EN (1 << 7) 558 #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 559 #define LVDS_BL_MOD_LEVEL_SHIFT 8 560 #define LVDS_BL_MOD_EN (1 << 16) 561 #define LVDS_DIGON (1 << 18) 562 #define LVDS_BLON (1 << 19) 563 #define LVDS_SEL_CRTC2 (1 << 23) 564 #define LVDS_STATE_MASK \ 565 (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | \ 566 LVDS_EN | LVDS_DIGON | LVDS_BLON) 567 568 /* LVDS_PLL_CNTL bit constatns */ 569 #define HSYNC_DELAY_SHIFT 0x1c 570 #define HSYNC_DELAY_MASK (0xf << 0x1c) 571 572 /* TMDS_TRANSMITTER_CNTL bit constants */ 573 #define TMDS_PLL_EN (1 << 0) 574 #define TMDS_PLLRST (1 << 1) 575 #define TMDS_RAN_PAT_RST (1 << 7) 576 #define TMDS_ICHCSEL (1 << 28) 577 578 /* FP_HORZ_STRETCH bit constants */ 579 #define HORZ_STRETCH_RATIO_MASK 0xffff 580 #define HORZ_STRETCH_RATIO_MAX 4096 581 #define HORZ_PANEL_SIZE (0x1ff << 16) 582 #define HORZ_PANEL_SHIFT 16 583 #define HORZ_STRETCH_PIXREP (0 << 25) 584 #define HORZ_STRETCH_BLEND (1 << 26) 585 #define HORZ_STRETCH_ENABLE (1 << 25) 586 #define HORZ_AUTO_RATIO (1 << 27) 587 #define HORZ_FP_LOOP_STRETCH (0x7 << 28) 588 #define HORZ_AUTO_RATIO_INC (1 << 31) 589 590 591 /* FP_VERT_STRETCH bit constants */ 592 #define VERT_STRETCH_RATIO_MASK 0xfff 593 #define VERT_STRETCH_RATIO_MAX 4096 594 #define VERT_PANEL_SIZE (0xfff << 12) 595 #define VERT_PANEL_SHIFT 12 596 #define VERT_STRETCH_LINREP (0 << 26) 597 #define VERT_STRETCH_BLEND (1 << 26) 598 #define VERT_STRETCH_ENABLE (1 << 25) 599 #define VERT_AUTO_RATIO_EN (1 << 27) 600 #define VERT_FP_LOOP_STRETCH (0x7 << 28) 601 #define VERT_STRETCH_RESERVED 0xf1000000 602 603 /* DAC_CNTL bit constants */ 604 #define DAC_8BIT_EN 0x00000100 605 #define DAC_4BPP_PIX_ORDER 0x00000200 606 #define DAC_CRC_EN 0x00080000 607 #define DAC_MASK_ALL (0xff << 24) 608 #define DAC_EXPAND_MODE (1 << 14) 609 #define DAC_VGA_ADR_EN (1 << 13) 610 #define DAC_RANGE_CNTL (3 << 0) 611 #define DAC_BLANKING (1 << 2) 612 #define DAC_CMP_EN (1 << 3) 613 614 /* DAC_CNTL2 bit constants */ 615 #define DAC2_CMP_EN (1 << 7) 616 #define DAC2_PALETTE_ACCESS_CNTL (1 << 5) 617 618 619 /* GEN_RESET_CNTL bit constants */ 620 #define SOFT_RESET_GUI 0x00000001 621 #define SOFT_RESET_VCLK 0x00000100 622 #define SOFT_RESET_PCLK 0x00000200 623 #define SOFT_RESET_ECP 0x00000400 624 #define SOFT_RESET_DISPENG_XCLK 0x00000800 625 626 /* MEM_CNTL bit constants */ 627 #define MEM_CTLR_STATUS_IDLE 0x00000000 628 #define MEM_CTLR_STATUS_BUSY 0x00100000 629 #define MEM_SEQNCR_STATUS_IDLE 0x00000000 630 #define MEM_SEQNCR_STATUS_BUSY 0x00200000 631 #define MEM_ARBITER_STATUS_IDLE 0x00000000 632 #define MEM_ARBITER_STATUS_BUSY 0x00400000 633 #define MEM_REQ_UNLOCK 0x00000000 634 #define MEM_REQ_LOCK 0x00800000 635 636 637 /* RBBM_SOFT_RESET bit constants */ 638 #define SOFT_RESET_CP (1 << 0) 639 #define SOFT_RESET_HI (1 << 1) 640 #define SOFT_RESET_SE (1 << 2) 641 #define SOFT_RESET_RE (1 << 3) 642 #define SOFT_RESET_PP (1 << 4) 643 #define SOFT_RESET_E2 (1 << 5) 644 #define SOFT_RESET_RB (1 << 6) 645 #define SOFT_RESET_HDP (1 << 7) 646 647 /* HOST_PATH_CNTL bit constants */ 648 #define HDP_SOFT_RESET (1 << 26) 649 650 /* SURFACE_CNTL bit consants */ 651 #define SURF_TRANSLATION_DIS (1 << 8) 652 #define NONSURF_AP0_SWP_16BPP (1 << 20) 653 #define NONSURF_AP0_SWP_32BPP (1 << 21) 654 #define NONSURF_AP1_SWP_16BPP (1 << 22) 655 #define NONSURF_AP1_SWP_32BPP (1 << 23) 656 657 /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ 658 #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 659 #define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 660 661 /* MM_INDEX bit constants */ 662 #define MM_APER 0x80000000 663 664 /* CLR_CMP_CNTL bit constants */ 665 #define COMPARE_SRC_FALSE 0x00000000 666 #define COMPARE_SRC_TRUE 0x00000001 667 #define COMPARE_SRC_NOT_EQUAL 0x00000004 668 #define COMPARE_SRC_EQUAL 0x00000005 669 #define COMPARE_SRC_EQUAL_FLIP 0x00000007 670 #define COMPARE_DST_FALSE 0x00000000 671 #define COMPARE_DST_TRUE 0x00000100 672 #define COMPARE_DST_NOT_EQUAL 0x00000400 673 #define COMPARE_DST_EQUAL 0x00000500 674 #define COMPARE_DESTINATION 0x00000000 675 #define COMPARE_SOURCE 0x01000000 676 #define COMPARE_SRC_AND_DST 0x02000000 677 678 679 /* DP_CNTL bit constants */ 680 #define DST_X_RIGHT_TO_LEFT 0x00000000 681 #define DST_X_LEFT_TO_RIGHT 0x00000001 682 #define DST_Y_BOTTOM_TO_TOP 0x00000000 683 #define DST_Y_TOP_TO_BOTTOM 0x00000002 684 #define DST_X_MAJOR 0x00000000 685 #define DST_Y_MAJOR 0x00000004 686 #define DST_X_TILE 0x00000008 687 #define DST_Y_TILE 0x00000010 688 #define DST_LAST_PEL 0x00000020 689 #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 690 #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 691 #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 692 #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 693 #define DST_BRES_SIGN 0x00000100 694 #define DST_HOST_BIG_ENDIAN_EN 0x00000200 695 #define DST_POLYLINE_NONLAST 0x00008000 696 #define DST_RASTER_STALL 0x00010000 697 #define DST_POLY_EDGE 0x00040000 698 699 700 /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ 701 #define DST_X_MAJOR_S 0x00000000 702 #define DST_Y_MAJOR_S 0x00000001 703 #define DST_Y_BOTTOM_TO_TOP_S 0x00000000 704 #define DST_Y_TOP_TO_BOTTOM_S 0x00008000 705 #define DST_X_RIGHT_TO_LEFT_S 0x00000000 706 #define DST_X_LEFT_TO_RIGHT_S 0x80000000 707 708 709 /* DP_DATATYPE bit constants */ 710 #define DST_8BPP 0x00000002 711 #define DST_15BPP 0x00000003 712 #define DST_16BPP 0x00000004 713 #define DST_24BPP 0x00000005 714 #define DST_32BPP 0x00000006 715 #define DST_8BPP_RGB332 0x00000007 716 #define DST_8BPP_Y8 0x00000008 717 #define DST_8BPP_RGB8 0x00000009 718 #define DST_16BPP_VYUY422 0x0000000b 719 #define DST_16BPP_YVYU422 0x0000000c 720 #define DST_32BPP_AYUV444 0x0000000e 721 #define DST_16BPP_ARGB4444 0x0000000f 722 #define BRUSH_SOLIDCOLOR 0x00000d00 723 #define SRC_MONO 0x00000000 724 #define SRC_MONO_LBKGD 0x00010000 725 #define SRC_DSTCOLOR 0x00030000 726 #define BYTE_ORDER_MSB_TO_LSB 0x00000000 727 #define BYTE_ORDER_LSB_TO_MSB 0x40000000 728 #define DP_CONVERSION_TEMP 0x80000000 729 #define HOST_BIG_ENDIAN_EN (1 << 29) 730 731 732 /* DP_GUI_MASTER_CNTL bit constants */ 733 #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 734 #define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 735 #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 736 #define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 737 #define GMC_SRC_CLIP_DEFAULT 0x00000000 738 #define GMC_SRC_CLIP_LEAVE 0x00000004 739 #define GMC_DST_CLIP_DEFAULT 0x00000000 740 #define GMC_DST_CLIP_LEAVE 0x00000008 741 #define GMC_BRUSH_8x8MONO 0x00000000 742 #define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 743 #define GMC_BRUSH_8x1MONO 0x00000020 744 #define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 745 #define GMC_BRUSH_1x8MONO 0x00000040 746 #define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 747 #define GMC_BRUSH_32x1MONO 0x00000060 748 #define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 749 #define GMC_BRUSH_32x32MONO 0x00000080 750 #define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 751 #define GMC_BRUSH_8x8COLOR 0x000000a0 752 #define GMC_BRUSH_8x1COLOR 0x000000b0 753 #define GMC_BRUSH_1x8COLOR 0x000000c0 754 #define GMC_BRUSH_SOLID_COLOR 0x000000d0 755 #define GMC_DST_8BPP 0x00000200 756 #define GMC_DST_15BPP 0x00000300 757 #define GMC_DST_16BPP 0x00000400 758 #define GMC_DST_24BPP 0x00000500 759 #define GMC_DST_32BPP 0x00000600 760 #define GMC_DST_8BPP_RGB332 0x00000700 761 #define GMC_DST_8BPP_Y8 0x00000800 762 #define GMC_DST_8BPP_RGB8 0x00000900 763 #define GMC_DST_16BPP_VYUY422 0x00000b00 764 #define GMC_DST_16BPP_YVYU422 0x00000c00 765 #define GMC_DST_32BPP_AYUV444 0x00000e00 766 #define GMC_DST_16BPP_ARGB4444 0x00000f00 767 #define GMC_SRC_MONO 0x00000000 768 #define GMC_SRC_MONO_LBKGD 0x00001000 769 #define GMC_SRC_DSTCOLOR 0x00003000 770 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 771 #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 772 #define GMC_DP_CONVERSION_TEMP_9300 0x00008000 773 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 774 #define GMC_DP_SRC_RECT 0x02000000 775 #define GMC_DP_SRC_HOST 0x03000000 776 #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 777 #define GMC_3D_FCN_EN_CLR 0x00000000 778 #define GMC_3D_FCN_EN_SET 0x08000000 779 #define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 780 #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 781 #define GMC_AUX_CLIP_LEAVE 0x00000000 782 #define GMC_AUX_CLIP_CLEAR 0x20000000 783 #define GMC_WRITE_MASK_LEAVE 0x00000000 784 #define GMC_WRITE_MASK_SET 0x40000000 785 #define GMC_CLR_CMP_CNTL_DIS (1 << 28) 786 #define GMC_SRC_DATATYPE_COLOR (3 << 12) 787 #define ROP3_S 0x00cc0000 788 #define ROP3_SRCCOPY 0x00cc0000 789 #define ROP3_P 0x00f00000 790 #define ROP3_PATCOPY 0x00f00000 791 #define DP_SRC_SOURCE_MASK (7 << 24) 792 #define GMC_BRUSH_NONE (15 << 4) 793 #define DP_SRC_SOURCE_MEMORY (2 << 24) 794 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 795 796 /* DP_MIX bit constants */ 797 #define DP_SRC_RECT 0x00000200 798 #define DP_SRC_HOST 0x00000300 799 #define DP_SRC_HOST_BYTEALIGN 0x00000400 800 801 /* MPLL_CNTL bit constants */ 802 #define MPLL_RESET 0x00000001 803 804 /* MDLL_RDCKA bit constants */ 805 #define MRDCKA0_SLEEP 0x00000001 806 #define MRDCKA0_RESET 0x00000002 807 #define MRDCKA1_SLEEP 0x00010000 808 #define MRDCKA1_RESET 0x00020000 809 810 /* VCLK_ECP_CNTL constants */ 811 #define PIXCLK_ALWAYS_ONb 0x00000040 812 #define PIXCLK_DAC_ALWAYS_ONb 0x00000080 813 814 /* BUS_CNTL1 constants */ 815 #define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 816 #define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 817 #define BUS_CNTL1_AGPCLK_VALID 0x80000000 818 819 /* PLL_PWRMGT_CNTL constants */ 820 #define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 821 #define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 822 #define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 823 #define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 824 #define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 825 #define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 826 #define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 827 828 /* TV_DAC_CNTL constants */ 829 #define TV_DAC_CNTL_BGSLEEP 0x00000040 830 #define TV_DAC_CNTL_DETECT 0x00000010 831 #define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 832 #define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 833 #define TV_DAC_CNTL_BGADJ__SHIFT 16 834 #define TV_DAC_CNTL_DACADJ__SHIFT 20 835 #define TV_DAC_CNTL_RDACPD 0x01000000 836 #define TV_DAC_CNTL_GDACPD 0x02000000 837 #define TV_DAC_CNTL_BDACPD 0x04000000 838 839 /* DISP_MISC_CNTL constants */ 840 #define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) 841 #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) 842 #define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) 843 #define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) 844 #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) 845 #define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) 846 #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) 847 #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) 848 #define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) 849 #define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) 850 #define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) 851 #define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) 852 853 /* DISP_PWR_MAN constants */ 854 #define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) 855 #define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) 856 #define DISP_PWR_MAN_DISP_D3_RST (1 << 16) 857 #define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) 858 #define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) 859 #define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) 860 #define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) 861 #define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) 862 #define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) 863 #define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) 864 #define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) 865 #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) 866 #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) 867 868 /* masks */ 869 870 #define CONFIG_MEMSIZE_MASK 0x1f000000 871 #define MEM_CFG_TYPE 0x40000000 872 #define DST_OFFSET_MASK 0x003fffff 873 #define DST_PITCH_MASK 0x3fc00000 874 #define DEFAULT_TILE_MASK 0xc0000000 875 #define PPLL_DIV_SEL_MASK 0x00000300 876 #define PPLL_RESET 0x00000001 877 #define PPLL_ATOMIC_UPDATE_EN 0x00010000 878 #define PPLL_REF_DIV_MASK 0x000003ff 879 #define PPLL_FB3_DIV_MASK 0x000007ff 880 #define PPLL_POST3_DIV_MASK 0x00070000 881 #define PPLL_ATOMIC_UPDATE_R 0x00008000 882 #define PPLL_ATOMIC_UPDATE_W 0x00008000 883 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 884 885 #define GUI_ACTIVE 0x80000000 886 887 888 #define MC_IND_INDEX 0x01F8 889 #define MC_IND_DATA 0x01FC 890 #define MEM_REFRESH_CNTL 0x0178 891 892 // CLK_PIN_CNTL 893 #define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L 894 #define CLK_PIN_CNTL__OSC_EN 0x00000001L 895 #define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L 896 #define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L 897 #define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L 898 #define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L 899 #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L 900 #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L 901 #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L 902 #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L 903 #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L 904 #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L 905 #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L 906 #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L 907 #define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L 908 #define CLK_PIN_CNTL__CG_SPARE 0x00004000L 909 #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L 910 #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L 911 #define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L 912 #define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L 913 #define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L 914 #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L 915 #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L 916 #define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L 917 918 // CLK_PWRMGT_CNTL_M6 919 #define CLK_PWRMGT_CNTL_M6__MPLL_PWRMGT_OFF__SHIFT 0x00000000 920 #define CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF__SHIFT 0x00000001 921 #define CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_OFF__SHIFT 0x00000002 922 #define CLK_PWRMGT_CNTL_M6__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 923 #define CLK_PWRMGT_CNTL_M6__MCLK_TURNOFF__SHIFT 0x00000004 924 #define CLK_PWRMGT_CNTL_M6__SCLK_TURNOFF__SHIFT 0x00000005 925 #define CLK_PWRMGT_CNTL_M6__PCLK_TURNOFF__SHIFT 0x00000006 926 #define CLK_PWRMGT_CNTL_M6__P2CLK_TURNOFF__SHIFT 0x00000007 927 #define CLK_PWRMGT_CNTL_M6__MC_CH_MODE__SHIFT 0x00000008 928 #define CLK_PWRMGT_CNTL_M6__TEST_MODE__SHIFT 0x00000009 929 #define CLK_PWRMGT_CNTL_M6__GLOBAL_PMAN_EN__SHIFT 0x0000000a 930 #define CLK_PWRMGT_CNTL_M6__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c 931 #define CLK_PWRMGT_CNTL_M6__ACTIVE_HILO_LAT__SHIFT 0x0000000d 932 #define CLK_PWRMGT_CNTL_M6__DISP_DYN_STOP_LAT__SHIFT 0x0000000f 933 #define CLK_PWRMGT_CNTL_M6__MC_BUSY__SHIFT 0x00000010 934 #define CLK_PWRMGT_CNTL_M6__MC_INT_CNTL__SHIFT 0x00000011 935 #define CLK_PWRMGT_CNTL_M6__MC_SWITCH__SHIFT 0x00000012 936 #define CLK_PWRMGT_CNTL_M6__DLL_READY__SHIFT 0x00000013 937 #define CLK_PWRMGT_CNTL_M6__DISP_PM__SHIFT 0x00000014 938 #define CLK_PWRMGT_CNTL_M6__DYN_STOP_MODE__SHIFT 0x00000015 939 #define CLK_PWRMGT_CNTL_M6__CG_NO1_DEBUG__SHIFT 0x00000018 940 #define CLK_PWRMGT_CNTL_M6__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e 941 #define CLK_PWRMGT_CNTL_M6__TVCLK_TURNOFF__SHIFT 0x0000001f 942 943 // P2PLL_CNTL 944 #define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L 945 #define P2PLL_CNTL__P2PLL_RESET 0x00000001L 946 #define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L 947 #define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L 948 #define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L 949 #define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L 950 #define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L 951 #define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L 952 #define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L 953 #define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L 954 #define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L 955 #define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L 956 #define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L 957 #define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L 958 #define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L 959 #define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L 960 #define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L 961 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L 962 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L 963 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L 964 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L 965 #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L 966 #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L 967 968 // PIXCLKS_CNTL 969 #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 970 #define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 971 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 972 #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 973 #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 974 #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 975 #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b 976 #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c 977 #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d 978 #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e 979 #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f 980 981 982 // PIXCLKS_CNTL 983 #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L 984 #define PIXCLKS_CNTL__PIX2CLK_INVERT_MASK 0x00000010L 985 #define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L 986 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT_MASK 0x00000020L 987 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L 988 #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb_MASK 0x00000040L 989 #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L 990 #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb_MASK 0x00000080L 991 #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L 992 #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL_MASK 0x00000100L 993 #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L 994 #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb_MASK 0x00000800L 995 #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L 996 #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb_MASK 0x00001000L 997 #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L 998 #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb_MASK 0x00002000L 999 #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L 1000 #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb_MASK 0x00004000L 1001 #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L 1002 #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb_MASK 0x00008000L 1003 #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L 1004 1005 1006 // P2PLL_DIV_0 1007 #define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL 1008 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L 1009 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L 1010 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L 1011 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L 1012 #define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L 1013 1014 // SCLK_CNTL_M6 1015 #define SCLK_CNTL_M6__SCLK_SRC_SEL_MASK 0x00000007L 1016 #define SCLK_CNTL_M6__CP_MAX_DYN_STOP_LAT_MASK 0x00000008L 1017 #define SCLK_CNTL_M6__CP_MAX_DYN_STOP_LAT 0x00000008L 1018 #define SCLK_CNTL_M6__HDP_MAX_DYN_STOP_LAT_MASK 0x00000010L 1019 #define SCLK_CNTL_M6__HDP_MAX_DYN_STOP_LAT 0x00000010L 1020 #define SCLK_CNTL_M6__TV_MAX_DYN_STOP_LAT_MASK 0x00000020L 1021 #define SCLK_CNTL_M6__TV_MAX_DYN_STOP_LAT 0x00000020L 1022 #define SCLK_CNTL_M6__E2_MAX_DYN_STOP_LAT_MASK 0x00000040L 1023 #define SCLK_CNTL_M6__E2_MAX_DYN_STOP_LAT 0x00000040L 1024 #define SCLK_CNTL_M6__SE_MAX_DYN_STOP_LAT_MASK 0x00000080L 1025 #define SCLK_CNTL_M6__SE_MAX_DYN_STOP_LAT 0x00000080L 1026 #define SCLK_CNTL_M6__IDCT_MAX_DYN_STOP_LAT_MASK 0x00000100L 1027 #define SCLK_CNTL_M6__IDCT_MAX_DYN_STOP_LAT 0x00000100L 1028 #define SCLK_CNTL_M6__VIP_MAX_DYN_STOP_LAT_MASK 0x00000200L 1029 #define SCLK_CNTL_M6__VIP_MAX_DYN_STOP_LAT 0x00000200L 1030 #define SCLK_CNTL_M6__RE_MAX_DYN_STOP_LAT_MASK 0x00000400L 1031 #define SCLK_CNTL_M6__RE_MAX_DYN_STOP_LAT 0x00000400L 1032 #define SCLK_CNTL_M6__PB_MAX_DYN_STOP_LAT_MASK 0x00000800L 1033 #define SCLK_CNTL_M6__PB_MAX_DYN_STOP_LAT 0x00000800L 1034 #define SCLK_CNTL_M6__TAM_MAX_DYN_STOP_LAT_MASK 0x00001000L 1035 #define SCLK_CNTL_M6__TAM_MAX_DYN_STOP_LAT 0x00001000L 1036 #define SCLK_CNTL_M6__TDM_MAX_DYN_STOP_LAT_MASK 0x00002000L 1037 #define SCLK_CNTL_M6__TDM_MAX_DYN_STOP_LAT 0x00002000L 1038 #define SCLK_CNTL_M6__RB_MAX_DYN_STOP_LAT_MASK 0x00004000L 1039 #define SCLK_CNTL_M6__RB_MAX_DYN_STOP_LAT 0x00004000L 1040 #define SCLK_CNTL_M6__FORCE_DISP2_MASK 0x00008000L 1041 #define SCLK_CNTL_M6__FORCE_DISP2 0x00008000L 1042 #define SCLK_CNTL_M6__FORCE_CP_MASK 0x00010000L 1043 #define SCLK_CNTL_M6__FORCE_CP 0x00010000L 1044 #define SCLK_CNTL_M6__FORCE_HDP_MASK 0x00020000L 1045 #define SCLK_CNTL_M6__FORCE_HDP 0x00020000L 1046 #define SCLK_CNTL_M6__FORCE_DISP1_MASK 0x00040000L 1047 #define SCLK_CNTL_M6__FORCE_DISP1 0x00040000L 1048 #define SCLK_CNTL_M6__FORCE_TOP_MASK 0x00080000L 1049 #define SCLK_CNTL_M6__FORCE_TOP 0x00080000L 1050 #define SCLK_CNTL_M6__FORCE_E2_MASK 0x00100000L 1051 #define SCLK_CNTL_M6__FORCE_E2 0x00100000L 1052 #define SCLK_CNTL_M6__FORCE_SE_MASK 0x00200000L 1053 #define SCLK_CNTL_M6__FORCE_SE 0x00200000L 1054 #define SCLK_CNTL_M6__FORCE_IDCT_MASK 0x00400000L 1055 #define SCLK_CNTL_M6__FORCE_IDCT 0x00400000L 1056 #define SCLK_CNTL_M6__FORCE_VIP_MASK 0x00800000L 1057 #define SCLK_CNTL_M6__FORCE_VIP 0x00800000L 1058 #define SCLK_CNTL_M6__FORCE_RE_MASK 0x01000000L 1059 #define SCLK_CNTL_M6__FORCE_RE 0x01000000L 1060 #define SCLK_CNTL_M6__FORCE_PB_MASK 0x02000000L 1061 #define SCLK_CNTL_M6__FORCE_PB 0x02000000L 1062 #define SCLK_CNTL_M6__FORCE_TAM_MASK 0x04000000L 1063 #define SCLK_CNTL_M6__FORCE_TAM 0x04000000L 1064 #define SCLK_CNTL_M6__FORCE_TDM_MASK 0x08000000L 1065 #define SCLK_CNTL_M6__FORCE_TDM 0x08000000L 1066 #define SCLK_CNTL_M6__FORCE_RB_MASK 0x10000000L 1067 #define SCLK_CNTL_M6__FORCE_RB 0x10000000L 1068 #define SCLK_CNTL_M6__FORCE_TV_SCLK_MASK 0x20000000L 1069 #define SCLK_CNTL_M6__FORCE_TV_SCLK 0x20000000L 1070 #define SCLK_CNTL_M6__FORCE_SUBPIC_MASK 0x40000000L 1071 #define SCLK_CNTL_M6__FORCE_SUBPIC 0x40000000L 1072 #define SCLK_CNTL_M6__FORCE_OV0_MASK 0x80000000L 1073 #define SCLK_CNTL_M6__FORCE_OV0 0x80000000L 1074 1075 // SCLK_MORE_CNTL 1076 #define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT_MASK 0x00000001L 1077 #define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L 1078 #define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT_MASK 0x00000002L 1079 #define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L 1080 #define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT_MASK 0x00000004L 1081 #define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L 1082 #define SCLK_MORE_CNTL__FORCE_DISPREGS_MASK 0x00000100L 1083 #define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L 1084 #define SCLK_MORE_CNTL__FORCE_MC_GUI_MASK 0x00000200L 1085 #define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L 1086 #define SCLK_MORE_CNTL__FORCE_MC_HOST_MASK 0x00000400L 1087 #define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L 1088 #define SCLK_MORE_CNTL__STOP_SCLK_EN_MASK 0x00001000L 1089 #define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L 1090 #define SCLK_MORE_CNTL__STOP_SCLK_A_MASK 0x00002000L 1091 #define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L 1092 #define SCLK_MORE_CNTL__STOP_SCLK_B_MASK 0x00004000L 1093 #define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L 1094 #define SCLK_MORE_CNTL__STOP_SCLK_C_MASK 0x00008000L 1095 #define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L 1096 #define SCLK_MORE_CNTL__HALF_SPEED_SCLK_MASK 0x00010000L 1097 #define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L 1098 #define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP_MASK 0x00020000L 1099 #define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L 1100 #define SCLK_MORE_CNTL__TVFB_SOFT_RESET_MASK 0x00040000L 1101 #define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L 1102 #define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC_MASK 0x00080000L 1103 #define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L 1104 #define SCLK_MORE_CNTL__VOLTAGE_DELAY_SEL_MASK 0x00300000L 1105 #define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK_MASK 0x00400000L 1106 #define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L 1107 #define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK_MASK 0x00800000L 1108 #define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L 1109 #define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L 1110 1111 // MCLK_CNTL_M6 1112 #define MCLK_CNTL_M6__MCLKA_SRC_SEL_MASK 0x00000007L 1113 #define MCLK_CNTL_M6__YCLKA_SRC_SEL_MASK 0x00000070L 1114 #define MCLK_CNTL_M6__MCLKB_SRC_SEL_MASK 0x00000700L 1115 #define MCLK_CNTL_M6__YCLKB_SRC_SEL_MASK 0x00007000L 1116 #define MCLK_CNTL_M6__FORCE_MCLKA_MASK 0x00010000L 1117 #define MCLK_CNTL_M6__FORCE_MCLKA 0x00010000L 1118 #define MCLK_CNTL_M6__FORCE_MCLKB_MASK 0x00020000L 1119 #define MCLK_CNTL_M6__FORCE_MCLKB 0x00020000L 1120 #define MCLK_CNTL_M6__FORCE_YCLKA_MASK 0x00040000L 1121 #define MCLK_CNTL_M6__FORCE_YCLKA 0x00040000L 1122 #define MCLK_CNTL_M6__FORCE_YCLKB_MASK 0x00080000L 1123 #define MCLK_CNTL_M6__FORCE_YCLKB 0x00080000L 1124 #define MCLK_CNTL_M6__FORCE_MC_MASK 0x00100000L 1125 #define MCLK_CNTL_M6__FORCE_MC 0x00100000L 1126 #define MCLK_CNTL_M6__FORCE_AIC_MASK 0x00200000L 1127 #define MCLK_CNTL_M6__FORCE_AIC 0x00200000L 1128 #define MCLK_CNTL_M6__MRDCKA0_SOUTSEL_MASK 0x03000000L 1129 #define MCLK_CNTL_M6__MRDCKA1_SOUTSEL_MASK 0x0c000000L 1130 #define MCLK_CNTL_M6__MRDCKB0_SOUTSEL_MASK 0x30000000L 1131 #define MCLK_CNTL_M6__MRDCKB1_SOUTSEL_MASK 0xc0000000L 1132 1133 // MCLK_MISC 1134 #define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L 1135 #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L 1136 #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L 1137 #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L 1138 #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L 1139 #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L 1140 #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L 1141 #define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L 1142 #define MCLK_MISC__DLL_READY_LAT 0x00000100L 1143 #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L 1144 #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L 1145 #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L 1146 #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L 1147 #define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L 1148 #define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L 1149 #define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L 1150 #define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L 1151 #define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L 1152 #define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L 1153 #define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L 1154 #define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L 1155 #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L 1156 #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L 1157 #define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L 1158 #define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L 1159 #define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L 1160 #define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L 1161 #define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L 1162 1163 // VCLK_ECP_CNTL 1164 #define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L 1165 #define VCLK_ECP_CNTL__VCLK_INVERT_MASK 0x00000010L 1166 #define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L 1167 #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT_MASK 0x00000020L 1168 #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L 1169 #define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb_MASK 0x00000040L 1170 #define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L 1171 #define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb_MASK 0x00000080L 1172 #define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L 1173 #define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L 1174 #define VCLK_ECP_CNTL__ECP_FORCE_ON_MASK 0x00040000L 1175 #define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L 1176 #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON_MASK 0x00080000L 1177 #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L 1178 1179 // PLL_PWRMGT_CNTL 1180 #define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L 1181 #define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L 1182 #define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L 1183 #define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L 1184 #define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L 1185 #define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L 1186 #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L 1187 #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L 1188 #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L 1189 #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L 1190 #define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L 1191 #define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L 1192 #define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L 1193 #define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L 1194 #define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L 1195 #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L 1196 #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L 1197 #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L 1198 #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L 1199 #define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L 1200 #define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L 1201 #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L 1202 #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L 1203 #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L 1204 #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L 1205 #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L 1206 #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L 1207 #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L 1208 #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L 1209 #define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD_MASK 0x00200000L 1210 #define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L 1211 #define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L 1212 1213 // CLK_PWRMGT_CNTL_M6 1214 #define CLK_PWRMGT_CNTL_M6__MPLL_PWRMGT_OFF_MASK 0x00000001L 1215 #define CLK_PWRMGT_CNTL_M6__MPLL_PWRMGT_OFF 0x00000001L 1216 #define CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF_MASK 0x00000002L 1217 #define CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF 0x00000002L 1218 #define CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_OFF_MASK 0x00000004L 1219 #define CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_OFF 0x00000004L 1220 #define CLK_PWRMGT_CNTL_M6__P2PLL_PWRMGT_OFF_MASK 0x00000008L 1221 #define CLK_PWRMGT_CNTL_M6__P2PLL_PWRMGT_OFF 0x00000008L 1222 #define CLK_PWRMGT_CNTL_M6__MCLK_TURNOFF_MASK 0x00000010L 1223 #define CLK_PWRMGT_CNTL_M6__MCLK_TURNOFF 0x00000010L 1224 #define CLK_PWRMGT_CNTL_M6__SCLK_TURNOFF_MASK 0x00000020L 1225 #define CLK_PWRMGT_CNTL_M6__SCLK_TURNOFF 0x00000020L 1226 #define CLK_PWRMGT_CNTL_M6__PCLK_TURNOFF_MASK 0x00000040L 1227 #define CLK_PWRMGT_CNTL_M6__PCLK_TURNOFF 0x00000040L 1228 #define CLK_PWRMGT_CNTL_M6__P2CLK_TURNOFF_MASK 0x00000080L 1229 #define CLK_PWRMGT_CNTL_M6__P2CLK_TURNOFF 0x00000080L 1230 #define CLK_PWRMGT_CNTL_M6__MC_CH_MODE_MASK 0x00000100L 1231 #define CLK_PWRMGT_CNTL_M6__MC_CH_MODE 0x00000100L 1232 #define CLK_PWRMGT_CNTL_M6__TEST_MODE_MASK 0x00000200L 1233 #define CLK_PWRMGT_CNTL_M6__TEST_MODE 0x00000200L 1234 #define CLK_PWRMGT_CNTL_M6__GLOBAL_PMAN_EN_MASK 0x00000400L 1235 #define CLK_PWRMGT_CNTL_M6__GLOBAL_PMAN_EN 0x00000400L 1236 #define CLK_PWRMGT_CNTL_M6__ENGINE_DYNCLK_MODE_MASK 0x00001000L 1237 #define CLK_PWRMGT_CNTL_M6__ENGINE_DYNCLK_MODE 0x00001000L 1238 #define CLK_PWRMGT_CNTL_M6__ACTIVE_HILO_LAT_MASK 0x00006000L 1239 #define CLK_PWRMGT_CNTL_M6__DISP_DYN_STOP_LAT_MASK 0x00008000L 1240 #define CLK_PWRMGT_CNTL_M6__DISP_DYN_STOP_LAT 0x00008000L 1241 #define CLK_PWRMGT_CNTL_M6__MC_BUSY_MASK 0x00010000L 1242 #define CLK_PWRMGT_CNTL_M6__MC_BUSY 0x00010000L 1243 #define CLK_PWRMGT_CNTL_M6__MC_INT_CNTL_MASK 0x00020000L 1244 #define CLK_PWRMGT_CNTL_M6__MC_INT_CNTL 0x00020000L 1245 #define CLK_PWRMGT_CNTL_M6__MC_SWITCH_MASK 0x00040000L 1246 #define CLK_PWRMGT_CNTL_M6__MC_SWITCH 0x00040000L 1247 #define CLK_PWRMGT_CNTL_M6__DLL_READY_MASK 0x00080000L 1248 #define CLK_PWRMGT_CNTL_M6__DLL_READY 0x00080000L 1249 #define CLK_PWRMGT_CNTL_M6__DISP_PM_MASK 0x00100000L 1250 #define CLK_PWRMGT_CNTL_M6__DISP_PM 0x00100000L 1251 #define CLK_PWRMGT_CNTL_M6__DYN_STOP_MODE_MASK 0x00e00000L 1252 #define CLK_PWRMGT_CNTL_M6__CG_NO1_DEBUG_MASK 0x3f000000L 1253 #define CLK_PWRMGT_CNTL_M6__TVPLL_PWRMGT_OFF_MASK 0x40000000L 1254 #define CLK_PWRMGT_CNTL_M6__TVPLL_PWRMGT_OFF 0x40000000L 1255 #define CLK_PWRMGT_CNTL_M6__TVCLK_TURNOFF_MASK 0x80000000L 1256 #define CLK_PWRMGT_CNTL_M6__TVCLK_TURNOFF 0x80000000L 1257 1258 // BUS_CNTL1 1259 #define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L 1260 #define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L 1261 #define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L 1262 #define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L 1263 #define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L 1264 #define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L 1265 #define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L 1266 #define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L 1267 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L 1268 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L 1269 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L 1270 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L 1271 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L 1272 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L 1273 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L 1274 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L 1275 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L 1276 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L 1277 #define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L 1278 #define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L 1279 #define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L 1280 #define BUS_CNTL1__AGPCLK_VALID 0x80000000L 1281 1282 // BUS_CNTL1 1283 #define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 1284 #define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 1285 #define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 1286 #define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 1287 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 1288 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 1289 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 1290 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a 1291 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b 1292 #define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a 1293 #define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c 1294 #define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f 1295 1296 // CRTC_OFFSET_CNTL 1297 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL 1298 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L 1299 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L 1300 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L 1301 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L 1302 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L 1303 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L 1304 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L 1305 #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L 1306 #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L 1307 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L 1308 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L 1309 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L 1310 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L 1311 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L 1312 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L 1313 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L 1314 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L 1315 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L 1316 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L 1317 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L 1318 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L 1319 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L 1320 1321 // CRTC_GEN_CNTL 1322 #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L 1323 #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L 1324 #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L 1325 #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L 1326 #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L 1327 #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L 1328 #define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L 1329 #define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L 1330 #define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L 1331 #define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L 1332 #define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L 1333 #define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L 1334 #define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L 1335 #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L 1336 #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L 1337 #define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L 1338 #define CRTC_GEN_CNTL__CRTC_EN 0x02000000L 1339 #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L 1340 #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L 1341 1342 // CRTC2_GEN_CNTL 1343 #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L 1344 #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L 1345 #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L 1346 #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L 1347 #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L 1348 #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L 1349 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L 1350 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L 1351 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L 1352 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L 1353 #define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L 1354 #define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L 1355 #define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L 1356 #define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L 1357 #define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L 1358 #define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L 1359 #define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L 1360 #define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L 1361 #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L 1362 #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L 1363 #define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L 1364 #define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L 1365 #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L 1366 #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L 1367 #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L 1368 #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L 1369 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L 1370 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L 1371 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L 1372 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L 1373 1374 // AGP_CNTL 1375 #define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL 1376 #define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L 1377 #define AGP_CNTL__HOLD_RD_FIFO 0x00000100L 1378 #define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L 1379 #define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L 1380 #define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L 1381 #define AGP_CNTL__EN_2X_STBB 0x00000400L 1382 #define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L 1383 #define AGP_CNTL__FORCE_FULL_SBA 0x00000800L 1384 #define AGP_CNTL__SBA_DIS_MASK 0x00001000L 1385 #define AGP_CNTL__SBA_DIS 0x00001000L 1386 #define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L 1387 #define AGP_CNTL__AGP_REV_ID 0x00002000L 1388 #define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L 1389 #define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L 1390 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L 1391 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L 1392 #define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L 1393 #define AGP_CNTL__FORCE_INT_VREF 0x00010000L 1394 #define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L 1395 #define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L 1396 #define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L 1397 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L 1398 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L 1399 #define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L 1400 #define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L 1401 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L 1402 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L 1403 #define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L 1404 #define AGP_CNTL__EN_RBFCALM 0x00800000L 1405 #define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L 1406 #define AGP_CNTL__FORCE_EXT_VREF 0x01000000L 1407 #define AGP_CNTL__DIS_RBF_MASK 0x02000000L 1408 #define AGP_CNTL__DIS_RBF 0x02000000L 1409 #define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L 1410 #define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L 1411 #define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L 1412 #define AGP_CNTL__AGP_MISC_MASK 0xc0000000L 1413 1414 // AGP_CNTL 1415 #define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 1416 #define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 1417 #define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 1418 #define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a 1419 #define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b 1420 #define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c 1421 #define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d 1422 #define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e 1423 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f 1424 #define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 1425 #define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 1426 #define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 1427 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 1428 #define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 1429 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 1430 #define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 1431 #define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 1432 #define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 1433 #define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a 1434 #define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b 1435 #define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e 1436 1437 // DISP_MISC_CNTL 1438 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L 1439 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L 1440 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L 1441 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L 1442 #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L 1443 #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L 1444 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L 1445 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L 1446 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L 1447 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L 1448 #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L 1449 #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L 1450 #define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L 1451 #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L 1452 #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L 1453 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L 1454 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L 1455 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L 1456 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L 1457 #define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L 1458 #define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L 1459 #define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L 1460 #define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L 1461 #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L 1462 #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L 1463 #define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L 1464 #define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L 1465 #define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L 1466 #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L 1467 #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L 1468 1469 // DISP_PWR_MAN 1470 #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L 1471 #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L 1472 #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L 1473 #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L 1474 #define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L 1475 #define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L 1476 #define DISP_PWR_MAN__DISP_D3_RST 0x00010000L 1477 #define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L 1478 #define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L 1479 #define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L 1480 #define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L 1481 #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L 1482 #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L 1483 #define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L 1484 #define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L 1485 #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L 1486 #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L 1487 #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L 1488 #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L 1489 #define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L 1490 #define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L 1491 #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L 1492 #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L 1493 #define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L 1494 #define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L 1495 #define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L 1496 #define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L 1497 1498 // MC_IND_INDEX 1499 #define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL 1500 #define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L 1501 #define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L 1502 1503 // MC_IND_DATA 1504 #define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL 1505 1506 // MC_CHP_IO_CNTL_A1 1507 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 1508 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 1509 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 1510 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 1511 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 1512 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 1513 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 1514 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 1515 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 1516 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 1517 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a 1518 #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c 1519 #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e 1520 #define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 1521 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 1522 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 1523 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 1524 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 1525 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 1526 #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a 1527 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c 1528 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e 1529 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f 1530 1531 // MC_CHP_IO_CNTL_B1 1532 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 1533 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 1534 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 1535 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 1536 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 1537 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 1538 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 1539 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 1540 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 1541 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 1542 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a 1543 #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c 1544 #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e 1545 #define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 1546 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 1547 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 1548 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 1549 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 1550 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 1551 #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a 1552 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c 1553 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e 1554 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f 1555 1556 // MC_CHP_IO_CNTL_A1 1557 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L 1558 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L 1559 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L 1560 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L 1561 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L 1562 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L 1563 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L 1564 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L 1565 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L 1566 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L 1567 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L 1568 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L 1569 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L 1570 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L 1571 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L 1572 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L 1573 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L 1574 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L 1575 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L 1576 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L 1577 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L 1578 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L 1579 #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L 1580 #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L 1581 #define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L 1582 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L 1583 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L 1584 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L 1585 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L 1586 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L 1587 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L 1588 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L 1589 #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L 1590 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L 1591 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L 1592 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L 1593 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L 1594 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L 1595 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L 1596 1597 // MC_CHP_IO_CNTL_B1 1598 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L 1599 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L 1600 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L 1601 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L 1602 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L 1603 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L 1604 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L 1605 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L 1606 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L 1607 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L 1608 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L 1609 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L 1610 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L 1611 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L 1612 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L 1613 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L 1614 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L 1615 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L 1616 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L 1617 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L 1618 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L 1619 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L 1620 #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L 1621 #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L 1622 #define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L 1623 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L 1624 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L 1625 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L 1626 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L 1627 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L 1628 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L 1629 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L 1630 #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L 1631 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L 1632 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L 1633 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L 1634 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L 1635 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L 1636 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L 1637 1638 // MEM_SDRAM_MODE_REG 1639 #define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL 1640 #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L 1641 #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L 1642 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L 1643 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L 1644 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L 1645 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L 1646 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L 1647 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L 1648 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L 1649 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L 1650 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L 1651 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L 1652 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L 1653 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L 1654 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L 1655 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L 1656 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L 1657 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L 1658 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L 1659 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L 1660 1661 // MEM_SDRAM_MODE_REG 1662 #define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 1663 #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 1664 #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 1665 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 1666 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 1667 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 1668 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a 1669 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b 1670 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c 1671 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d 1672 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e 1673 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f 1674 1675 // MEM_REFRESH_CNTL 1676 #define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL 1677 #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L 1678 #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L 1679 #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L 1680 #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L 1681 #define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L 1682 #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L 1683 #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L 1684 #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L 1685 #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L 1686 #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L 1687 #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L 1688 #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L 1689 #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L 1690 #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L 1691 #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L 1692 #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L 1693 #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L 1694 #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L 1695 #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L 1696 #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L 1697 #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L 1698 #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L 1699 #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L 1700 #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L 1701 #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L 1702 #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L 1703 #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L 1704 1705 // MC_STATUS 1706 #define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L 1707 #define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L 1708 #define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L 1709 #define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L 1710 #define MC_STATUS__MC_IDLE_MASK 0x00000004L 1711 #define MC_STATUS__MC_IDLE 0x00000004L 1712 #define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L 1713 #define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L 1714 #define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L 1715 #define MC_STATUS__TEST_OUT_R_BACK 0x00000800L 1716 #define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L 1717 #define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L 1718 #define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L 1719 #define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L 1720 #define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L 1721 #define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L 1722 1723 // MDLL_CKO 1724 #define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L 1725 #define MDLL_CKO__MCKOA_SLEEP 0x00000001L 1726 #define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L 1727 #define MDLL_CKO__MCKOA_RESET 0x00000002L 1728 #define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL 1729 #define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L 1730 #define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L 1731 #define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L 1732 #define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L 1733 #define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L 1734 #define MDLL_CKO__MCKOA_BP_SEL 0x00008000L 1735 #define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L 1736 #define MDLL_CKO__MCKOB_SLEEP 0x00010000L 1737 #define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L 1738 #define MDLL_CKO__MCKOB_RESET 0x00020000L 1739 #define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L 1740 #define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L 1741 #define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L 1742 #define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L 1743 #define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L 1744 #define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L 1745 #define MDLL_CKO__MCKOB_BP_SEL 0x80000000L 1746 1747 // MDLL_RDCKA 1748 #define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L 1749 #define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L 1750 #define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L 1751 #define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L 1752 #define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL 1753 #define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L 1754 #define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L 1755 #define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L 1756 #define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L 1757 #define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L 1758 #define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L 1759 #define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L 1760 #define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L 1761 #define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L 1762 #define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L 1763 #define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L 1764 #define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L 1765 #define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L 1766 #define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L 1767 #define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L 1768 #define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L 1769 #define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L 1770 #define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L 1771 #define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L 1772 #define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L 1773 #define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L 1774 1775 // MDLL_RDCKB 1776 #define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L 1777 #define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L 1778 #define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L 1779 #define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L 1780 #define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL 1781 #define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L 1782 #define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L 1783 #define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L 1784 #define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L 1785 #define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L 1786 #define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L 1787 #define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L 1788 #define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L 1789 #define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L 1790 #define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L 1791 #define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L 1792 #define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L 1793 #define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L 1794 #define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L 1795 #define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L 1796 #define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L 1797 #define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L 1798 #define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L 1799 #define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L 1800 #define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L 1801 #define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L 1802 1803 #define pllVCLK_ECP_CNTL 0x0008 1804 #define pllDISP_TEST_MACRO_RW_WRITE 0x001A 1805 #define pllDISP_TEST_MACRO_RW_READ 0x001B 1806 #define pllDISP_TEST_MACRO_RW_DATA 0x001C 1807 #define pllDISP_TEST_MACRO_RW_CNTL 0x001D 1808 #define pllPIXCLKS_CNTL 0x002D 1809 #define pllPPLL_DIV_0 0x0004 1810 #define pllPPLL_DIV_1 0x0005 1811 #define pllPPLL_DIV_2 0x0006 1812 #define pllPPLL_DIV_3 0x0007 1813 #define pllHTOTAL_CNTL 0x0009 1814 #define pllPLL_TEST_CNTL_M6 0x0013 1815 #define pllP2PLL_DIV_0 0x002C 1816 #define pllHTOTAL2_CNTL 0x002E 1817 #define pllCLK_PIN_CNTL 0x0001 1818 #define pllPPLL_CNTL 0x0002 1819 #define pllPPLL_REF_DIV 0x0003 1820 #define pllSPLL_CNTL 0x000C 1821 #define pllSPLL_AUX_CNTL 0x0024 1822 #define pllSCLK_CNTL_M6 0x000D 1823 #define pllAGP_PLL_CNTL 0x000B 1824 #define pllTV_PLL_FINE_CNTL 0x0020 1825 #define pllTV_PLL_CNTL 0x0021 1826 #define pllTV_PLL_CNTL1 0x0022 1827 #define pllTV_DTO_INCREMENTS 0x0023 1828 #define pllP2PLL_CNTL 0x002A 1829 #define pllP2PLL_REF_DIV 0x002B 1830 #define pllSSPLL_CNTL 0x0030 1831 #define pllSSPLL_REF_DIV 0x0031 1832 #define pllSSPLL_DIV_0 0x0032 1833 #define pllSS_INT_CNTL 0x0033 1834 #define pllSS_TST_CNTL 0x0034 1835 #define pllSCLK_MORE_CNTL 0x0035 1836 #define pllCLK_PWRMGT_CNTL_M6 0x0014 1837 #define pllPLL_PWRMGT_CNTL 0x0015 1838 #define pllM_SPLL_REF_FB_DIV 0x000A 1839 #define pllMPLL_CNTL 0x000E 1840 #define pllMPLL_AUX_CNTL 0x0025 1841 #define pllMDLL_CKO 0x000F 1842 #define pllMDLL_RDCKA 0x0010 1843 #define pllMDLL_RDCKB 0x0011 1844 #define pllMCLK_CNTL_M6 0x0012 1845 #define pllMCLK_MISC 0x001F 1846 #define pllCG_TEST_MACRO_RW_WRITE 0x0016 1847 #define pllCG_TEST_MACRO_RW_READ 0x0017 1848 #define pllCG_TEST_MACRO_RW_DATA 0x0018 1849 #define pllCG_TEST_MACRO_RW_CNTL 0x0019 1850 1851 #define ixMC_PERF_CNTL 0x0000 1852 #define ixMC_PERF_SEL 0x0001 1853 #define ixMC_PERF_REGION_0 0x0002 1854 #define ixMC_PERF_REGION_1 0x0003 1855 #define ixMC_PERF_COUNT_0 0x0004 1856 #define ixMC_PERF_COUNT_1 0x0005 1857 #define ixMC_PERF_COUNT_2 0x0006 1858 #define ixMC_PERF_COUNT_3 0x0007 1859 #define ixMC_PERF_COUNT_MEMCH_A 0x0008 1860 #define ixMC_PERF_COUNT_MEMCH_B 0x0009 1861 #define ixMC_IMP_CNTL 0x000A 1862 #define ixMC_CHP_IO_CNTL_A0 0x000B 1863 #define ixMC_CHP_IO_CNTL_A1 0x000C 1864 #define ixMC_CHP_IO_CNTL_B0 0x000D 1865 #define ixMC_CHP_IO_CNTL_B1 0x000E 1866 #define ixMC_IMP_CNTL_0 0x000F 1867 #define ixTC_MISMATCH_1 0x0010 1868 #define ixTC_MISMATCH_2 0x0011 1869 #define ixMC_BIST_CTRL 0x0012 1870 #define ixREG_COLLAR_WRITE 0x0013 1871 #define ixREG_COLLAR_READ 0x0014 1872 1873 1874 1875 1876 #endif /* _RADEON_H */ 1877 1878