Searched refs:DCRN_UIC_SR (Results 1 – 4 of 4) sorted by relevance
226 mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - bit))); in ppc405_uic_disable_and_ack()231 mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit))); in ppc405_uic_disable_and_ack()233 mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - UIC0_UIC1NC))); in ppc405_uic_disable_and_ack()265 mtdcr(DCRN_UIC_SR(UIC0), 1 << (31 - bit)); in ppc405_uic_end()269 mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit)); in ppc405_uic_end()271 mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - UIC0_UIC1NC))); in ppc405_uic_end()436 mtdcr(DCRN_UIC_SR(UIC1), 0xffffffff); in ppc4xx_pic_init()438 mtdcr(DCRN_UIC_SR(UIC0), 0xffffffff); in ppc4xx_pic_init()
162 mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */ in board_setup_irq()
310 #define DCRN_UIC_SR(base) (base + 0x0) macro
169 #define DCRN_UIC_SR(base) (base + 0x0) macro