1 #ifndef _IBM_LANA_INCLUDE_ 2 #define _IBM_LANA_INCLUDE_ 3 4 #ifdef _IBM_LANA_DRIVER_ 5 6 /* version-dependent functions/structures */ 7 8 #if LINUX_VERSION_CODE >= 0x020318 9 #define IBMLANA_READB(addr) isa_readb(addr) 10 #define IBMLANA_TOIO(dest, src, len) isa_memcpy_toio(dest, src, len) 11 #define IBMLANA_FROMIO(dest, src, len) isa_memcpy_fromio(dest, src, len) 12 #define IBMLANA_SETIO(dest, val, len) isa_memset_io(dest, val, len) 13 #define IBMLANA_NETDEV net_device 14 #else 15 #define IBMLANA_READB(addr) readb(addr) 16 #define IBMLANA_TOIO(dest, src, len) memcpy_toio(dest, src, len) 17 #define IBMLANA_FROMIO(dest, src, len) memcpy_fromio(dest, src, len) 18 #define IBMLANA_SETIO(dest, val, len) memset_io(dest, val, len) 19 #define IBMLANA_NETDEV device 20 #endif 21 22 /* maximum packet size */ 23 24 #define PKTSIZE 1524 25 26 /* number of transmit buffers */ 27 28 #define TXBUFCNT 4 29 30 /* Adapter ID's */ 31 #define IBM_LANA_ID 0xffe0 32 33 /* media enumeration - defined in a way that it fits onto the LAN/A's 34 POS registers... */ 35 36 typedef enum { Media_10BaseT, Media_10Base5, 37 Media_Unknown, Media_10Base2, Media_Count 38 } ibmlana_medium; 39 40 /* private structure */ 41 42 typedef struct { 43 unsigned int slot; /* MCA-Slot-# */ 44 struct net_device_stats stat; /* packet statistics */ 45 int realirq; /* memorizes actual IRQ, even when 46 currently not allocated */ 47 ibmlana_medium medium; /* physical cannector */ 48 u32 tdastart, txbufstart, /* addresses */ 49 rrastart, rxbufstart, rdastart, rxbufcnt, txusedcnt; 50 int nextrxdescr, /* next rx descriptor to be used */ 51 lastrxdescr, /* last free rx descriptor */ 52 nexttxdescr, /* last tx descriptor to be used */ 53 currtxdescr, /* tx descriptor currently tx'ed */ 54 txused[TXBUFCNT]; /* busy flags */ 55 } ibmlana_priv; 56 57 /* this card uses quite a lot of I/O ports...luckily the MCA bus decodes 58 a full 64K I/O range... */ 59 60 #define IBM_LANA_IORANGE 0xa0 61 62 /* Command Register: */ 63 64 #define SONIC_CMDREG 0x00 65 #define CMDREG_HTX 0x0001 /* halt transmission */ 66 #define CMDREG_TXP 0x0002 /* start transmission */ 67 #define CMDREG_RXDIS 0x0004 /* disable receiver */ 68 #define CMDREG_RXEN 0x0008 /* enable receiver */ 69 #define CMDREG_STP 0x0010 /* stop timer */ 70 #define CMDREG_ST 0x0020 /* start timer */ 71 #define CMDREG_RST 0x0080 /* software reset */ 72 #define CMDREG_RRRA 0x0100 /* force SONIC to read first RRA */ 73 #define CMDREG_LCAM 0x0200 /* force SONIC to read CAM descrs */ 74 75 /* Data Configuration Register */ 76 77 #define SONIC_DCREG 0x02 78 #define DCREG_EXBUS 0x8000 /* Extended Bus Mode */ 79 #define DCREG_LBR 0x2000 /* Latched Bus Retry */ 80 #define DCREG_PO1 0x1000 /* Programmable Outputs */ 81 #define DCREG_PO0 0x0800 82 #define DCREG_SBUS 0x0400 /* Synchronous Bus Mode */ 83 #define DCREG_USR1 0x0200 /* User Definable Pins */ 84 #define DCREG_USR0 0x0100 85 #define DCREG_WC0 0x0000 /* 0..3 Wait States */ 86 #define DCREG_WC1 0x0040 87 #define DCREG_WC2 0x0080 88 #define DCREG_WC3 0x00c0 89 #define DCREG_DW16 0x0000 /* 16 bit Bus Mode */ 90 #define DCREG_DW32 0x0020 /* 32 bit Bus Mode */ 91 #define DCREG_BMS 0x0010 /* Block Mode Select */ 92 #define DCREG_RFT4 0x0000 /* 4/8/16/24 bytes RX Threshold */ 93 #define DCREG_RFT8 0x0004 94 #define DCREG_RFT16 0x0008 95 #define DCREG_RFT24 0x000c 96 #define DCREG_TFT8 0x0000 /* 8/16/24/28 bytes TX Threshold */ 97 #define DCREG_TFT16 0x0001 98 #define DCREG_TFT24 0x0002 99 #define DCREG_TFT28 0x0003 100 101 /* Receive Control Register */ 102 103 #define SONIC_RCREG 0x04 104 #define RCREG_ERR 0x8000 /* accept damaged and collided pkts */ 105 #define RCREG_RNT 0x4000 /* accept packets that are < 64 */ 106 #define RCREG_BRD 0x2000 /* accept broadcasts */ 107 #define RCREG_PRO 0x1000 /* promiscous mode */ 108 #define RCREG_AMC 0x0800 /* accept all multicasts */ 109 #define RCREG_LB_NONE 0x0000 /* no loopback */ 110 #define RCREG_LB_MAC 0x0200 /* MAC loopback */ 111 #define RCREG_LB_ENDEC 0x0400 /* ENDEC loopback */ 112 #define RCREG_LB_XVR 0x0600 /* Transceiver loopback */ 113 #define RCREG_MC 0x0100 /* Multicast received */ 114 #define RCREG_BC 0x0080 /* Broadcast received */ 115 #define RCREG_LPKT 0x0040 /* last packet in RBA */ 116 #define RCREG_CRS 0x0020 /* carrier sense present */ 117 #define RCREG_COL 0x0010 /* recv'd packet with collision */ 118 #define RCREG_CRCR 0x0008 /* recv'd packet with CRC error */ 119 #define RCREG_FAER 0x0004 /* recv'd packet with inv. framing */ 120 #define RCREG_LBK 0x0002 /* recv'd loopback packet */ 121 #define RCREG_PRX 0x0001 /* recv'd packet is OK */ 122 123 /* Transmit Control Register */ 124 125 #define SONIC_TCREG 0x06 126 #define TCREG_PINT 0x8000 /* generate interrupt after TDA read */ 127 #define TCREG_POWC 0x4000 /* timer start out of window detect */ 128 #define TCREG_CRCI 0x2000 /* inhibit CRC generation */ 129 #define TCREG_EXDIS 0x1000 /* disable excessive deferral timer */ 130 #define TCREG_EXD 0x0400 /* excessive deferral occurred */ 131 #define TCREG_DEF 0x0200 /* single deferral occurred */ 132 #define TCREG_NCRS 0x0100 /* no carrier detected */ 133 #define TCREG_CRSL 0x0080 /* carrier lost */ 134 #define TCREG_EXC 0x0040 /* excessive collisions occurred */ 135 #define TCREG_OWC 0x0020 /* out of window collision occurred */ 136 #define TCREG_PMB 0x0008 /* packet monitored bad */ 137 #define TCREG_FU 0x0004 /* FIFO underrun */ 138 #define TCREG_BCM 0x0002 /* byte count mismatch of fragments */ 139 #define TCREG_PTX 0x0001 /* packet transmitted OK */ 140 141 /* Interrupt Mask Register */ 142 143 #define SONIC_IMREG 0x08 144 #define IMREG_BREN 0x4000 /* interrupt when bus retry occurred */ 145 #define IMREG_HBLEN 0x2000 /* interrupt when heartbeat lost */ 146 #define IMREG_LCDEN 0x1000 /* interrupt when CAM loaded */ 147 #define IMREG_PINTEN 0x0800 /* interrupt when PINT in TDA set */ 148 #define IMREG_PRXEN 0x0400 /* interrupt when packet received */ 149 #define IMREG_PTXEN 0x0200 /* interrupt when packet was sent */ 150 #define IMREG_TXEREN 0x0100 /* interrupt when send failed */ 151 #define IMREG_TCEN 0x0080 /* interrupt when timer completed */ 152 #define IMREG_RDEEN 0x0040 /* interrupt when RDA exhausted */ 153 #define IMREG_RBEEN 0x0020 /* interrupt when RBA exhausted */ 154 #define IMREG_RBAEEN 0x0010 /* interrupt when RBA too short */ 155 #define IMREG_CRCEN 0x0008 /* interrupt when CRC counter rolls */ 156 #define IMREG_FAEEN 0x0004 /* interrupt when FAE counter rolls */ 157 #define IMREG_MPEN 0x0002 /* interrupt when MP counter rolls */ 158 #define IMREG_RFOEN 0x0001 /* interrupt when Rx FIFO overflows */ 159 160 /* Interrupt Status Register */ 161 162 #define SONIC_ISREG 0x0a 163 #define ISREG_BR 0x4000 /* bus retry occurred */ 164 #define ISREG_HBL 0x2000 /* heartbeat lost */ 165 #define ISREG_LCD 0x1000 /* CAM loaded */ 166 #define ISREG_PINT 0x0800 /* PINT in TDA set */ 167 #define ISREG_PKTRX 0x0400 /* packet received */ 168 #define ISREG_TXDN 0x0200 /* packet was sent */ 169 #define ISREG_TXER 0x0100 /* send failed */ 170 #define ISREG_TC 0x0080 /* timer completed */ 171 #define ISREG_RDE 0x0040 /* RDA exhausted */ 172 #define ISREG_RBE 0x0020 /* RBA exhausted */ 173 #define ISREG_RBAE 0x0010 /* RBA too short for received frame */ 174 #define ISREG_CRC 0x0008 /* CRC counter rolls over */ 175 #define ISREG_FAE 0x0004 /* FAE counter rolls over */ 176 #define ISREG_MP 0x0002 /* MP counter rolls over */ 177 #define ISREG_RFO 0x0001 /* Rx FIFO overflows */ 178 179 #define SONIC_UTDA 0x0c /* current transmit descr address */ 180 #define SONIC_CTDA 0x0e 181 182 #define SONIC_URDA 0x1a /* current receive descr address */ 183 #define SONIC_CRDA 0x1c 184 185 #define SONIC_CRBA0 0x1e /* current receive buffer address */ 186 #define SONIC_CRBA1 0x20 187 188 #define SONIC_RBWC0 0x22 /* word count in receive buffer */ 189 #define SONIC_RBWC1 0x24 190 191 #define SONIC_EOBC 0x26 /* minimum space to be free in RBA */ 192 193 #define SONIC_URRA 0x28 /* upper address of CDA & Recv Area */ 194 195 #define SONIC_RSA 0x2a /* start of receive resource area */ 196 197 #define SONIC_REA 0x2c /* end of receive resource area */ 198 199 #define SONIC_RRP 0x2e /* resource read pointer */ 200 201 #define SONIC_RWP 0x30 /* resource write pointer */ 202 203 #define SONIC_CAMEPTR 0x42 /* CAM entry pointer */ 204 205 #define SONIC_CAMADDR2 0x44 /* CAM address ports */ 206 #define SONIC_CAMADDR1 0x46 207 #define SONIC_CAMADDR0 0x48 208 209 #define SONIC_CAMPTR 0x4c /* lower address of CDA */ 210 211 #define SONIC_CAMCNT 0x4e /* # of CAM descriptors to load */ 212 213 /* Data Configuration Register 2 */ 214 215 #define SONIC_DCREG2 0x7e 216 #define DCREG2_EXPO3 0x8000 /* extended programmable outputs */ 217 #define DCREG2_EXPO2 0x4000 218 #define DCREG2_EXPO1 0x2000 219 #define DCREG2_EXPO0 0x1000 220 #define DCREG2_HD 0x0800 /* heartbeat disable */ 221 #define DCREG2_JD 0x0200 /* jabber timer disable */ 222 #define DCREG2_AUTO 0x0100 /* enable AUI/TP auto selection */ 223 #define DCREG2_XWRAP 0x0040 /* TP transceiver loopback */ 224 #define DCREG2_PH 0x0010 /* HOLD request timing */ 225 #define DCREG2_PCM 0x0004 /* packet compress when matched */ 226 #define DCREG2_PCNM 0x0002 /* packet compress when not matched */ 227 #define DCREG2_RJCM 0x0001 /* inverse packet match via CAM */ 228 229 /* Board Control Register: Enable RAM, Interrupts... */ 230 231 #define BCMREG 0x80 232 #define BCMREG_RAMEN 0x80 /* switch over to RAM */ 233 #define BCMREG_IPEND 0x40 /* interrupt pending ? */ 234 #define BCMREG_RESET 0x08 /* reset board */ 235 #define BCMREG_16BIT 0x04 /* adapter in 16-bit slot */ 236 #define BCMREG_RAMWIN 0x02 /* enable RAM window */ 237 #define BCMREG_IEN 0x01 /* interrupt enable */ 238 239 /* MAC Address PROM */ 240 241 #define MACADDRPROM 0x92 242 243 /* structure of a CAM entry */ 244 245 typedef struct { 246 u32 index; /* pointer into CAM area */ 247 u32 addr0; /* address part (bits 0..15 used) */ 248 u32 addr1; 249 u32 addr2; 250 } camentry_t; 251 252 /* structure of a receive resource */ 253 254 typedef struct { 255 u32 startlo; /* start address (bits 0..15 used) */ 256 u32 starthi; 257 u32 cntlo; /* size in 16-bit quantities */ 258 u32 cnthi; 259 } rra_t; 260 261 /* structure of a receive descriptor */ 262 263 typedef struct { 264 u32 status; /* packet status */ 265 u32 length; /* length in bytes */ 266 u32 startlo; /* start address */ 267 u32 starthi; 268 u32 seqno; /* frame sequence */ 269 u32 link; /* pointer to next descriptor */ 270 /* bit 0 = EOL */ 271 u32 inuse; /* !=0 --> free for SONIC to write */ 272 } rda_t; 273 274 /* structure of a transmit descriptor */ 275 276 typedef struct { 277 u32 status; /* transmit status */ 278 u32 config; /* value for TCR */ 279 u32 length; /* total length */ 280 u32 fragcount; /* number of fragments */ 281 u32 startlo; /* start address of fragment */ 282 u32 starthi; 283 u32 fraglength; /* length of this fragment */ 284 /* more address/length triplets may */ 285 /* follow here */ 286 u32 link; /* pointer to next descriptor */ 287 /* bit 0 = EOL */ 288 } tda_t; 289 290 #endif /* _IBM_LANA_DRIVER_ */ 291 292 extern int ibmlana_probe(struct IBMLANA_NETDEV *); 293 294 295 #endif /* _IBM_LANA_INCLUDE_ */ 296