1 /* 2 * linux/drivers/video/sgivwfb.h -- SGI DBE frame buffer device header 3 * 4 * Copyright (C) 1999 Silicon Graphics, Inc. 5 * Jeffrey Newquist, newquist@engr.sgi.som 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file COPYING in the main directory of this archive for 9 * more details. 10 */ 11 12 #ifndef __SGIVWFB_H__ 13 #define __SGIVWFB_H__ 14 15 #define DBE_GETREG(reg, dest) ((dest) = DBE_REG_BASE->##reg) 16 #define DBE_SETREG(reg, src) DBE_REG_BASE->##reg = (src) 17 #define DBE_IGETREG(reg, idx, dest) ((dest) = DBE_REG_BASE->##reg##[idx]) 18 #define DBE_ISETREG(reg, idx, src) (DBE_REG_BASE->##reg##[idx] = (src)) 19 20 #define MASK(msb, lsb) ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) ) 21 #define GET(v, msb, lsb) ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) ) 22 #define SET(v, f, msb, lsb) ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) ) 23 24 #define GET_DBE_FIELD(reg, field, v) GET((v), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB) 25 #define SET_DBE_FIELD(reg, field, v, f) SET((v), (f), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB) 26 27 /* NOTE: All loads/stores must be 32 bits and uncached */ 28 29 #define DBE_REG_PHYS 0xd0000000 30 #define DBE_REG_SIZE 0x01000000 31 32 typedef struct { 33 volatile u32 ctrlstat; /* 0x000000 general control */ 34 volatile u32 dotclock; /* 0x000004 dot clock PLL control */ 35 volatile u32 i2c; /* 0x000008 crt I2C control */ 36 volatile u32 sysclk; /* 0x00000c system clock PLL control */ 37 volatile u32 i2cfp; /* 0x000010 flat panel I2C control */ 38 volatile u32 id; /* 0x000014 device id/chip revision */ 39 volatile u32 config; /* 0x000018 power on configuration */ 40 volatile u32 bist; /* 0x00001c internal bist status */ 41 42 char _pad0[ 0x010000 - 0x000020 ]; 43 44 volatile u32 vt_xy; /* 0x010000 current dot coords */ 45 volatile u32 vt_xymax; /* 0x010004 maximum dot coords */ 46 volatile u32 vt_vsync; /* 0x010008 vsync on/off */ 47 volatile u32 vt_hsync; /* 0x01000c hsync on/off */ 48 volatile u32 vt_vblank; /* 0x010010 vblank on/off */ 49 volatile u32 vt_hblank; /* 0x010014 hblank on/off */ 50 volatile u32 vt_flags; /* 0x010018 polarity of vt signals */ 51 volatile u32 vt_f2rf_lock; /* 0x01001c f2rf & framelck y coord */ 52 volatile u32 vt_intr01; /* 0x010020 intr 0,1 y coords */ 53 volatile u32 vt_intr23; /* 0x010024 intr 2,3 y coords */ 54 volatile u32 fp_hdrv; /* 0x010028 flat panel hdrv on/off */ 55 volatile u32 fp_vdrv; /* 0x01002c flat panel vdrv on/off */ 56 volatile u32 fp_de; /* 0x010030 flat panel de on/off */ 57 volatile u32 vt_hpixen; /* 0x010034 intrnl horiz pixel on/off*/ 58 volatile u32 vt_vpixen; /* 0x010038 intrnl vert pixel on/off */ 59 volatile u32 vt_hcmap; /* 0x01003c cmap write (horiz) */ 60 volatile u32 vt_vcmap; /* 0x010040 cmap write (vert) */ 61 volatile u32 did_start_xy; /* 0x010044 eol/f did/xy reset val */ 62 volatile u32 crs_start_xy; /* 0x010048 eol/f crs/xy reset val */ 63 volatile u32 vc_start_xy; /* 0x01004c eol/f vc/xy reset val */ 64 65 char _pad1[ 0x020000 - 0x010050 ]; 66 67 volatile u32 ovr_width_tile; /* 0x020000 overlay plane ctrl 0 */ 68 volatile u32 ovr_inhwctrl; /* 0x020004 overlay plane ctrl 1 */ 69 volatile u32 ovr_control; /* 0x020008 overlay plane ctrl 1 */ 70 71 char _pad2[ 0x030000 - 0x02000C ]; 72 73 volatile u32 frm_size_tile; /* 0x030000 normal plane ctrl 0 */ 74 volatile u32 frm_size_pixel; /* 0x030004 normal plane ctrl 1 */ 75 volatile u32 frm_inhwctrl; /* 0x030008 normal plane ctrl 2 */ 76 volatile u32 frm_control; /* 0x03000C normal plane ctrl 3 */ 77 78 char _pad3[ 0x040000 - 0x030010 ]; 79 80 volatile u32 did_inhwctrl; /* 0x040000 DID control */ 81 volatile u32 did_control; /* 0x040004 DID shadow */ 82 83 char _pad4[ 0x048000 - 0x040008 ]; 84 85 volatile u32 mode_regs[32]; /* 0x048000 - 0x04807c WID table */ 86 87 char _pad5[ 0x050000 - 0x048080 ]; 88 89 volatile u32 cmap[6144]; /* 0x050000 - 0x055ffc color map */ 90 91 char _pad6[ 0x058000 - 0x056000 ]; 92 93 volatile u32 cm_fifo; /* 0x058000 color map fifo status */ 94 95 char _pad7[ 0x060000 - 0x058004 ]; 96 97 volatile u32 gmap[256]; /* 0x060000 - 0x0603fc gamma map */ 98 99 char _pad8[ 0x068000 - 0x060400 ]; 100 101 volatile u32 gmap10[1024]; /* 0x068000 - 0x068ffc gamma map */ 102 103 char _pad9[ 0x070000 - 0x069000 ]; 104 105 volatile u32 crs_pos; /* 0x070000 cusror control 0 */ 106 volatile u32 crs_ctl; /* 0x070004 cusror control 1 */ 107 volatile u32 crs_cmap[3]; /* 0x070008 - 0x070010 crs cmap */ 108 109 char _pad10[ 0x078000 - 0x070014 ]; 110 111 volatile u32 crs_glyph[64]; /* 0x078000 - 0x0780fc crs glyph */ 112 113 char _pad11[ 0x080000 - 0x078100 ]; 114 115 volatile u32 vc_0; /* 0x080000 video capture crtl 0 */ 116 volatile u32 vc_1; /* 0x080004 video capture crtl 1 */ 117 volatile u32 vc_2; /* 0x080008 video capture crtl 2 */ 118 volatile u32 vc_3; /* 0x08000c video capture crtl 3 */ 119 volatile u32 vc_4; /* 0x080010 video capture crtl 3 */ 120 volatile u32 vc_5; /* 0x080014 video capture crtl 3 */ 121 volatile u32 vc_6; /* 0x080018 video capture crtl 3 */ 122 volatile u32 vc_7; /* 0x08001c video capture crtl 3 */ 123 volatile u32 vc_8; /* 0x08000c video capture crtl 3 */ 124 } asregs; 125 126 /* Bit mask information */ 127 128 #define DBE_CTRLSTAT_CHIPID_MSB 3 129 #define DBE_CTRLSTAT_CHIPID_LSB 0 130 #define DBE_CTRLSTAT_SENSE_N_MSB 4 131 #define DBE_CTRLSTAT_SENSE_N_LSB 4 132 #define DBE_CTRLSTAT_PCLKSEL_MSB 29 133 #define DBE_CTRLSTAT_PCLKSEL_LSB 28 134 135 #define DBE_DOTCLK_M_MSB 7 136 #define DBE_DOTCLK_M_LSB 0 137 #define DBE_DOTCLK_N_MSB 13 138 #define DBE_DOTCLK_N_LSB 8 139 #define DBE_DOTCLK_P_MSB 15 140 #define DBE_DOTCLK_P_LSB 14 141 #define DBE_DOTCLK_RUN_MSB 20 142 #define DBE_DOTCLK_RUN_LSB 20 143 144 #define DBE_VT_XY_VT_FREEZE_MSB 31 145 #define DBE_VT_XY_VT_FREEZE_LSB 31 146 147 #define DBE_VT_VSYNC_VT_VSYNC_ON_MSB 23 148 #define DBE_VT_VSYNC_VT_VSYNC_ON_LSB 12 149 #define DBE_VT_VSYNC_VT_VSYNC_OFF_MSB 11 150 #define DBE_VT_VSYNC_VT_VSYNC_OFF_LSB 0 151 152 #define DBE_VT_HSYNC_VT_HSYNC_ON_MSB 23 153 #define DBE_VT_HSYNC_VT_HSYNC_ON_LSB 12 154 #define DBE_VT_HSYNC_VT_HSYNC_OFF_MSB 11 155 #define DBE_VT_HSYNC_VT_HSYNC_OFF_LSB 0 156 157 #define DBE_VT_VBLANK_VT_VBLANK_ON_MSB 23 158 #define DBE_VT_VBLANK_VT_VBLANK_ON_LSB 12 159 #define DBE_VT_VBLANK_VT_VBLANK_OFF_MSB 11 160 #define DBE_VT_VBLANK_VT_VBLANK_OFF_LSB 0 161 162 #define DBE_VT_HBLANK_VT_HBLANK_ON_MSB 23 163 #define DBE_VT_HBLANK_VT_HBLANK_ON_LSB 12 164 #define DBE_VT_HBLANK_VT_HBLANK_OFF_MSB 11 165 #define DBE_VT_HBLANK_VT_HBLANK_OFF_LSB 0 166 167 #define DBE_VT_VCMAP_VT_VCMAP_ON_MSB 23 168 #define DBE_VT_VCMAP_VT_VCMAP_ON_LSB 12 169 #define DBE_VT_VCMAP_VT_VCMAP_OFF_MSB 11 170 #define DBE_VT_VCMAP_VT_VCMAP_OFF_LSB 0 171 172 #define DBE_VT_HCMAP_VT_HCMAP_ON_MSB 23 173 #define DBE_VT_HCMAP_VT_HCMAP_ON_LSB 12 174 #define DBE_VT_HCMAP_VT_HCMAP_OFF_MSB 11 175 #define DBE_VT_HCMAP_VT_HCMAP_OFF_LSB 0 176 177 #define DBE_VT_XYMAX_VT_MAXX_MSB 11 178 #define DBE_VT_XYMAX_VT_MAXX_LSB 0 179 #define DBE_VT_XYMAX_VT_MAXY_MSB 23 180 #define DBE_VT_XYMAX_VT_MAXY_LSB 12 181 182 #define DBE_VT_HPIXEN_VT_HPIXEN_ON_MSB 23 183 #define DBE_VT_HPIXEN_VT_HPIXEN_ON_LSB 12 184 #define DBE_VT_HPIXEN_VT_HPIXEN_OFF_MSB 11 185 #define DBE_VT_HPIXEN_VT_HPIXEN_OFF_LSB 0 186 187 #define DBE_VT_VPIXEN_VT_VPIXEN_ON_MSB 23 188 #define DBE_VT_VPIXEN_VT_VPIXEN_ON_LSB 12 189 #define DBE_VT_VPIXEN_VT_VPIXEN_OFF_MSB 11 190 #define DBE_VT_VPIXEN_VT_VPIXEN_OFF_LSB 0 191 192 #define DBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0 193 #define DBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0 194 195 #define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0 196 #define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0 197 198 #define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13 199 #define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13 200 201 #define DBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0 202 #define DBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0 203 #define DBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31 204 #define DBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9 205 #define DBE_FRM_CONTROL_FRM_LINEAR_MSB 1 206 #define DBE_FRM_CONTROL_FRM_LINEAR_LSB 1 207 208 #define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0 209 #define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0 210 211 #define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12 212 #define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5 213 #define DBE_FRM_SIZE_TILE_FRM_RHS_MSB 4 214 #define DBE_FRM_SIZE_TILE_FRM_RHS_LSB 0 215 #define DBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14 216 #define DBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13 217 #define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15 218 #define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15 219 220 #define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31 221 #define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16 222 223 #define DBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0 224 #define DBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0 225 #define DBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0 226 #define DBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0 227 228 #define DBE_DID_START_XY_DID_STARTY_MSB 23 229 #define DBE_DID_START_XY_DID_STARTY_LSB 12 230 #define DBE_DID_START_XY_DID_STARTX_MSB 11 231 #define DBE_DID_START_XY_DID_STARTX_LSB 0 232 233 #define DBE_CRS_START_XY_CRS_STARTY_MSB 23 234 #define DBE_CRS_START_XY_CRS_STARTY_LSB 12 235 #define DBE_CRS_START_XY_CRS_STARTX_MSB 11 236 #define DBE_CRS_START_XY_CRS_STARTX_LSB 0 237 238 #define DBE_WID_TYP_MSB 4 239 #define DBE_WID_TYP_LSB 2 240 #define DBE_WID_BUF_MSB 1 241 #define DBE_WID_BUF_LSB 0 242 243 #define DBE_VC_START_XY_VC_STARTY_MSB 23 244 #define DBE_VC_START_XY_VC_STARTY_LSB 12 245 #define DBE_VC_START_XY_VC_STARTX_MSB 11 246 #define DBE_VC_START_XY_VC_STARTX_LSB 0 247 248 /* Constants */ 249 250 #define DBE_FRM_DEPTH_8 0 251 #define DBE_FRM_DEPTH_16 1 252 #define DBE_FRM_DEPTH_32 2 253 254 #define DBE_CMODE_I8 0 255 #define DBE_CMODE_I12 1 256 #define DBE_CMODE_RG3B2 2 257 #define DBE_CMODE_RGB4 3 258 #define DBE_CMODE_ARGB5 4 259 #define DBE_CMODE_RGB8 5 260 #define DBE_CMODE_RGBA5 6 261 #define DBE_CMODE_RGB10 7 262 263 #define DBE_BMODE_BOTH 3 264 265 #define DBE_CRS_MAGIC 54 266 267 /* Config Register (DBE Only) Definitions */ 268 269 #define DBE_CONFIG_VDAC_ENABLE 0x00000001 270 #define DBE_CONFIG_VDAC_GSYNC 0x00000002 271 #define DBE_CONFIG_VDAC_PBLANK 0x00000004 272 #define DBE_CONFIG_FPENABLE 0x00000008 273 #define DBE_CONFIG_LENDIAN 0x00000020 274 #define DBE_CONFIG_TILEHIST 0x00000040 275 #define DBE_CONFIG_EXT_ADDR 0x00000080 276 277 #define DBE_CONFIG_FBDEV ( DBE_CONFIG_VDAC_ENABLE | \ 278 DBE_CONFIG_VDAC_GSYNC | \ 279 DBE_CONFIG_VDAC_PBLANK | \ 280 DBE_CONFIG_LENDIAN | \ 281 DBE_CONFIG_EXT_ADDR ) 282 283 /* 284 * Available Video Timings and Corresponding Indices 285 */ 286 287 typedef enum { 288 DBE_VT_640_480_60, 289 290 DBE_VT_800_600_60, 291 DBE_VT_800_600_75, 292 DBE_VT_800_600_120, 293 294 DBE_VT_1024_768_50, 295 DBE_VT_1024_768_60, 296 DBE_VT_1024_768_75, 297 DBE_VT_1024_768_85, 298 DBE_VT_1024_768_120, 299 300 DBE_VT_1280_1024_50, 301 DBE_VT_1280_1024_60, 302 DBE_VT_1280_1024_75, 303 DBE_VT_1280_1024_85, 304 305 DBE_VT_1600_1024_53, 306 DBE_VT_1600_1024_60, 307 308 DBE_VT_1600_1200_50, 309 DBE_VT_1600_1200_60, 310 DBE_VT_1600_1200_75, 311 312 DBE_VT_1920_1080_50, 313 DBE_VT_1920_1080_60, 314 DBE_VT_1920_1080_72, 315 316 DBE_VT_1920_1200_50, 317 DBE_VT_1920_1200_60, 318 DBE_VT_1920_1200_66, 319 320 DBE_VT_UNKNOWN 321 } dbe_timing_t; 322 323 324 325 /* 326 * Crime Video Timing Data Structure 327 */ 328 329 typedef struct dbe_timing_info 330 { 331 dbe_timing_t type; 332 int flags; 333 short width; /* Monitor resolution */ 334 short height; 335 int fields_sec; /* fields/sec (Hz -3 dec. places */ 336 int cfreq; /* pixel clock frequency (MHz -3 dec. places) */ 337 short htotal; /* Horizontal total pixels */ 338 short hblank_start; /* Horizontal blank start */ 339 short hblank_end; /* Horizontal blank end */ 340 short hsync_start; /* Horizontal sync start */ 341 short hsync_end; /* Horizontal sync end */ 342 short vtotal; /* Vertical total lines */ 343 short vblank_start; /* Vertical blank start */ 344 short vblank_end; /* Vertical blank end */ 345 short vsync_start; /* Vertical sync start */ 346 short vsync_end; /* Vertical sync end */ 347 short pll_m; /* PLL M parameter */ 348 short pll_n; /* PLL P parameter */ 349 short pll_p; /* PLL N parameter */ 350 } dbe_timing_info_t; 351 352 /* Defines for dbe_vof_info_t flags */ 353 354 #define DBE_VOF_UNKNOWNMON 1 355 #define DBE_VOF_STEREO 2 356 #define DBE_VOF_DO_GENSYNC 4 /* enable incoming sync */ 357 #define DBE_VOF_SYNC_ON_GREEN 8 /* sync on green */ 358 #define DBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */ 359 #define DBE_VOF_MAGICKEY 0x2000 /* Backdoor key */ 360 361 /* 362 * DBE Timing Tables 363 */ 364 365 #ifdef INCLUDE_TIMING_TABLE_DATA 366 struct dbe_timing_info dbeVTimings[] = { 367 { 368 DBE_VT_640_480_60, 369 /* flags, width, height, fields_sec, cfreq */ 370 0, 640, 480, 59940, 25175, 371 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 372 800, 640, 800, 656, 752, 373 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 374 525, 480, 525, 490, 492, 375 /* pll_m, pll_n, pll_p */ 376 15, 2, 3 377 }, 378 379 { 380 DBE_VT_800_600_60, 381 /* flags, width, height, fields_sec, cfreq */ 382 0, 800, 600, 60317, 40000, 383 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 384 1056, 800, 1056, 840, 968, 385 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 386 628, 600, 628, 601, 605, 387 /* pll_m, pll_n, pll_p */ 388 3, 1, 1 389 }, 390 391 { 392 DBE_VT_800_600_75, 393 /* flags, width, height, fields_sec, cfreq */ 394 0, 800, 600, 75000, 49500, 395 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 396 1056, 800, 1056, 816, 896, 397 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 398 625, 600, 625, 601, 604, 399 /* pll_m, pll_n, pll_p */ 400 11, 3, 1 401 }, 402 403 { 404 DBE_VT_800_600_120, 405 /* flags, width, height, fields_sec, cfreq */ 406 DBE_VOF_STEREO, 800, 600, 119800, 82978, 407 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 408 1040, 800, 1040, 856, 976, 409 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 410 666, 600, 666, 637, 643, 411 /* pll_m, pll_n, pll_p */ 412 31, 5, 1 413 }, 414 415 { 416 DBE_VT_1024_768_50, 417 /* flags, width, height, fields_sec, cfreq */ 418 0, 1024, 768, 50000, 54163, 419 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 420 1344, 1024, 1344, 1048, 1184, 421 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 422 806, 768, 806, 771, 777, 423 /* pll_m, pll_n, pll_p */ 424 4, 1, 1 425 }, 426 427 { 428 DBE_VT_1024_768_60, 429 /* flags, width, height, fields_sec, cfreq */ 430 0, 1024, 768, 60004, 65000, 431 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 432 1344, 1024, 1344, 1048, 1184, 433 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 434 806, 768, 806, 771, 777, 435 /* pll_m, pll_n, pll_p */ 436 12, 5, 0 437 }, 438 439 { 440 DBE_VT_1024_768_75, 441 /* flags, width, height, fields_sec, cfreq */ 442 0, 1024, 768, 75029, 78750, 443 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 444 1312, 1024, 1312, 1040, 1136, 445 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 446 800, 768, 800, 769, 772, 447 /* pll_m, pll_n, pll_p */ 448 29, 5, 1 449 }, 450 451 { 452 DBE_VT_1024_768_85, 453 /* flags, width, height, fields_sec, cfreq */ 454 0, 1024, 768, 84997, 94500, 455 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 456 1376, 1024, 1376, 1072, 1168, 457 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 458 808, 768, 808, 769, 772, 459 /* pll_m, pll_n, pll_p */ 460 7, 2, 0 461 }, 462 463 { 464 DBE_VT_1024_768_120, 465 /* flags, width, height, fields_sec, cfreq */ 466 DBE_VOF_STEREO, 1024, 768, 119800, 133195, 467 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 468 1376, 1024, 1376, 1072, 1168, 469 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 470 808, 768, 808, 769, 772, 471 /* pll_m, pll_n, pll_p */ 472 5, 1, 0 473 }, 474 475 { 476 DBE_VT_1280_1024_50, 477 /* flags, width, height, fields_sec, cfreq */ 478 0, 1280, 1024, 50000, 89460, 479 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 480 1680, 1280, 1680, 1360, 1480, 481 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 482 1065, 1024, 1065, 1027, 1030, 483 /* pll_m, pll_n, pll_p */ 484 10, 3, 0 485 }, 486 487 { 488 DBE_VT_1280_1024_60, 489 /* flags, width, height, fields_sec, cfreq */ 490 0, 1280, 1024, 60020, 108000, 491 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 492 1688, 1280, 1688, 1328, 1440, 493 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 494 1066, 1024, 1066, 1025, 1028, 495 /* pll_m, pll_n, pll_p */ 496 4, 1, 0 497 }, 498 499 { 500 DBE_VT_1280_1024_75, 501 /* flags, width, height, fields_sec, cfreq */ 502 0, 1280, 1024, 75025, 135000, 503 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 504 1688, 1280, 1688, 1296, 1440, 505 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 506 1066, 1024, 1066, 1025, 1028, 507 /* pll_m, pll_n, pll_p */ 508 5, 1, 0 509 }, 510 511 { 512 DBE_VT_1280_1024_85, 513 /* flags, width, height, fields_sec, cfreq */ 514 0, 1280, 1024, 85024, 157500, 515 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 516 1728, 1280, 1728, 1344, 1504, 517 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 518 1072, 1024, 1072, 1025, 1028, 519 /* pll_m, pll_n, pll_p */ 520 29, 5, 0 521 }, 522 523 { 524 DBE_VT_1600_1024_53, 525 /* flags, width, height, fields_sec, cfreq */ 526 DBE_VOF_FLATPANEL | DBE_VOF_MAGICKEY, 527 1600, 1024, 53000, 107447, 528 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 529 1900, 1600, 1900, 1630, 1730, 530 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 531 1067, 1024, 1067, 1027, 1030, 532 /* pll_m, pll_n, pll_p */ 533 4, 1, 0 534 }, 535 536 { 537 DBE_VT_1600_1024_60, 538 /* flags, width, height, fields_sec, cfreq */ 539 DBE_VOF_FLATPANEL, 1600, 1024, 60000, 106913, 540 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 541 1670, 1600, 1670, 1630, 1650, 542 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 543 1067, 1024, 1067, 1027, 1030, 544 /* pll_m, pll_n, pll_p */ 545 4, 1, 0 546 }, 547 548 { 549 DBE_VT_1600_1200_50, 550 /* flags, width, height, fields_sec, cfreq */ 551 0, 1600, 1200, 50000, 130500, 552 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 553 2088, 1600, 2088, 1644, 1764, 554 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 555 1250, 1200, 1250, 1205, 1211, 556 /* pll_m, pll_n, pll_p */ 557 24, 5, 0 558 }, 559 560 { 561 DBE_VT_1600_1200_60, 562 /* flags, width, height, fields_sec, cfreq */ 563 0, 1600, 1200, 59940, 162000, 564 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 565 2160, 1600, 2160, 1644, 1856, 566 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 567 1250, 1200, 1250, 1201, 1204, 568 /* pll_m, pll_n, pll_p */ 569 6, 1, 0 570 }, 571 572 { 573 DBE_VT_1600_1200_75, 574 /* flags, width, height, fields_sec, cfreq */ 575 0, 1600, 1200, 75000, 202500, 576 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 577 2160, 1600, 2160, 1644, 1856, 578 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 579 1250, 1200, 1250, 1201, 1204, 580 /* pll_m, pll_n, pll_p */ 581 15, 2, 0 582 }, 583 584 { 585 DBE_VT_1920_1080_50, 586 /* flags, width, height, fields_sec, cfreq */ 587 0, 1920, 1080, 50000, 133200, 588 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 589 2368, 1920, 2368, 1952, 2096, 590 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 591 1125, 1080, 1125, 1083, 1086, 592 /* pll_m, pll_n, pll_p */ 593 5, 1, 0 594 }, 595 596 { 597 DBE_VT_1920_1080_60, 598 /* flags, width, height, fields_sec, cfreq */ 599 0, 1920, 1080, 59940, 159840, 600 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 601 2368, 1920, 2368, 1952, 2096, 602 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 603 1125, 1080, 1125, 1083, 1086, 604 /* pll_m, pll_n, pll_p */ 605 6, 1, 0 606 }, 607 608 { 609 DBE_VT_1920_1080_72, 610 /* flags, width, height, fields_sec, cfreq */ 611 0, 1920, 1080, 72000, 216023, 612 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 613 2560, 1920, 2560, 1968, 2184, 614 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 615 1172, 1080, 1172, 1083, 1086, 616 /* pll_m, pll_n, pll_p */ 617 8, 1, 0 618 }, 619 620 { 621 DBE_VT_1920_1200_50, 622 /* flags, width, height, fields_sec, cfreq */ 623 0, 1920, 1200, 50000, 161500, 624 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 625 2584, 1920, 2584, 1984, 2240, 626 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 627 1250, 1200, 1250, 1203, 1206, 628 /* pll_m, pll_n, pll_p */ 629 6, 1, 0 630 }, 631 632 { 633 DBE_VT_1920_1200_60, 634 /* flags, width, height, fields_sec, cfreq */ 635 0, 1920, 1200, 59940, 193800, 636 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 637 2584, 1920, 2584, 1984, 2240, 638 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 639 1250, 1200, 1250, 1203, 1206, 640 /* pll_m, pll_n, pll_p */ 641 29, 4, 0 642 }, 643 644 { 645 DBE_VT_1920_1200_66, 646 /* flags, width, height, fields_sec, cfreq */ 647 0, 1920, 1200, 66000, 213180, 648 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ 649 2584, 1920, 2584, 1984, 2240, 650 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ 651 1250, 1200, 1250, 1203, 1206, 652 /* pll_m, pll_n, pll_p */ 653 8, 1, 0 654 } 655 }; 656 657 #define DBE_VT_SIZE (sizeof(dbeVTimings)/sizeof(dbeVTimings[0])) 658 #endif // INCLUDE_TIMING_TABLE_DATA 659 660 #endif // ! __SGIVWFB_H__ 661