Searched refs:DAC (Results 1 – 10 of 10) sorted by relevance
539 spinlock_t DAC; member918 #define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC))919 #define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC))920 #define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)921 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
2424 spin_lock_init(&ACCESS_FBINFO(lock.DAC)); in matroxfb_probe()
112 DAC | | | | | | |126 DAC | | | | | +-------+
78 32-bits in a SAC cycle. For a 64-bit DAC capable device, this needs124 here is to try for 64-bit DAC addressing, but back down to a128 32-bit SAC addressing is done more efficiently than DAC addressing.132 all 64-bits during a DAC cycle:148 finite resource on many platforms. Please see the "DAC Addressing289 the upper 32-bits and thus perform DAC cycles, consistent allocation586 64-bit DMA and DAC cycle support598 DAC Addressing for Address Space Hungry Devices613 may use DAC cycles to directly address all of physical memory.632 layer with your devices DAC addressing capabilities:[all …]
8644 This option only applies to PCI-SCSI chip that are PCI DAC capable 8658 properly engineered PCI DAC capable host bridges. You may configure8664 DAC cycles.28949 properly with 32-bit PCI devices that do not support DAC (Double Address29304 # LocalWords: Sitor Amtor Pactor GTOR hayes TX TMOUT JFdocs BIGMEM DAC IRQ's
148 - Sometimes the driver will not recognise the DAC , and the
221 G400 manual, in description of DAC register 0x1F. For normal operation
118 - Do not enable PCI DAC cycles. This just broke support for 511 - Ignore chips that are driven by SISL RAID (DAC 960).
228 - Ignore chips that are driven by SISL RAID (DAC 960).
1421 1044 c05b 2400A UDMA Four Channel DAC