1 /***************************************************************************\ 2 |* *| 3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| 4 |* *| 5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *| 6 |* international laws. Users and possessors of this source code are *| 7 |* hereby granted a nonexclusive, royalty-free copyright license to *| 8 |* use this code in individual and commercial software. *| 9 |* *| 10 |* Any use of this source code must include, in the user documenta- *| 11 |* tion and internal comments to the code, notices to the end user *| 12 |* as follows: *| 13 |* *| 14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| 15 |* *| 16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| 17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| 18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| 19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| 20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| 21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| 22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| 23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| 24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| 25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| 26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| 27 |* *| 28 |* U.S. Government End Users. This source code is a "commercial *| 29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| 30 |* consisting of "commercial computer software" and "commercial *| 31 |* computer software documentation," as such terms are used in *| 32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| 33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *| 34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| 35 |* all U.S. Government End Users acquire the source code with only *| 36 |* those rights set forth herein. *| 37 |* *| 38 \***************************************************************************/ 39 40 /* 41 * GPL licensing note -- nVidia is allowing a liberal interpretation of 42 * the documentation restriction above, to merely say that this nVidia's 43 * copyright and disclaimer should be included with all code derived 44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 45 */ 46 47 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.6 2000/02/08 17:19:12 dawes Exp $ */ 48 #ifndef __RIVA_HW_H__ 49 #define __RIVA_HW_H__ 50 #define RIVA_SW_VERSION 0x00010003 51 52 /* 53 * Typedefs to force certain sized values. 54 */ 55 typedef unsigned char U008; 56 typedef unsigned short U016; 57 typedef unsigned int U032; 58 59 /* 60 * HW access macros. 61 */ 62 #if defined(__powerpc__) 63 #include <asm/io.h> 64 #define NV_WR08(p,i,d) out_8(p+i, d) 65 #define NV_RD08(p,i) in_8(p+i) 66 #else 67 #define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d)) 68 #define NV_RD08(p,i) (((U008 *)(p))[i]) 69 #endif 70 #define NV_WR16(p,i,d) (((U016 *)(p))[(i)/2]=(d)) 71 #define NV_RD16(p,i) (((U016 *)(p))[(i)/2]) 72 #define NV_WR32(p,i,d) (((U032 *)(p))[(i)/4]=(d)) 73 #define NV_RD32(p,i) (((U032 *)(p))[(i)/4]) 74 #define VGA_WR08(p,i,d) NV_WR08(p,i,d) 75 #define VGA_RD08(p,i) NV_RD08(p,i) 76 77 /* 78 * Define supported architectures. 79 */ 80 #define NV_ARCH_03 0x03 81 #define NV_ARCH_04 0x04 82 #define NV_ARCH_10 0x10 83 #define NV_ARCH_20 0x20 84 85 /***************************************************************************\ 86 * * 87 * FIFO registers. * 88 * * 89 \***************************************************************************/ 90 91 /* 92 * Raster OPeration. Windows style ROP3. 93 */ 94 typedef volatile struct 95 { 96 U032 reserved00[4]; 97 #ifdef __BIG_ENDIAN 98 U032 FifoFree; 99 #else 100 U016 FifoFree; 101 U016 Nop; 102 #endif 103 U032 reserved01[0x0BB]; 104 U032 Rop3; 105 } RivaRop; 106 /* 107 * 8X8 Monochrome pattern. 108 */ 109 typedef volatile struct 110 { 111 U032 reserved00[4]; 112 #ifdef __BIG_ENDIAN 113 U032 FifoFree; 114 #else 115 U016 FifoFree; 116 U016 Nop; 117 #endif 118 U032 reserved01[0x0BD]; 119 U032 Shape; 120 U032 reserved03[0x001]; 121 U032 Color0; 122 U032 Color1; 123 U032 Monochrome[2]; 124 } RivaPattern; 125 /* 126 * Scissor clip rectangle. 127 */ 128 typedef volatile struct 129 { 130 U032 reserved00[4]; 131 #ifdef __BIG_ENDIAN 132 U032 FifoFree; 133 #else 134 U016 FifoFree; 135 U016 Nop; 136 #endif 137 U032 reserved01[0x0BB]; 138 U032 TopLeft; 139 U032 WidthHeight; 140 } RivaClip; 141 /* 142 * 2D filled rectangle. 143 */ 144 typedef volatile struct 145 { 146 U032 reserved00[4]; 147 #ifdef __BIG_ENDIAN 148 U032 FifoFree; 149 #else 150 U016 FifoFree; 151 U016 Nop[1]; 152 #endif 153 U032 reserved01[0x0BC]; 154 U032 Color; 155 U032 reserved03[0x03E]; 156 U032 TopLeft; 157 U032 WidthHeight; 158 } RivaRectangle; 159 /* 160 * 2D screen-screen BLT. 161 */ 162 typedef volatile struct 163 { 164 U032 reserved00[4]; 165 #ifdef __BIG_ENDIAN 166 U032 FifoFree; 167 #else 168 U016 FifoFree; 169 U016 Nop; 170 #endif 171 U032 reserved01[0x0BB]; 172 U032 TopLeftSrc; 173 U032 TopLeftDst; 174 U032 WidthHeight; 175 } RivaScreenBlt; 176 /* 177 * 2D pixel BLT. 178 */ 179 typedef volatile struct 180 { 181 U032 reserved00[4]; 182 #ifdef __BIG_ENDIAN 183 U032 FifoFree; 184 #else 185 U016 FifoFree; 186 U016 Nop[1]; 187 #endif 188 U032 reserved01[0x0BC]; 189 U032 TopLeft; 190 U032 WidthHeight; 191 U032 WidthHeightIn; 192 U032 reserved02[0x03C]; 193 U032 Pixels; 194 } RivaPixmap; 195 /* 196 * Filled rectangle combined with monochrome expand. Useful for glyphs. 197 */ 198 typedef volatile struct 199 { 200 U032 reserved00[4]; 201 #ifdef __BIG_ENDIAN 202 U032 FifoFree; 203 #else 204 U016 FifoFree; 205 U016 Nop; 206 #endif 207 U032 reserved01[0x0BB]; 208 U032 reserved03[(0x040)-1]; 209 U032 Color1A; 210 struct 211 { 212 U032 TopLeft; 213 U032 WidthHeight; 214 } UnclippedRectangle[64]; 215 U032 reserved04[(0x080)-3]; 216 struct 217 { 218 U032 TopLeft; 219 U032 BottomRight; 220 } ClipB; 221 U032 Color1B; 222 struct 223 { 224 U032 TopLeft; 225 U032 BottomRight; 226 } ClippedRectangle[64]; 227 U032 reserved05[(0x080)-5]; 228 struct 229 { 230 U032 TopLeft; 231 U032 BottomRight; 232 } ClipC; 233 U032 Color1C; 234 U032 WidthHeightC; 235 U032 PointC; 236 U032 MonochromeData1C; 237 U032 reserved06[(0x080)+121]; 238 struct 239 { 240 U032 TopLeft; 241 U032 BottomRight; 242 } ClipD; 243 U032 Color1D; 244 U032 WidthHeightInD; 245 U032 WidthHeightOutD; 246 U032 PointD; 247 U032 MonochromeData1D; 248 U032 reserved07[(0x080)+120]; 249 struct 250 { 251 U032 TopLeft; 252 U032 BottomRight; 253 } ClipE; 254 U032 Color0E; 255 U032 Color1E; 256 U032 WidthHeightInE; 257 U032 WidthHeightOutE; 258 U032 PointE; 259 U032 MonochromeData01E; 260 } RivaBitmap; 261 /* 262 * 3D textured, Z buffered triangle. 263 */ 264 typedef volatile struct 265 { 266 U032 reserved00[4]; 267 #ifdef __BIG_ENDIAN 268 U032 FifoFree; 269 #else 270 U016 FifoFree; 271 U016 Nop; 272 #endif 273 U032 reserved01[0x0BC]; 274 U032 TextureOffset; 275 U032 TextureFormat; 276 U032 TextureFilter; 277 U032 FogColor; 278 /* This is a problem on LynxOS */ 279 #ifdef Control 280 #undef Control 281 #endif 282 U032 Control; 283 U032 AlphaTest; 284 U032 reserved02[0x339]; 285 U032 FogAndIndex; 286 U032 Color; 287 float ScreenX; 288 float ScreenY; 289 float ScreenZ; 290 float EyeM; 291 float TextureS; 292 float TextureT; 293 } RivaTexturedTriangle03; 294 typedef volatile struct 295 { 296 U032 reserved00[4]; 297 #ifdef __BIG_ENDIAN 298 U032 FifoFree; 299 #else 300 U016 FifoFree; 301 U016 Nop; 302 #endif 303 U032 reserved01[0x0BB]; 304 U032 ColorKey; 305 U032 TextureOffset; 306 U032 TextureFormat; 307 U032 TextureFilter; 308 U032 Blend; 309 /* This is a problem on LynxOS */ 310 #ifdef Control 311 #undef Control 312 #endif 313 U032 Control; 314 U032 FogColor; 315 U032 reserved02[0x39]; 316 struct 317 { 318 float ScreenX; 319 float ScreenY; 320 float ScreenZ; 321 float EyeM; 322 U032 Color; 323 U032 Specular; 324 float TextureS; 325 float TextureT; 326 } Vertex[16]; 327 U032 DrawTriangle3D; 328 } RivaTexturedTriangle05; 329 /* 330 * 2D line. 331 */ 332 typedef volatile struct 333 { 334 U032 reserved00[4]; 335 #ifdef __BIG_ENDIAN 336 U032 FifoFree; 337 #else 338 U016 FifoFree; 339 U016 Nop[1]; 340 #endif 341 U032 reserved01[0x0BC]; 342 U032 Color; /* source color 0304-0307*/ 343 U032 Reserved02[0x03e]; 344 struct { /* start aliased methods in array 0400- */ 345 U032 point0; /* y_x S16_S16 in pixels 0- 3*/ 346 U032 point1; /* y_x S16_S16 in pixels 4- 7*/ 347 } Lin[16]; /* end of aliased methods in array -047f*/ 348 struct { /* start aliased methods in array 0480- */ 349 U032 point0X; /* in pixels, 0 at left 0- 3*/ 350 U032 point0Y; /* in pixels, 0 at top 4- 7*/ 351 U032 point1X; /* in pixels, 0 at left 8- b*/ 352 U032 point1Y; /* in pixels, 0 at top c- f*/ 353 } Lin32[8]; /* end of aliased methods in array -04ff*/ 354 U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/ 355 struct { /* start aliased methods in array 0580- */ 356 U032 x; /* in pixels, 0 at left 0- 3*/ 357 U032 y; /* in pixels, 0 at top 4- 7*/ 358 } PolyLin32[16]; /* end of aliased methods in array -05ff*/ 359 struct { /* start aliased methods in array 0600- */ 360 U032 color; /* source color 0- 3*/ 361 U032 point; /* y_x S16_S16 in pixels 4- 7*/ 362 } ColorPolyLin[16]; /* end of aliased methods in array -067f*/ 363 } RivaLine; 364 /* 365 * 2D/3D surfaces 366 */ 367 typedef volatile struct 368 { 369 U032 reserved00[4]; 370 #ifdef __BIG_ENDIAN 371 U032 FifoFree; 372 #else 373 U016 FifoFree; 374 U016 Nop; 375 #endif 376 U032 reserved01[0x0BE]; 377 U032 Offset; 378 } RivaSurface; 379 typedef volatile struct 380 { 381 U032 reserved00[4]; 382 #ifdef __BIG_ENDIAN 383 U032 FifoFree; 384 #else 385 U016 FifoFree; 386 U016 Nop; 387 #endif 388 U032 reserved01[0x0BD]; 389 U032 Pitch; 390 U032 RenderBufferOffset; 391 U032 ZBufferOffset; 392 } RivaSurface3D; 393 394 /***************************************************************************\ 395 * * 396 * Virtualized RIVA H/W interface. * 397 * * 398 \***************************************************************************/ 399 400 struct _riva_hw_inst; 401 struct _riva_hw_state; 402 /* 403 * Virtialized chip interface. Makes RIVA 128 and TNT look alike. 404 */ 405 typedef struct _riva_hw_inst 406 { 407 /* 408 * Chip specific settings. 409 */ 410 U032 Architecture; 411 U032 Version; 412 U032 CrystalFreqKHz; 413 U032 RamAmountKBytes; 414 U032 MaxVClockFreqKHz; 415 U032 RamBandwidthKBytesPerSec; 416 U032 EnableIRQ; 417 U032 IO; 418 U032 VBlankBit; 419 U032 FifoFreeCount; 420 U032 FifoEmptyCount; 421 U032 flatPanel; 422 /* 423 * Non-FIFO registers. 424 */ 425 volatile U032 *PCRTC; 426 volatile U032 *PRAMDAC; 427 volatile U032 *PFB; 428 volatile U032 *PFIFO; 429 volatile U032 *PGRAPH; 430 volatile U032 *PEXTDEV; 431 volatile U032 *PTIMER; 432 volatile U032 *PMC; 433 volatile U032 *PRAMIN; 434 volatile U032 *FIFO; 435 volatile U032 *CURSOR; 436 volatile U032 *CURSORPOS; 437 volatile U032 *VBLANKENABLE; 438 volatile U032 *VBLANK; 439 volatile U008 *PCIO; 440 volatile U008 *PVIO; 441 volatile U008 *PDIO; 442 /* 443 * Common chip functions. 444 */ 445 int (*Busy)(struct _riva_hw_inst *); 446 void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int,int,int,int,int,int,int,int,int); 447 void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); 448 void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); 449 void (*SetStartAddress)(struct _riva_hw_inst *,U032); 450 void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032); 451 void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032); 452 int (*ShowHideCursor)(struct _riva_hw_inst *,int); 453 void (*LockUnlock)(struct _riva_hw_inst *, int); 454 /* 455 * Current extended mode settings. 456 */ 457 struct _riva_hw_state *CurrentState; 458 /* 459 * FIFO registers. 460 */ 461 RivaRop *Rop; 462 RivaPattern *Patt; 463 RivaClip *Clip; 464 RivaPixmap *Pixmap; 465 RivaScreenBlt *Blt; 466 RivaBitmap *Bitmap; 467 RivaLine *Line; 468 RivaTexturedTriangle03 *Tri03; 469 RivaTexturedTriangle05 *Tri05; 470 } RIVA_HW_INST; 471 /* 472 * Extended mode state information. 473 */ 474 typedef struct _riva_hw_state 475 { 476 U032 bpp; 477 U032 width; 478 U032 height; 479 U032 repaint0; 480 U032 repaint1; 481 U032 screen; 482 U032 scale; 483 U032 extra; 484 U032 pixel; 485 U032 horiz; 486 U032 arbitration0; 487 U032 arbitration1; 488 U032 vpll; 489 U032 vpll2; 490 U032 pllsel; 491 U032 general; 492 U032 config; 493 U032 cursor0; 494 U032 cursor1; 495 U032 cursor2; 496 U032 offset0; 497 U032 offset1; 498 U032 offset2; 499 U032 offset3; 500 U032 pitch0; 501 U032 pitch1; 502 U032 pitch2; 503 U032 pitch3; 504 } RIVA_HW_STATE; 505 /* 506 * External routines. 507 */ 508 int RivaGetConfig(RIVA_HW_INST *); 509 /* 510 * FIFO Free Count. Should attempt to yield processor if RIVA is busy. 511 */ 512 513 #define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \ 514 { \ 515 while ((hwinst).FifoFreeCount < (cnt)) \ 516 (hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2; \ 517 (hwinst).FifoFreeCount -= (cnt); \ 518 } 519 #endif /* __RIVA_HW_H__ */ 520 521