1 /* 2 * falc.h Description of the Siemens FALC T1/E1 framer. 3 * 4 * Author: Ivan Passos <ivan.passos@cyclades.com> 5 * 6 * Copyright: (c) 2000-2003 Cyclades Corp. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 * 13 */ 14 15 #ifndef _FALC_LH_H 16 #define _FALC_LH_H 17 18 #define NUM_OF_T1_CHANNELS 24 19 #define NUM_OF_E1_CHANNELS 32 20 21 /*>>>>>>>>>>>>>>>>> FALC Register Bits (Transmit Mode) <<<<<<<<<<<<<<<<<<< */ 22 23 /* CMDR (Command Register) 24 ---------------- E1 & T1 ------------------------------ */ 25 #define CMDR_RMC 0x80 26 #define CMDR_RRES 0x40 27 #define CMDR_XREP 0x20 28 #define CMDR_XRES 0x10 29 #define CMDR_XHF 0x08 30 #define CMDR_XTF 0x04 31 #define CMDR_XME 0x02 32 #define CMDR_SRES 0x01 33 34 /* MODE (Mode Register) 35 ----------------- E1 & T1 ----------------------------- */ 36 #define MODE_MDS2 0x80 37 #define MODE_MDS1 0x40 38 #define MODE_MDS0 0x20 39 #define MODE_BRAC 0x10 40 #define MODE_HRAC 0x08 41 42 /* IPC (Interrupt Port Configuration) 43 ----------------- E1 & T1 ----------------------------- */ 44 #define IPC_VIS 0x80 45 #define IPC_SCI 0x04 46 #define IPC_IC1 0x02 47 #define IPC_IC0 0x01 48 49 /* CCR1 (Common Configuration Register 1) 50 ----------------- E1 & T1 ----------------------------- */ 51 #define CCR1_SFLG 0x80 52 #define CCR1_XTS16RA 0x40 53 #define CCR1_BRM 0x40 54 #define CCR1_CASSYM 0x20 55 #define CCR1_EDLX 0x20 56 #define CCR1_EITS 0x10 57 #define CCR1_ITF 0x08 58 #define CCR1_RFT1 0x02 59 #define CCR1_RFT0 0x01 60 61 /* CCR3 (Common Configuration Register 3) 62 ---------------- E1 & T1 ------------------------------ */ 63 64 #define CCR3_PRE1 0x80 65 #define CCR3_PRE0 0x40 66 #define CCR3_EPT 0x20 67 #define CCR3_RADD 0x10 68 #define CCR3_RCRC 0x04 69 #define CCR3_XCRC 0x02 70 71 72 /* RTR1-4 (Receive Timeslot Register 1-4) 73 ---------------- E1 & T1 ------------------------------ */ 74 75 #define RTR1_TS0 0x80 76 #define RTR1_TS1 0x40 77 #define RTR1_TS2 0x20 78 #define RTR1_TS3 0x10 79 #define RTR1_TS4 0x08 80 #define RTR1_TS5 0x04 81 #define RTR1_TS6 0x02 82 #define RTR1_TS7 0x01 83 84 #define RTR2_TS8 0x80 85 #define RTR2_TS9 0x40 86 #define RTR2_TS10 0x20 87 #define RTR2_TS11 0x10 88 #define RTR2_TS12 0x08 89 #define RTR2_TS13 0x04 90 #define RTR2_TS14 0x02 91 #define RTR2_TS15 0x01 92 93 #define RTR3_TS16 0x80 94 #define RTR3_TS17 0x40 95 #define RTR3_TS18 0x20 96 #define RTR3_TS19 0x10 97 #define RTR3_TS20 0x08 98 #define RTR3_TS21 0x04 99 #define RTR3_TS22 0x02 100 #define RTR3_TS23 0x01 101 102 #define RTR4_TS24 0x80 103 #define RTR4_TS25 0x40 104 #define RTR4_TS26 0x20 105 #define RTR4_TS27 0x10 106 #define RTR4_TS28 0x08 107 #define RTR4_TS29 0x04 108 #define RTR4_TS30 0x02 109 #define RTR4_TS31 0x01 110 111 112 /* TTR1-4 (Transmit Timeslot Register 1-4) 113 ---------------- E1 & T1 ------------------------------ */ 114 115 #define TTR1_TS0 0x80 116 #define TTR1_TS1 0x40 117 #define TTR1_TS2 0x20 118 #define TTR1_TS3 0x10 119 #define TTR1_TS4 0x08 120 #define TTR1_TS5 0x04 121 #define TTR1_TS6 0x02 122 #define TTR1_TS7 0x01 123 124 #define TTR2_TS8 0x80 125 #define TTR2_TS9 0x40 126 #define TTR2_TS10 0x20 127 #define TTR2_TS11 0x10 128 #define TTR2_TS12 0x08 129 #define TTR2_TS13 0x04 130 #define TTR2_TS14 0x02 131 #define TTR2_TS15 0x01 132 133 #define TTR3_TS16 0x80 134 #define TTR3_TS17 0x40 135 #define TTR3_TS18 0x20 136 #define TTR3_TS19 0x10 137 #define TTR3_TS20 0x08 138 #define TTR3_TS21 0x04 139 #define TTR3_TS22 0x02 140 #define TTR3_TS23 0x01 141 142 #define TTR4_TS24 0x80 143 #define TTR4_TS25 0x40 144 #define TTR4_TS26 0x20 145 #define TTR4_TS27 0x10 146 #define TTR4_TS28 0x08 147 #define TTR4_TS29 0x04 148 #define TTR4_TS30 0x02 149 #define TTR4_TS31 0x01 150 151 152 153 /* IMR0-4 (Interrupt Mask Register 0-4) 154 155 ----------------- E1 & T1 ----------------------------- */ 156 157 #define IMR0_RME 0x80 158 #define IMR0_RFS 0x40 159 #define IMR0_T8MS 0x20 160 #define IMR0_ISF 0x20 161 #define IMR0_RMB 0x10 162 #define IMR0_CASC 0x08 163 #define IMR0_RSC 0x08 164 #define IMR0_CRC6 0x04 165 #define IMR0_CRC4 0x04 166 #define IMR0_PDEN 0x02 167 #define IMR0_RPF 0x01 168 169 #define IMR1_CASE 0x80 170 #define IMR1_RDO 0x40 171 #define IMR1_ALLS 0x20 172 #define IMR1_XDU 0x10 173 #define IMR1_XMB 0x08 174 #define IMR1_XLSC 0x02 175 #define IMR1_XPR 0x01 176 #define IMR1_LLBSC 0x80 177 178 #define IMR2_FAR 0x80 179 #define IMR2_LFA 0x40 180 #define IMR2_MFAR 0x20 181 #define IMR2_T400MS 0x10 182 #define IMR2_LMFA 0x10 183 #define IMR2_AIS 0x08 184 #define IMR2_LOS 0x04 185 #define IMR2_RAR 0x02 186 #define IMR2_RA 0x01 187 188 #define IMR3_ES 0x80 189 #define IMR3_SEC 0x40 190 #define IMR3_LMFA16 0x20 191 #define IMR3_AIS16 0x10 192 #define IMR3_RA16 0x08 193 #define IMR3_API 0x04 194 #define IMR3_XSLP 0x20 195 #define IMR3_XSLN 0x10 196 #define IMR3_LLBSC 0x08 197 #define IMR3_XRS 0x04 198 #define IMR3_SLN 0x02 199 #define IMR3_SLP 0x01 200 201 #define IMR4_LFA 0x80 202 #define IMR4_FER 0x40 203 #define IMR4_CER 0x20 204 #define IMR4_AIS 0x10 205 #define IMR4_LOS 0x08 206 #define IMR4_CVE 0x04 207 #define IMR4_SLIP 0x02 208 #define IMR4_EBE 0x01 209 210 /* FMR0-5 for E1 and T1 (Framer Mode Register ) */ 211 212 #define FMR0_XC1 0x80 213 #define FMR0_XC0 0x40 214 #define FMR0_RC1 0x20 215 #define FMR0_RC0 0x10 216 #define FMR0_EXTD 0x08 217 #define FMR0_ALM 0x04 218 #define E1_FMR0_FRS 0x02 219 #define T1_FMR0_FRS 0x08 220 #define FMR0_SRAF 0x04 221 #define FMR0_EXLS 0x02 222 #define FMR0_SIM 0x01 223 224 #define FMR1_MFCS 0x80 225 #define FMR1_AFR 0x40 226 #define FMR1_ENSA 0x20 227 #define FMR1_CTM 0x80 228 #define FMR1_SIGM 0x40 229 #define FMR1_EDL 0x20 230 #define FMR1_PMOD 0x10 231 #define FMR1_XFS 0x08 232 #define FMR1_CRC 0x08 233 #define FMR1_ECM 0x04 234 #define FMR1_IMOD 0x02 235 #define FMR1_XAIS 0x01 236 237 #define FMR2_RFS1 0x80 238 #define FMR2_RFS0 0x40 239 #define FMR2_MCSP 0x40 240 #define FMR2_RTM 0x20 241 #define FMR2_SSP 0x20 242 #define FMR2_DAIS 0x10 243 #define FMR2_SAIS 0x08 244 #define FMR2_PLB 0x04 245 #define FMR2_AXRA 0x02 246 #define FMR2_ALMF 0x01 247 #define FMR2_EXZE 0x01 248 249 #define LOOP_RTM 0x40 250 #define LOOP_SFM 0x40 251 #define LOOP_ECLB 0x20 252 #define LOOP_CLA 0x1f 253 254 /*--------------------- E1 ----------------------------*/ 255 #define FMR3_XLD 0x20 256 #define FMR3_XLU 0x10 257 258 /*--------------------- T1 ----------------------------*/ 259 #define FMR4_AIS3 0x80 260 #define FMR4_TM 0x40 261 #define FMR4_XRA 0x20 262 #define FMR4_SSC1 0x10 263 #define FMR4_SSC0 0x08 264 #define FMR4_AUTO 0x04 265 #define FMR4_FM1 0x02 266 #define FMR4_FM0 0x01 267 268 #define FMR5_SRS 0x80 269 #define FMR5_EIBR 0x40 270 #define FMR5_XLD 0x20 271 #define FMR5_XLU 0x10 272 273 274 /* LOOP (Channel Loop Back) 275 276 ------------------ E1 & T1 ---------------------------- */ 277 278 #define LOOP_SFM 0x40 279 #define LOOP_ECLB 0x20 280 #define LOOP_CLA4 0x10 281 #define LOOP_CLA3 0x08 282 #define LOOP_CLA2 0x04 283 #define LOOP_CLA1 0x02 284 #define LOOP_CLA0 0x01 285 286 287 288 /* XSW (Transmit Service Word Pulseframe) 289 290 ------------------- E1 --------------------------- */ 291 292 #define XSW_XSIS 0x80 293 #define XSW_XTM 0x40 294 #define XSW_XRA 0x20 295 #define XSW_XY0 0x10 296 #define XSW_XY1 0x08 297 #define XSW_XY2 0x04 298 #define XSW_XY3 0x02 299 #define XSW_XY4 0x01 300 301 302 /* XSP (Transmit Spare Bits) 303 304 ------------------- E1 --------------------------- */ 305 306 #define XSP_XAP 0x80 307 #define XSP_CASEN 0x40 308 #define XSP_TT0 0x20 309 #define XSP_EBP 0x10 310 #define XSP_AXS 0x08 311 #define XSP_XSIF 0x04 312 #define XSP_XS13 0x02 313 #define XSP_XS15 0x01 314 315 316 /* XC0/1 (Transmit Control 0/1) 317 ------------------ E1 & T1 ---------------------------- */ 318 319 #define XC0_SA8E 0x80 320 #define XC0_SA7E 0x40 321 #define XC0_SA6E 0x20 322 #define XC0_SA5E 0x10 323 #define XC0_SA4E 0x08 324 #define XC0_BRM 0x80 325 #define XC0_MFBS 0x40 326 #define XC0_SFRZ 0x10 327 #define XC0_XCO2 0x04 328 #define XC0_XCO1 0x02 329 #define XC0_XCO0 0x01 330 331 #define XC1_XTO5 0x20 332 #define XC1_XTO4 0x10 333 #define XC1_XTO3 0x08 334 #define XC1_XTO2 0x04 335 #define XC1_XTO1 0x02 336 #define XC1_XTO0 0x01 337 338 339 /* RC0/1 (Receive Control 0/1) 340 ------------------ E1 & T1 ---------------------------- */ 341 342 #define RC0_SICS 0x40 343 #define RC0_CRCI 0x20 344 #define RC0_XCRCI 0x10 345 #define RC0_RDIS 0x08 346 #define RC0_RCO2 0x04 347 #define RC0_RCO1 0x02 348 #define RC0_RCO0 0x01 349 350 #define RC1_SWD 0x80 351 #define RC1_ASY4 0x40 352 #define RC1_RRAM 0x40 353 #define RC1_RTO5 0x20 354 #define RC1_RTO4 0x10 355 #define RC1_RTO3 0x08 356 #define RC1_RTO2 0x04 357 #define RC1_RTO1 0x02 358 #define RC1_RTO0 0x01 359 360 361 362 /* XPM0-2 (Transmit Pulse Mask 0-2) 363 --------------------- E1 & T1 ------------------------- */ 364 365 #define XPM0_XP12 0x80 366 #define XPM0_XP11 0x40 367 #define XPM0_XP10 0x20 368 #define XPM0_XP04 0x10 369 #define XPM0_XP03 0x08 370 #define XPM0_XP02 0x04 371 #define XPM0_XP01 0x02 372 #define XPM0_XP00 0x01 373 374 #define XPM1_XP30 0x80 375 #define XPM1_XP24 0x40 376 #define XPM1_XP23 0x20 377 #define XPM1_XP22 0x10 378 #define XPM1_XP21 0x08 379 #define XPM1_XP20 0x04 380 #define XPM1_XP14 0x02 381 #define XPM1_XP13 0x01 382 383 #define XPM2_XLHP 0x80 384 #define XPM2_XLT 0x40 385 #define XPM2_DAXLT 0x20 386 #define XPM2_XP34 0x08 387 #define XPM2_XP33 0x04 388 #define XPM2_XP32 0x02 389 #define XPM2_XP31 0x01 390 391 392 /* TSWM (Transparent Service Word Mask) 393 ------------------ E1 ---------------------------- */ 394 395 #define TSWM_TSIS 0x80 396 #define TSWM_TSIF 0x40 397 #define TSWM_TRA 0x20 398 #define TSWM_TSA4 0x10 399 #define TSWM_TSA5 0x08 400 #define TSWM_TSA6 0x04 401 #define TSWM_TSA7 0x02 402 #define TSWM_TSA8 0x01 403 404 /* IDLE <Idle Channel Code Register> 405 406 ------------------ E1 & T1 ----------------------- */ 407 408 #define IDLE_IDL7 0x80 409 #define IDLE_IDL6 0x40 410 #define IDLE_IDL5 0x20 411 #define IDLE_IDL4 0x10 412 #define IDLE_IDL3 0x08 413 #define IDLE_IDL2 0x04 414 #define IDLE_IDL1 0x02 415 #define IDLE_IDL0 0x01 416 417 418 /* XSA4-8 <Transmit SA4-8 Register(Read/Write) > 419 -------------------E1 ----------------------------- */ 420 421 #define XSA4_XS47 0x80 422 #define XSA4_XS46 0x40 423 #define XSA4_XS45 0x20 424 #define XSA4_XS44 0x10 425 #define XSA4_XS43 0x08 426 #define XSA4_XS42 0x04 427 #define XSA4_XS41 0x02 428 #define XSA4_XS40 0x01 429 430 #define XSA5_XS57 0x80 431 #define XSA5_XS56 0x40 432 #define XSA5_XS55 0x20 433 #define XSA5_XS54 0x10 434 #define XSA5_XS53 0x08 435 #define XSA5_XS52 0x04 436 #define XSA5_XS51 0x02 437 #define XSA5_XS50 0x01 438 439 #define XSA6_XS67 0x80 440 #define XSA6_XS66 0x40 441 #define XSA6_XS65 0x20 442 #define XSA6_XS64 0x10 443 #define XSA6_XS63 0x08 444 #define XSA6_XS62 0x04 445 #define XSA6_XS61 0x02 446 #define XSA6_XS60 0x01 447 448 #define XSA7_XS77 0x80 449 #define XSA7_XS76 0x40 450 #define XSA7_XS75 0x20 451 #define XSA7_XS74 0x10 452 #define XSA7_XS73 0x08 453 #define XSA7_XS72 0x04 454 #define XSA7_XS71 0x02 455 #define XSA7_XS70 0x01 456 457 #define XSA8_XS87 0x80 458 #define XSA8_XS86 0x40 459 #define XSA8_XS85 0x20 460 #define XSA8_XS84 0x10 461 #define XSA8_XS83 0x08 462 #define XSA8_XS82 0x04 463 #define XSA8_XS81 0x02 464 #define XSA8_XS80 0x01 465 466 467 /* XDL1-3 (Transmit DL-Bit Register1-3 (read/write)) 468 ----------------------- T1 --------------------- */ 469 470 #define XDL1_XDL17 0x80 471 #define XDL1_XDL16 0x40 472 #define XDL1_XDL15 0x20 473 #define XDL1_XDL14 0x10 474 #define XDL1_XDL13 0x08 475 #define XDL1_XDL12 0x04 476 #define XDL1_XDL11 0x02 477 #define XDL1_XDL10 0x01 478 479 #define XDL2_XDL27 0x80 480 #define XDL2_XDL26 0x40 481 #define XDL2_XDL25 0x20 482 #define XDL2_XDL24 0x10 483 #define XDL2_XDL23 0x08 484 #define XDL2_XDL22 0x04 485 #define XDL2_XDL21 0x02 486 #define XDL2_XDL20 0x01 487 488 #define XDL3_XDL37 0x80 489 #define XDL3_XDL36 0x40 490 #define XDL3_XDL35 0x20 491 #define XDL3_XDL34 0x10 492 #define XDL3_XDL33 0x08 493 #define XDL3_XDL32 0x04 494 #define XDL3_XDL31 0x02 495 #define XDL3_XDL30 0x01 496 497 498 /* ICB1-4 (Idle Channel Register 1-4) 499 ------------------ E1 ---------------------------- */ 500 501 #define E1_ICB1_IC0 0x80 502 #define E1_ICB1_IC1 0x40 503 #define E1_ICB1_IC2 0x20 504 #define E1_ICB1_IC3 0x10 505 #define E1_ICB1_IC4 0x08 506 #define E1_ICB1_IC5 0x04 507 #define E1_ICB1_IC6 0x02 508 #define E1_ICB1_IC7 0x01 509 510 #define E1_ICB2_IC8 0x80 511 #define E1_ICB2_IC9 0x40 512 #define E1_ICB2_IC10 0x20 513 #define E1_ICB2_IC11 0x10 514 #define E1_ICB2_IC12 0x08 515 #define E1_ICB2_IC13 0x04 516 #define E1_ICB2_IC14 0x02 517 #define E1_ICB2_IC15 0x01 518 519 #define E1_ICB3_IC16 0x80 520 #define E1_ICB3_IC17 0x40 521 #define E1_ICB3_IC18 0x20 522 #define E1_ICB3_IC19 0x10 523 #define E1_ICB3_IC20 0x08 524 #define E1_ICB3_IC21 0x04 525 #define E1_ICB3_IC22 0x02 526 #define E1_ICB3_IC23 0x01 527 528 #define E1_ICB4_IC24 0x80 529 #define E1_ICB4_IC25 0x40 530 #define E1_ICB4_IC26 0x20 531 #define E1_ICB4_IC27 0x10 532 #define E1_ICB4_IC28 0x08 533 #define E1_ICB4_IC29 0x04 534 #define E1_ICB4_IC30 0x02 535 #define E1_ICB4_IC31 0x01 536 537 /* ICB1-4 (Idle Channel Register 1-4) 538 ------------------ T1 ---------------------------- */ 539 540 #define T1_ICB1_IC1 0x80 541 #define T1_ICB1_IC2 0x40 542 #define T1_ICB1_IC3 0x20 543 #define T1_ICB1_IC4 0x10 544 #define T1_ICB1_IC5 0x08 545 #define T1_ICB1_IC6 0x04 546 #define T1_ICB1_IC7 0x02 547 #define T1_ICB1_IC8 0x01 548 549 #define T1_ICB2_IC9 0x80 550 #define T1_ICB2_IC10 0x40 551 #define T1_ICB2_IC11 0x20 552 #define T1_ICB2_IC12 0x10 553 #define T1_ICB2_IC13 0x08 554 #define T1_ICB2_IC14 0x04 555 #define T1_ICB2_IC15 0x02 556 #define T1_ICB2_IC16 0x01 557 558 #define T1_ICB3_IC17 0x80 559 #define T1_ICB3_IC18 0x40 560 #define T1_ICB3_IC19 0x20 561 #define T1_ICB3_IC20 0x10 562 #define T1_ICB3_IC21 0x08 563 #define T1_ICB3_IC22 0x04 564 #define T1_ICB3_IC23 0x02 565 #define T1_ICB3_IC24 0x01 566 567 /* FMR3 (Framer Mode Register 3) 568 --------------------E1------------------------ */ 569 570 #define FMR3_CMI 0x08 571 #define FMR3_SYNSA 0x04 572 #define FMR3_CFRZ 0x02 573 #define FMR3_EXTIW 0x01 574 575 576 577 /* CCB1-3 (Clear Channel Register) 578 ------------------- T1 ----------------------- */ 579 580 #define CCB1_CH1 0x80 581 #define CCB1_CH2 0x40 582 #define CCB1_CH3 0x20 583 #define CCB1_CH4 0x10 584 #define CCB1_CH5 0x08 585 #define CCB1_CH6 0x04 586 #define CCB1_CH7 0x02 587 #define CCB1_CH8 0x01 588 589 #define CCB2_CH9 0x80 590 #define CCB2_CH10 0x40 591 #define CCB2_CH11 0x20 592 #define CCB2_CH12 0x10 593 #define CCB2_CH13 0x08 594 #define CCB2_CH14 0x04 595 #define CCB2_CH15 0x02 596 #define CCB2_CH16 0x01 597 598 #define CCB3_CH17 0x80 599 #define CCB3_CH18 0x40 600 #define CCB3_CH19 0x20 601 #define CCB3_CH20 0x10 602 #define CCB3_CH21 0x08 603 #define CCB3_CH22 0x04 604 #define CCB3_CH23 0x02 605 #define CCB3_CH24 0x01 606 607 608 /* LIM0/1 (Line Interface Mode 0/1) 609 ------------------- E1 & T1 --------------------------- */ 610 611 #define LIM0_XFB 0x80 612 #define LIM0_XDOS 0x40 613 #define LIM0_SCL1 0x20 614 #define LIM0_SCL0 0x10 615 #define LIM0_EQON 0x08 616 #define LIM0_ELOS 0x04 617 #define LIM0_LL 0x02 618 #define LIM0_MAS 0x01 619 620 #define LIM1_EFSC 0x80 621 #define LIM1_RIL2 0x40 622 #define LIM1_RIL1 0x20 623 #define LIM1_RIL0 0x10 624 #define LIM1_DCOC 0x08 625 #define LIM1_JATT 0x04 626 #define LIM1_RL 0x02 627 #define LIM1_DRS 0x01 628 629 630 /* PCDR (Pulse Count Detection Register(Read/Write)) 631 ------------------ E1 & T1 ------------------------- */ 632 633 #define PCDR_PCD7 0x80 634 #define PCDR_PCD6 0x40 635 #define PCDR_PCD5 0x20 636 #define PCDR_PCD4 0x10 637 #define PCDR_PCD3 0x08 638 #define PCDR_PCD2 0x04 639 #define PCDR_PCD1 0x02 640 #define PCDR_PCD0 0x01 641 642 #define PCRR_PCR7 0x80 643 #define PCRR_PCR6 0x40 644 #define PCRR_PCR5 0x20 645 #define PCRR_PCR4 0x10 646 #define PCRR_PCR3 0x08 647 #define PCRR_PCR2 0x04 648 #define PCRR_PCR1 0x02 649 #define PCRR_PCR0 0x01 650 651 652 /* LIM2 (Line Interface Mode 2) 653 654 ------------------ E1 & T1 ---------------------------- */ 655 656 #define LIM2_DJA2 0x20 657 #define LIM2_DJA1 0x10 658 #define LIM2_LOS2 0x02 659 #define LIM2_LOS1 0x01 660 661 /* LCR1 (Loop Code Register 1) */ 662 663 #define LCR1_EPRM 0x80 664 #define LCR1_XPRBS 0x40 665 666 /* SIC1 (System Interface Control 1) */ 667 #define SIC1_SRSC 0x80 668 #define SIC1_RBS1 0x20 669 #define SIC1_RBS0 0x10 670 #define SIC1_SXSC 0x08 671 #define SIC1_XBS1 0x02 672 #define SIC1_XBS0 0x01 673 674 /* DEC (Disable Error Counter) 675 ------------------ E1 & T1 ---------------------------- */ 676 677 #define DEC_DCEC3 0x20 678 #define DEC_DBEC 0x10 679 #define DEC_DCEC1 0x08 680 #define DEC_DCEC 0x08 681 #define DEC_DEBC 0x04 682 #define DEC_DCVC 0x02 683 #define DEC_DFEC 0x01 684 685 686 /* FALC Register Bits (Receive Mode) 687 ---------------------------------------------------------------------------- */ 688 689 690 /* FRS0/1 (Framer Receive Status Register 0/1) 691 ----------------- E1 & T1 ---------------------------------- */ 692 693 #define FRS0_LOS 0x80 694 #define FRS0_AIS 0x40 695 #define FRS0_LFA 0x20 696 #define FRS0_RRA 0x10 697 #define FRS0_API 0x08 698 #define FRS0_NMF 0x04 699 #define FRS0_LMFA 0x02 700 #define FRS0_FSRF 0x01 701 702 #define FRS1_TS16RA 0x40 703 #define FRS1_TS16LOS 0x20 704 #define FRS1_TS16AIS 0x10 705 #define FRS1_TS16LFA 0x08 706 #define FRS1_EXZD 0x80 707 #define FRS1_LLBDD 0x10 708 #define FRS1_LLBAD 0x08 709 #define FRS1_XLS 0x02 710 #define FRS1_XLO 0x01 711 #define FRS1_PDEN 0x40 712 713 /* FRS2/3 (Framer Receive Status Register 2/3) 714 ----------------- T1 ---------------------------------- */ 715 716 #define FRS2_ESC2 0x80 717 #define FRS2_ESC1 0x40 718 #define FRS2_ESC0 0x20 719 720 #define FRS3_FEH5 0x20 721 #define FRS3_FEH4 0x10 722 #define FRS3_FEH3 0x08 723 #define FRS3_FEH2 0x04 724 #define FRS3_FEH1 0x02 725 #define FRS3_FEH0 0x01 726 727 728 /* RSW (Receive Service Word Pulseframe) 729 ----------------- E1 ------------------------------ */ 730 731 #define RSW_RSI 0x80 732 #define RSW_RRA 0x20 733 #define RSW_RYO 0x10 734 #define RSW_RY1 0x08 735 #define RSW_RY2 0x04 736 #define RSW_RY3 0x02 737 #define RSW_RY4 0x01 738 739 740 /* RSP (Receive Spare Bits / Additional Status) 741 ---------------- E1 ------------------------------- */ 742 743 #define RSP_SI1 0x80 744 #define RSP_SI2 0x40 745 #define RSP_LLBDD 0x10 746 #define RSP_LLBAD 0x08 747 #define RSP_RSIF 0x04 748 #define RSP_RS13 0x02 749 #define RSP_RS15 0x01 750 751 752 /* FECL (Framing Error Counter) 753 ---------------- E1 & T1 -------------------------- */ 754 755 #define FECL_FE7 0x80 756 #define FECL_FE6 0x40 757 #define FECL_FE5 0x20 758 #define FECL_FE4 0x10 759 #define FECL_FE3 0x08 760 #define FECL_FE2 0x04 761 #define FECL_FE1 0x02 762 #define FECL_FE0 0x01 763 764 #define FECH_FE15 0x80 765 #define FECH_FE14 0x40 766 #define FECH_FE13 0x20 767 #define FECH_FE12 0x10 768 #define FECH_FE11 0x08 769 #define FECH_FE10 0x04 770 #define FECH_FE9 0x02 771 #define FECH_FE8 0x01 772 773 774 /* CVCl (Code Violation Counter) 775 ----------------- E1 ------------------------- */ 776 777 #define CVCL_CV7 0x80 778 #define CVCL_CV6 0x40 779 #define CVCL_CV5 0x20 780 #define CVCL_CV4 0x10 781 #define CVCL_CV3 0x08 782 #define CVCL_CV2 0x04 783 #define CVCL_CV1 0x02 784 #define CVCL_CV0 0x01 785 786 #define CVCH_CV15 0x80 787 #define CVCH_CV14 0x40 788 #define CVCH_CV13 0x20 789 #define CVCH_CV12 0x10 790 #define CVCH_CV11 0x08 791 #define CVCH_CV10 0x04 792 #define CVCH_CV9 0x02 793 #define CVCH_CV8 0x01 794 795 796 /* CEC1-3L (CRC Error Counter) 797 ------------------ E1 ----------------------------- */ 798 799 #define CEC1L_CR7 0x80 800 #define CEC1L_CR6 0x40 801 #define CEC1L_CR5 0x20 802 #define CEC1L_CR4 0x10 803 #define CEC1L_CR3 0x08 804 #define CEC1L_CR2 0x04 805 #define CEC1L_CR1 0x02 806 #define CEC1L_CR0 0x01 807 808 #define CEC1H_CR15 0x80 809 #define CEC1H_CR14 0x40 810 #define CEC1H_CR13 0x20 811 #define CEC1H_CR12 0x10 812 #define CEC1H_CR11 0x08 813 #define CEC1H_CR10 0x04 814 #define CEC1H_CR9 0x02 815 #define CEC1H_CR8 0x01 816 817 #define CEC2L_CR7 0x80 818 #define CEC2L_CR6 0x40 819 #define CEC2L_CR5 0x20 820 #define CEC2L_CR4 0x10 821 #define CEC2L_CR3 0x08 822 #define CEC2L_CR2 0x04 823 #define CEC2L_CR1 0x02 824 #define CEC2L_CR0 0x01 825 826 #define CEC2H_CR15 0x80 827 #define CEC2H_CR14 0x40 828 #define CEC2H_CR13 0x20 829 #define CEC2H_CR12 0x10 830 #define CEC2H_CR11 0x08 831 #define CEC2H_CR10 0x04 832 #define CEC2H_CR9 0x02 833 #define CEC2H_CR8 0x01 834 835 #define CEC3L_CR7 0x80 836 #define CEC3L_CR6 0x40 837 #define CEC3L_CR5 0x20 838 #define CEC3L_CR4 0x10 839 #define CEC3L_CR3 0x08 840 #define CEC3L_CR2 0x04 841 #define CEC3L_CR1 0x02 842 #define CEC3L_CR0 0x01 843 844 #define CEC3H_CR15 0x80 845 #define CEC3H_CR14 0x40 846 #define CEC3H_CR13 0x20 847 #define CEC3H_CR12 0x10 848 #define CEC3H_CR11 0x08 849 #define CEC3H_CR10 0x04 850 #define CEC3H_CR9 0x02 851 #define CEC3H_CR8 0x01 852 853 854 /* CECL (CRC Error Counter) 855 856 ------------------ T1 ----------------------------- */ 857 858 #define CECL_CR7 0x80 859 #define CECL_CR6 0x40 860 #define CECL_CR5 0x20 861 #define CECL_CR4 0x10 862 #define CECL_CR3 0x08 863 #define CECL_CR2 0x04 864 #define CECL_CR1 0x02 865 #define CECL_CR0 0x01 866 867 #define CECH_CR15 0x80 868 #define CECH_CR14 0x40 869 #define CECH_CR13 0x20 870 #define CECH_CR12 0x10 871 #define CECH_CR11 0x08 872 #define CECH_CR10 0x04 873 #define CECH_CR9 0x02 874 #define CECH_CR8 0x01 875 876 /* EBCL (E Bit Error Counter) 877 ------------------- E1 & T1 ------------------------- */ 878 879 #define EBCL_EB7 0x80 880 #define EBCL_EB6 0x40 881 #define EBCL_EB5 0x20 882 #define EBCL_EB4 0x10 883 #define EBCL_EB3 0x08 884 #define EBCL_EB2 0x04 885 #define EBCL_EB1 0x02 886 #define EBCL_EB0 0x01 887 888 #define EBCH_EB15 0x80 889 #define EBCH_EB14 0x40 890 #define EBCH_EB13 0x20 891 #define EBCH_EB12 0x10 892 #define EBCH_EB11 0x08 893 #define EBCH_EB10 0x04 894 #define EBCH_EB9 0x02 895 #define EBCH_EB8 0x01 896 897 898 /* RSA4-8 (Receive Sa4-8-Bit Register) 899 -------------------- E1 --------------------------- */ 900 901 #define RSA4_RS47 0x80 902 #define RSA4_RS46 0x40 903 #define RSA4_RS45 0x20 904 #define RSA4_RS44 0x10 905 #define RSA4_RS43 0x08 906 #define RSA4_RS42 0x04 907 #define RSA4_RS41 0x02 908 #define RSA4_RS40 0x01 909 910 #define RSA5_RS57 0x80 911 #define RSA5_RS56 0x40 912 #define RSA5_RS55 0x20 913 #define RSA5_RS54 0x10 914 #define RSA5_RS53 0x08 915 #define RSA5_RS52 0x04 916 #define RSA5_RS51 0x02 917 #define RSA5_RS50 0x01 918 919 #define RSA6_RS67 0x80 920 #define RSA6_RS66 0x40 921 #define RSA6_RS65 0x20 922 #define RSA6_RS64 0x10 923 #define RSA6_RS63 0x08 924 #define RSA6_RS62 0x04 925 #define RSA6_RS61 0x02 926 #define RSA6_RS60 0x01 927 928 #define RSA7_RS77 0x80 929 #define RSA7_RS76 0x40 930 #define RSA7_RS75 0x20 931 #define RSA7_RS74 0x10 932 #define RSA7_RS73 0x08 933 #define RSA7_RS72 0x04 934 #define RSA7_RS71 0x02 935 #define RSA7_RS70 0x01 936 937 #define RSA8_RS87 0x80 938 #define RSA8_RS86 0x40 939 #define RSA8_RS85 0x20 940 #define RSA8_RS84 0x10 941 #define RSA8_RS83 0x08 942 #define RSA8_RS82 0x04 943 #define RSA8_RS81 0x02 944 #define RSA8_RS80 0x01 945 946 /* RSA6S (Receive Sa6 Bit Status Register) 947 ------------------------ T1 ------------------------- */ 948 949 #define RSA6S_SX 0x20 950 #define RSA6S_SF 0x10 951 #define RSA6S_SE 0x08 952 #define RSA6S_SC 0x04 953 #define RSA6S_SA 0x02 954 #define RSA6S_S8 0x01 955 956 957 /* RDL1-3 Receive DL-Bit Register1-3) 958 ------------------------ T1 ------------------------- */ 959 960 #define RDL1_RDL17 0x80 961 #define RDL1_RDL16 0x40 962 #define RDL1_RDL15 0x20 963 #define RDL1_RDL14 0x10 964 #define RDL1_RDL13 0x08 965 #define RDL1_RDL12 0x04 966 #define RDL1_RDL11 0x02 967 #define RDL1_RDL10 0x01 968 969 #define RDL2_RDL27 0x80 970 #define RDL2_RDL26 0x40 971 #define RDL2_RDL25 0x20 972 #define RDL2_RDL24 0x10 973 #define RDL2_RDL23 0x08 974 #define RDL2_RDL22 0x04 975 #define RDL2_RDL21 0x02 976 #define RDL2_RDL20 0x01 977 978 #define RDL3_RDL37 0x80 979 #define RDL3_RDL36 0x40 980 #define RDL3_RDL35 0x20 981 #define RDL3_RDL34 0x10 982 #define RDL3_RDL33 0x08 983 #define RDL3_RDL32 0x04 984 #define RDL3_RDL31 0x02 985 #define RDL3_RDL30 0x01 986 987 988 /* SIS (Signaling Status Register) 989 990 -------------------- E1 & T1 -------------------------- */ 991 992 #define SIS_XDOV 0x80 993 #define SIS_XFW 0x40 994 #define SIS_XREP 0x20 995 #define SIS_RLI 0x08 996 #define SIS_CEC 0x04 997 #define SIS_BOM 0x01 998 999 1000 /* RSIS (Receive Signaling Status Register) 1001 1002 -------------------- E1 & T1 --------------------------- */ 1003 1004 #define RSIS_VFR 0x80 1005 #define RSIS_RDO 0x40 1006 #define RSIS_CRC16 0x20 1007 #define RSIS_RAB 0x10 1008 #define RSIS_HA1 0x08 1009 #define RSIS_HA0 0x04 1010 #define RSIS_HFR 0x02 1011 #define RSIS_LA 0x01 1012 1013 1014 /* RBCL/H (Receive Byte Count Low/High) 1015 1016 ------------------- E1 & T1 ----------------------- */ 1017 1018 #define RBCL_RBC7 0x80 1019 #define RBCL_RBC6 0x40 1020 #define RBCL_RBC5 0x20 1021 #define RBCL_RBC4 0x10 1022 #define RBCL_RBC3 0x08 1023 #define RBCL_RBC2 0x04 1024 #define RBCL_RBC1 0x02 1025 #define RBCL_RBC0 0x01 1026 1027 #define RBCH_OV 0x10 1028 #define RBCH_RBC11 0x08 1029 #define RBCH_RBC10 0x04 1030 #define RBCH_RBC9 0x02 1031 #define RBCH_RBC8 0x01 1032 1033 1034 /* ISR1-3 (Interrupt Status Register 1-3) 1035 1036 ------------------ E1 & T1 ------------------------------ */ 1037 1038 #define FISR0_RME 0x80 1039 #define FISR0_RFS 0x40 1040 #define FISR0_T8MS 0x20 1041 #define FISR0_ISF 0x20 1042 #define FISR0_RMB 0x10 1043 #define FISR0_CASC 0x08 1044 #define FISR0_RSC 0x08 1045 #define FISR0_CRC6 0x04 1046 #define FISR0_CRC4 0x04 1047 #define FISR0_PDEN 0x02 1048 #define FISR0_RPF 0x01 1049 1050 #define FISR1_CASE 0x80 1051 #define FISR1_LLBSC 0x80 1052 #define FISR1_RDO 0x40 1053 #define FISR1_ALLS 0x20 1054 #define FISR1_XDU 0x10 1055 #define FISR1_XMB 0x08 1056 #define FISR1_XLSC 0x02 1057 #define FISR1_XPR 0x01 1058 1059 #define FISR2_FAR 0x80 1060 #define FISR2_LFA 0x40 1061 #define FISR2_MFAR 0x20 1062 #define FISR2_T400MS 0x10 1063 #define FISR2_LMFA 0x10 1064 #define FISR2_AIS 0x08 1065 #define FISR2_LOS 0x04 1066 #define FISR2_RAR 0x02 1067 #define FISR2_RA 0x01 1068 1069 #define FISR3_ES 0x80 1070 #define FISR3_SEC 0x40 1071 #define FISR3_LMFA16 0x20 1072 #define FISR3_AIS16 0x10 1073 #define FISR3_RA16 0x08 1074 #define FISR3_API 0x04 1075 #define FISR3_XSLP 0x20 1076 #define FISR3_XSLN 0x10 1077 #define FISR3_LLBSC 0x08 1078 #define FISR3_XRS 0x04 1079 #define FISR3_SLN 0x02 1080 #define FISR3_SLP 0x01 1081 1082 1083 /* GIS (Global Interrupt Status Register) 1084 1085 --------------------- E1 & T1 --------------------- */ 1086 1087 #define GIS_ISR3 0x08 1088 #define GIS_ISR2 0x04 1089 #define GIS_ISR1 0x02 1090 #define GIS_ISR0 0x01 1091 1092 1093 /* VSTR (Version Status Register) 1094 1095 --------------------- E1 & T1 --------------------- */ 1096 1097 #define VSTR_VN3 0x08 1098 #define VSTR_VN2 0x04 1099 #define VSTR_VN1 0x02 1100 #define VSTR_VN0 0x01 1101 1102 1103 /*>>>>>>>>>>>>>>>>>>>>> Local Control Structures <<<<<<<<<<<<<<<<<<<<<<<<< */ 1104 1105 /* Write-only Registers (E1/T1 control mode write registers) */ 1106 #define XFIFOH 0x00 /* Tx FIFO High Byte */ 1107 #define XFIFOL 0x01 /* Tx FIFO Low Byte */ 1108 #define CMDR 0x02 /* Command Reg */ 1109 #define DEC 0x60 /* Disable Error Counter */ 1110 #define TEST2 0x62 /* Manuf. Test Reg 2 */ 1111 #define XS(nbr) (0x70 + (nbr)) /* Tx CAS Reg (0 to 15) */ 1112 1113 /* Read-write Registers (E1/T1 status mode read registers) */ 1114 #define MODE 0x03 /* Mode Reg */ 1115 #define RAH1 0x04 /* Receive Address High 1 */ 1116 #define RAH2 0x05 /* Receive Address High 2 */ 1117 #define RAL1 0x06 /* Receive Address Low 1 */ 1118 #define RAL2 0x07 /* Receive Address Low 2 */ 1119 #define IPC 0x08 /* Interrupt Port Configuration */ 1120 #define CCR1 0x09 /* Common Configuration Reg 1 */ 1121 #define CCR3 0x0A /* Common Configuration Reg 3 */ 1122 #define PRE 0x0B /* Preamble Reg */ 1123 #define RTR1 0x0C /* Receive Timeslot Reg 1 */ 1124 #define RTR2 0x0D /* Receive Timeslot Reg 2 */ 1125 #define RTR3 0x0E /* Receive Timeslot Reg 3 */ 1126 #define RTR4 0x0F /* Receive Timeslot Reg 4 */ 1127 #define TTR1 0x10 /* Transmit Timeslot Reg 1 */ 1128 #define TTR2 0x11 /* Transmit Timeslot Reg 2 */ 1129 #define TTR3 0x12 /* Transmit Timeslot Reg 3 */ 1130 #define TTR4 0x13 /* Transmit Timeslot Reg 4 */ 1131 #define IMR0 0x14 /* Interrupt Mask Reg 0 */ 1132 #define IMR1 0x15 /* Interrupt Mask Reg 1 */ 1133 #define IMR2 0x16 /* Interrupt Mask Reg 2 */ 1134 #define IMR3 0x17 /* Interrupt Mask Reg 3 */ 1135 #define IMR4 0x18 /* Interrupt Mask Reg 4 */ 1136 #define IMR5 0x19 /* Interrupt Mask Reg 5 */ 1137 #define FMR0 0x1A /* Framer Mode Reigster 0 */ 1138 #define FMR1 0x1B /* Framer Mode Reigster 1 */ 1139 #define FMR2 0x1C /* Framer Mode Reigster 2 */ 1140 #define LOOP 0x1D /* Channel Loop Back */ 1141 #define XSW 0x1E /* Transmit Service Word */ 1142 #define FMR4 0x1E /* Framer Mode Reg 4 */ 1143 #define XSP 0x1F /* Transmit Spare Bits */ 1144 #define FMR5 0x1F /* Framer Mode Reg 5 */ 1145 #define XC0 0x20 /* Transmit Control 0 */ 1146 #define XC1 0x21 /* Transmit Control 1 */ 1147 #define RC0 0x22 /* Receive Control 0 */ 1148 #define RC1 0x23 /* Receive Control 1 */ 1149 #define XPM0 0x24 /* Transmit Pulse Mask 0 */ 1150 #define XPM1 0x25 /* Transmit Pulse Mask 1 */ 1151 #define XPM2 0x26 /* Transmit Pulse Mask 2 */ 1152 #define TSWM 0x27 /* Transparent Service Word Mask */ 1153 #define TEST1 0x28 /* Manuf. Test Reg 1 */ 1154 #define IDLE 0x29 /* Idle Channel Code */ 1155 #define XSA4 0x2A /* Transmit SA4 Bit Reg */ 1156 #define XDL1 0x2A /* Transmit DL-Bit Reg 2 */ 1157 #define XSA5 0x2B /* Transmit SA4 Bit Reg */ 1158 #define XDL2 0x2B /* Transmit DL-Bit Reg 2 */ 1159 #define XSA6 0x2C /* Transmit SA4 Bit Reg */ 1160 #define XDL3 0x2C /* Transmit DL-Bit Reg 2 */ 1161 #define XSA7 0x2D /* Transmit SA4 Bit Reg */ 1162 #define CCB1 0x2D /* Clear Channel Reg 1 */ 1163 #define XSA8 0x2E /* Transmit SA4 Bit Reg */ 1164 #define CCB2 0x2E /* Clear Channel Reg 2 */ 1165 #define FMR3 0x2F /* Framer Mode Reg. 3 */ 1166 #define CCB3 0x2F /* Clear Channel Reg 3 */ 1167 #define ICB1 0x30 /* Idle Channel Reg 1 */ 1168 #define ICB2 0x31 /* Idle Channel Reg 2 */ 1169 #define ICB3 0x32 /* Idle Channel Reg 3 */ 1170 #define ICB4 0x33 /* Idle Channel Reg 4 */ 1171 #define LIM0 0x34 /* Line Interface Mode 0 */ 1172 #define LIM1 0x35 /* Line Interface Mode 1 */ 1173 #define PCDR 0x36 /* Pulse Count Detection */ 1174 #define PCRR 0x37 /* Pulse Count Recovery */ 1175 #define LIM2 0x38 /* Line Interface Mode Reg 2 */ 1176 #define LCR1 0x39 /* Loop Code Reg 1 */ 1177 #define LCR2 0x3A /* Loop Code Reg 2 */ 1178 #define LCR3 0x3B /* Loop Code Reg 3 */ 1179 #define SIC1 0x3C /* System Interface Control 1 */ 1180 1181 /* Read-only Registers (E1/T1 control mode read registers) */ 1182 #define RFIFOH 0x00 /* Receive FIFO */ 1183 #define RFIFOL 0x01 /* Receive FIFO */ 1184 #define FRS0 0x4C /* Framer Receive Status 0 */ 1185 #define FRS1 0x4D /* Framer Receive Status 1 */ 1186 #define RSW 0x4E /* Receive Service Word */ 1187 #define FRS2 0x4E /* Framer Receive Status 2 */ 1188 #define RSP 0x4F /* Receive Spare Bits */ 1189 #define FRS3 0x4F /* Framer Receive Status 3 */ 1190 #define FECL 0x50 /* Framing Error Counter */ 1191 #define FECH 0x51 /* Framing Error Counter */ 1192 #define CVCL 0x52 /* Code Violation Counter */ 1193 #define CVCH 0x53 /* Code Violation Counter */ 1194 #define CECL 0x54 /* CRC Error Counter 1 */ 1195 #define CECH 0x55 /* CRC Error Counter 1 */ 1196 #define EBCL 0x56 /* E-Bit Error Counter */ 1197 #define EBCH 0x57 /* E-Bit Error Counter */ 1198 #define BECL 0x58 /* Bit Error Counter Low */ 1199 #define BECH 0x59 /* Bit Error Counter Low */ 1200 #define CEC3 0x5A /* CRC Error Counter 3 (16-bit) */ 1201 #define RSA4 0x5C /* Receive SA4 Bit Reg */ 1202 #define RDL1 0x5C /* Receive DL-Bit Reg 1 */ 1203 #define RSA5 0x5D /* Receive SA5 Bit Reg */ 1204 #define RDL2 0x5D /* Receive DL-Bit Reg 2 */ 1205 #define RSA6 0x5E /* Receive SA6 Bit Reg */ 1206 #define RDL3 0x5E /* Receive DL-Bit Reg 3 */ 1207 #define RSA7 0x5F /* Receive SA7 Bit Reg */ 1208 #define RSA8 0x60 /* Receive SA8 Bit Reg */ 1209 #define RSA6S 0x61 /* Receive SA6 Bit Status Reg */ 1210 #define TSR0 0x62 /* Manuf. Test Reg 0 */ 1211 #define TSR1 0x63 /* Manuf. Test Reg 1 */ 1212 #define SIS 0x64 /* Signaling Status Reg */ 1213 #define RSIS 0x65 /* Receive Signaling Status Reg */ 1214 #define RBCL 0x66 /* Receive Byte Control */ 1215 #define RBCH 0x67 /* Receive Byte Control */ 1216 #define FISR0 0x68 /* Interrupt Status Reg 0 */ 1217 #define FISR1 0x69 /* Interrupt Status Reg 1 */ 1218 #define FISR2 0x6A /* Interrupt Status Reg 2 */ 1219 #define FISR3 0x6B /* Interrupt Status Reg 3 */ 1220 #define GIS 0x6E /* Global Interrupt Status */ 1221 #define VSTR 0x6F /* Version Status */ 1222 #define RS(nbr) (0x70 + (nbr)) /* Rx CAS Reg (0 to 15) */ 1223 1224 #endif /* _FALC_LH_H */ 1225 1226