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Searched refs:BUS_AND_STATUS_REG (Results 1 – 8 of 8) sorted by relevance

/linux-2.4.37.9/drivers/scsi/
Dmac_scsi.c465 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pread()
468 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pread()
469 && (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) { in macscsi_pread()
557 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pwrite()
559 || (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH))) in macscsi_pwrite()
561 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)) { in macscsi_pwrite()
DNCR5380.c414 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
1306 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_intr()
1346 while (NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK && time_before(jiffies, timeout)); in NCR5380_intr()
1353 while (NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK); in NCR5380_intr()
2050 tmp = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_transfer_dma()
2092 …if (((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | BASR_ACK)) == (BASR_PHASE_MATCH | BAS… in NCR5380_transfer_dma()
2099 …while (((tmp = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_ACK) || (NCR5380_read(STATUS_REG) & SR_REQ… in NCR5380_transfer_dma()
2174 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)); in NCR5380_transfer_dma()
2194 …while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) && (NCR5380_read(BUS_AND_STATUS_REG) & BASR_… in NCR5380_transfer_dma()
2219 if (NCR5380_read(BUS_AND_STATUS_REG) & BASR_IRQ) { in NCR5380_transfer_dma()
[all …]
Dmac_NCR5380.c587 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
1225 if ((((NCR5380_read(BUS_AND_STATUS_REG)) & in NCR5380_dma_complete()
1236 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()
1290 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_intr()
2031 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)); in NCR5380_transfer_dma()
2055 while (!(NCR5380_read(BUS_AND_STATUS_REG) & in NCR5380_transfer_dma()
2056 BASR_DRQ) && (NCR5380_read(BUS_AND_STATUS_REG) & in NCR5380_transfer_dma()
2061 !(NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK); in NCR5380_transfer_dma()
2109 if (NCR5380_read(BUS_AND_STATUS_REG) & BASR_IRQ) { in NCR5380_transfer_dma()
2822 NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_abort()
Dsun3_scsi.c564 if(count && (NCR5380_read(BUS_AND_STATUS_REG) & in sun3scsi_dma_finish()
567 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG)); in sun3scsi_dma_finish()
Dg_NCR5380.c604 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) in NCR5380_pread()
692 if (!((i = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_END_DMA_TRANSFER)) in NCR5380_pwrite()
698 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) { in NCR5380_pwrite()
Dsun3_NCR5380.c572 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
1208 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()
1219 if((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | in NCR5380_dma_complete()
1222 printk("scsi%d: BASR %02x\n", HOSTNO, NCR5380_read(BUS_AND_STATUS_REG)); in NCR5380_dma_complete()
1269 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_intr()
2712 NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_abort()
DNCR5380.h136 #define BUS_AND_STATUS_REG 5 /* ro */ macro
Datari_NCR5380.c564 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
1221 if ((((NCR5380_read(BUS_AND_STATUS_REG)) & in NCR5380_dma_complete()
1232 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()
1286 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_intr()
2678 NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_abort()