Searched refs:BIT_7 (Results 1 – 7 of 7) sorted by relevance
59 #define CB_CFIG_DMBC_EN BIT_7 /* Enable Tx/Rx min. DMA counts */70 #define CB_CFIG_SAVE_BAD_FRAMES BIT_7 /* Save Bad Frames Enabled */74 #define CB_CFIG_DYNTBD_EN BIT_7 /* Enable dynamic TBD */106 #define CB_CFIG_CRS_OR_CDT BIT_7 /* CRS Or CDT */134 #define CB_CFIG_FDX_ENABLE BIT_7 /* Full Duplex Enabled */
181 #define BIT_7 0x0080 macro255 #define SCB_CUS_MASK (BIT_6 | BIT_7) /* CUS 2-bit Mask */258 #define SCB_CUS_ACTIVE BIT_7 /* CU Active */277 #define SCB_CUC_UNKNOWN BIT_7 /* CU unknown command */279 #define SCB_CUC_STATIC_RESUME (BIT_5 | BIT_7) /* 82558/9 Static Resume */304 #define SCB_CX_INT_MASK BIT_7 /* CU eXecution w/ I-bit done */307 #define SCB_GCR2_EEPROM_ACCESS_SEMAPHORE BIT_7389 #define RFD_FRAME_TOO_SHORT BIT_7 /* Receive Frame Short */717 #define IPCB_LARGESEND_ENABLE BIT_7
86 #define MDI_MDIX_AUTO_SWITCH_ENABLE BIT_7 /* 1 = MDI/MDI-X feature enabled */
56 #define BIT_7 (1L << 7) macro292 #define PCI_EXT_PATCH_3 BIT_7826 #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */869 #define IS_XA1_F BIT_7 /* Q_XA1 End of Frame */892 #define IS_NO_TIST_M1 BIT_7 /* No Time Stamp from MAC 1 */997 #define GP_IO_7 BIT_7 /* IO_7 pin */1197 #define CSR_ENA_POL BIT_7 /* Enable Descr Polling */1246 #define T2_AC_T_ON BIT_7 /* Address Counter Test Mode on */1442 #define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */1475 #define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
1094 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */1100 #define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */
35 #define BIT_7 0x80 macro153 #define QLA1280_BREM BIT_7 /* controller is removed */197 #define HOST_INT BIT_7 /* host interrupt bit */976 #define OF_DATA_OUT BIT_7 /* Data out from initiator */978 #define OF_NO_DATA (BIT_7 | BIT_6)
1673 mb[1] = (uint16_t) (bus ? target | BIT_7 : target); in qla12160_set_target_parameters()2669 if (!(status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_4 | in qla1280_init_rings()2683 status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_5 | in qla1280_init_rings()2923 status |= qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_2 | in qla1280_nvram_config()2970 mb[1] = bus ? ha->bus_settings[bus].id | BIT_7 : in qla1280_nvram_config()2987 mb[1] = (uint16_t) (bus ? target | BIT_7 : target); in qla1280_nvram_config()3053 mb[1] = (uint16_t)(bus ? target | BIT_7 : target); in qla1280_nvram_config()3404 mb[1] = (bus ? (target | BIT_7) : target) << 8; in qla1280_device_reset()3440 mb[1] = (bus ? target | BIT_7 : target) << 8 | lun; in qla1280_abort_device()3480 mb[1] = (bus ? target | BIT_7 : target) << 8 | lun; in qla1280_abort_command()[all …]