Searched refs:BIT_4 (Results 1 – 6 of 6) sorted by relevance
178 #define BIT_4 0x0010 macro265 #define SCB_RUS_READY BIT_4 /* RU Ready */268 #define SCB_RUS_READY_NO_RBDS (BIT_4 | BIT_5) /* RU Ready, No RBDs */275 #define SCB_CUC_START BIT_4 /* CU Start */281 #define SCB_CUC_DUMP_STAT (BIT_4 | BIT_6) /* CU Dump stat. counters */301 #define SCB_RNR_INT_MASK BIT_4 /* RU Not Ready */388 #define RFD_RX_ERR BIT_4 /* RX_ERR pin on Phy was set */400 #define RFD_H_BIT BIT_4 /* Header RFD Bit */462 #define TCPUDP_CHECKSUM_BIT_VALID BIT_4714 #define IPCB_IP_CHECKSUM_ENABLE BIT_4
68 #define CB_CFIG_EXT_TCB_DIS BIT_4 /* Extended TCB */127 #define CB_CFIG_FC_RESTART BIT_4 /* Rx Flow Control Restart */
83 #define MDI_MDIX_CONFIG_IS_OK BIT_4 /* 1 = resolution algorithm completes OK */
59 #define BIT_4 (1L << 4) macro295 #define PCI_EXT_PATCH_0 BIT_4829 #define PC_VCC_DIS BIT_4 /* Switch VCC Disable */873 #define IS_XS2_F BIT_4 /* Q_XS2 End of Frame */895 #define IS_RAM_WR_PAR BIT_4 /* RAM Write Parity Error */1000 #define GP_IO_4 BIT_4 /* IO_4 pin */1011 #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */1200 #define CSR_START BIT_4 /* Start Rx/Tx Queue */1249 #define T2_BC_T_OFF BIT_4 /* Byte Counter Test Mode off */1445 #define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */[all …]
32 #define BIT_4 0x10 macro150 #define QLA1280_QRESET BIT_4968 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
2556 if ((status = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | in qla1280_setup_chip()2574 BIT_4 | BIT_3 | BIT_2 | in qla1280_setup_chip()2669 if (!(status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_4 | in qla1280_init_rings()2938 mb[1] |= BIT_4; in qla1280_nvram_config()2943 mb[2] |= BIT_4; in qla1280_nvram_config()