Searched refs:BIT_2 (Results 1 – 7 of 7) sorted by relevance
51 #define CB_CFIG_READAL_EN BIT_2 /* Enable Read Align */65 #define CB_CFIG_TNO_INT BIT_2 /* Tx Not OK Interrupt */66 #define CB_CFIG_TCO_STAT BIT_2 /* TCO statistics in 559 and above */119 #define CB_CFIG_CRC_IN_MEM BIT_2 /* Transfer CRC To Memory */125 #define CB_CFIG_TX_FC_DIS BIT_2 /* Tx Flow Control Disable */
176 #define BIT_2 0x0004 macro263 #define SCB_RUS_SUSPEND BIT_2 /* RU Suspended */266 #define SCB_RUS_SUSP_NO_RBDS (BIT_2 | BIT_5) /* RU No More RBDs */290 #define SCB_RUC_ABORT BIT_2 /* RU Abort */291 #define SCB_RUC_LOAD_HDS (BIT_0 | BIT_2) /* Load RFD Header Data Size */292 #define SCB_RUC_LOAD_BASE (BIT_1 | BIT_2) /* Load the RU base */299 #define SCB_FCP_INT_MASK BIT_2 /* Flow Control Pause */420 #define CB_SELFTEST_ROM_BIT BIT_2445 #define PHY_82555_LED_DRIVER_CONTROL BIT_2 // the driver is in control446 #define PHY_82555_LED_OFF BIT_2 // activity LED is off[all …]
65 #define MDI_NC3133_100FX_ENABLE BIT_2125 #define EXTENDED_SQUELCH_BIT BIT_2
511 if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_2) in e100_find_speed_duplex()
30 #define BIT_2 0x4 macro124 #define SRB_ABORT_PENDING BIT_2 /* Command abort sent to device */148 #define QLA1280_QSUSP BIT_2166 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */171 #define RISC_INT BIT_2 /* RISC interrupt */178 #define NV_DATA_OUT BIT_2318 #define NV_START_BIT BIT_2568 #define RF_BAD_HEADER BIT_2 /* Bad header. */966 #define SS_CONDITION_MET BIT_2
1669 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla12160_set_target_parameters()2557 BIT_2 | BIT_1 | BIT_0, in qla1280_setup_chip()2574 BIT_4 | BIT_3 | BIT_2 | in qla1280_setup_chip()2670 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()2684 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()2888 WRT_REG_WORD(®->gpio_enable, (BIT_3 + BIT_2 + BIT_1 + BIT_0)); in qla1280_nvram_config()2889 mb[0] = nv->termination.c & (BIT_3 + BIT_2 + BIT_1 + BIT_0); in qla1280_nvram_config()2923 status |= qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_2 | in qla1280_nvram_config()2930 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); in qla1280_nvram_config()2944 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); in qla1280_nvram_config()[all …]
61 #define BIT_2 (1L << 2) macro297 #define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */831 #define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */876 #define IS_XA2_B BIT_2 /* Q_XA2 End of Buffer */897 #define IS_M2_PAR_ERR BIT_2 /* MAC 2 Parity Error */1002 #define GP_IO_2 BIT_2 /* IO_2 pin */1202 #define CSR_IRQ_CL_B BIT_2 /* Clear EOB IRQ */1251 #define T2_STEP03 BIT_2 /* Inc AC/Dec BC by 3 */1447 #define GMF_OPER_OFF BIT_2 /* Operational Mode Off */1480 #define GMC_PAUSE_OFF BIT_2 /* Pause Off */[all …]