1 /*
2 * drivers/net/big_sur_ge.c - Driver for PMC-Sierra Big Sur
3 * ethernet ports
4 *
5 * Copyright (C) 2003, 2004 PMC-Sierra Inc.
6 * Author : Manish Lachwani (lachwani@pmc-sierra.com)
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 *
22 */
23
24 /*
25 * This driver also includes the PHY related stuff. The device
26 * is a fast ethernet device. But, there is a Gigabit unit
27 * in the works. When that is ready, this driver will support
28 * it.
29 *
30 * Basic Operation
31 * ================
32 * The device operates in following modes:
33 * -> Polled mode, no DMA (FIFO)
34 * -> Polled mode, Simple DMA
35 * -> Interrupt mode, Simple DMA
36 * -> Interrupt mode, Scatter Gather DMA
37 *
38 * Scatter Gather DMA does not work. So, we make use of Simple DMA
39 * mode here. There is no implementation of ring descriptors here
40 * since it is not working as yet. Note that there could be an enhancement
41 * whereby the driver can support FIFO mode or Simple DMA. However,
42 * this version only supports Simple DMA.
43 *
44 * Receive Operation
45 * ==================
46 * The device DMA's sends an interrupt to the processor. The driver
47 * is invoked and it determines if the packet is to be received. If
48 * yes, it allocates a new skb and has the DMA controller transfer the
49 * data into the newly allocated skb. The receive side handles one
50 * packet at a time. The Rx FIFO on the device is 2000 bytes.
51 *
52 * Send Operation
53 * ===============
54 * The device Transmit FIFO is 2000 bytes long, i.e. one packet. When
55 * sending, the driver makes sure that the packet is aligned. Once
56 * done, it asks the device to do a DMA transfer from memory to the
57 * onboard FIFO. The device is stopped till the transfer completes since
58 * it can DMA only one packet at a time.
59 *
60 */
61
62 #include <linux/module.h>
63 #include <linux/init.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/skbuff.h>
67 #include <linux/mii.h>
68 #include <linux/interrupt.h>
69 #include <asm/io.h>
70 #include <asm/irq.h>
71
72 #include "big_sur_ge.h"
73
74 MODULE_AUTHOR("Manish Lachwani <lachwani@pmc-sierra.com>");
75 MODULE_DESCRIPTION("PMC-Sierra Big Sur Ethernet MAC Driver");
76 MODULE_LICENSE("GPL");
77
78 #define TX_TIMEOUT (60 * HZ) /* Transmit timeout */
79
80 typedef enum DUPLEX { UNKNOWN, HALF_DUPLEX, FULL_DUPLEX } DUPLEX;
81
82 /* Big Sur Ethernet MAC structure */
83 struct big_sur_ge_enet {
84 struct net_device_stats *stats; /* Statistics for this device */
85 struct timer_list phy_timer; /* PHY monitoring timer */
86 u32 index; /* Which interface is this */
87 u32 save_base_address; /* Saved physical base address */
88 struct sk_buff *saved_skb; /* skb being transmitted */
89 spinlock_t lock; /* For atomic access to saved_skb */
90 u8 mii_addr; /* The MII address of the PHY */
91 big_sur_ge *emac; /* GE driver structure */
92 struct tasklet_struct big_sur_tasklet; /* Tasklet structure */
93 };
94
95 extern unsigned char big_sur_mac_addr_base[6];
96
97 /*
98 * Function Prototypes
99 */
100 unsigned long big_sur_ge_dma_control(xdma_channel *);
101 void big_sur_ge_dma_reset(xdma_channel *);
102 static void handle_intr(struct net_device *, big_sur_ge *);
103 void big_sur_ge_check_fifo_recv_error(struct net_device *, big_sur_ge *);
104 void big_sur_ge_check_fifo_send_error(struct net_device *, big_sur_ge *);
105 static int big_sur_ge_config_fifo(big_sur_ge *);
106 static int big_sur_ge_config_dma(big_sur_ge *);
107 void big_sur_ge_enet_reset(big_sur_ge *);
108 void big_sur_ge_check_mac_error(big_sur_ge *, unsigned long);
109 static void big_sur_receive(struct net_device *);
110 static void big_sur_tx_free_skb(struct net_device *);
111 big_sur_ge_config *big_sur_ge_get_config(int);
112 static void big_sur_ge_reset(struct net_device *,DUPLEX);
113
114 /*
115 * DMA Channel Initialization. In case of Simple DMA,
116 * not much to do here. However, in case of SG DMA, we
117 * need to intialize the descriptor pointers
118 */
big_sur_ge_dma_init(xdma_channel * dma,unsigned long base_address)119 int big_sur_ge_dma_init(xdma_channel *dma, unsigned long base_address)
120 {
121 dma->reg_base_address = base_address;
122 dma->ready = 1;
123
124 big_sur_ge_dma_reset(dma);
125 return 0;
126 }
127
128 /*
129 * Perform the self test on the DMA channel
130 */
131 #define BIG_SUR_GE_CONTROL_REG_RESET_MASK 0x98000000
132
big_sur_ge_dma_self_test(xdma_channel * dma)133 int big_sur_ge_dma_self_test(xdma_channel *dma)
134 {
135 unsigned long reg_data;
136
137 big_sur_ge_dma_reset(dma);
138
139 reg_data = big_sur_ge_dma_control(dma);
140 if (reg_data != BIG_SUR_GE_CONTROL_REG_RESET_MASK) {
141 printk(KERN_ERR "DMA Channel Self Test Failed \n");
142 return -1;
143 }
144
145 return 0;
146 }
147
148 /*
149 * Reset the DMA channel
150 */
big_sur_ge_dma_reset(xdma_channel * dma)151 void big_sur_ge_dma_reset(xdma_channel *dma)
152 {
153 BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_RST_REG_OFFSET,
154 BIG_SUR_GE_RESET_MASK);
155 }
156
157 /*
158 * Get control register from the DMA channel
159 */
big_sur_ge_dma_control(xdma_channel * dma)160 unsigned long big_sur_ge_dma_control(xdma_channel *dma)
161 {
162 return BIG_SUR_GE_READ(dma->reg_base_address + BIG_SUR_GE_DMAC_REG_OFFSET);
163 }
164
165 /*
166 * Set control register of the DMA channel
167 */
big_sur_ge_set_dma_control(xdma_channel * dma,unsigned long control)168 void big_sur_ge_set_dma_control(xdma_channel *dma, unsigned long control)
169 {
170 BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_DMAC_REG_OFFSET, control);
171 }
172
173 /*
174 * Get the status of the DMA channel
175 */
big_sur_ge_dma_status(xdma_channel * dma)176 unsigned long big_sur_ge_dma_status(xdma_channel *dma)
177 {
178 return BIG_SUR_GE_READ(dma->reg_base_address + BIG_SUR_GE_DMAS_REG_OFFSET);
179 }
180
181 /*
182 * Transfer the data over the DMA channel
183 */
big_sur_ge_dma_transfer(xdma_channel * dma,unsigned long * source,unsigned long * dest,unsigned long length)184 void big_sur_ge_dma_transfer(xdma_channel *dma, unsigned long *source,
185 unsigned long *dest, unsigned long length)
186 {
187 /* Source Address */
188 BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_SA_REG_OFFSET,
189 (unsigned long)source);
190
191 /* Destination Address */
192 BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_DA_REG_OFFSET,
193 (unsigned long)dest);
194
195 /* Length of the data */
196 BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_LEN_REG_OFFSET,
197 length);
198 }
199
200 /*
201 * Init the packet fifo only in the FIFO mode
202 */
packet_fifo_init(packet_fifo * fifo,u32 reg,u32 data)203 int packet_fifo_init(packet_fifo *fifo, u32 reg, u32 data)
204 {
205 fifo->reg_base_addr = reg;
206 fifo->data_base_address = data;
207 fifo->ready_status = 1;
208
209 BIG_SUR_GE_FIFO_RESET(fifo);
210
211 return 0;
212 }
213
214 /*
215 * Write to the packet FIFO, 32-bit at a time.
216 */
packet_fifo_write(packet_fifo * fifo,int * buffer,int len)217 static int packet_fifo_write(packet_fifo * fifo, int *buffer, int len)
218 {
219 unsigned long fifo_count, word_count, extra_byte;
220 unsigned long *buffer_data = (unsigned long *) buffer;
221
222 fifo_count =
223 BIG_SUR_GE_READ(fifo->reg_base_addr +
224 BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
225 fifo_count &= BIG_SUR_GE_COUNT_MASK;
226
227 word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
228 extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
229
230 if (extra_byte > 0)
231 if (fifo_count > (word_count + 1)) {
232 printk(KERN_ERR
233 "No room in the packet send fifo \n");
234 return -1;
235 }
236
237 for (fifo_count = 0; fifo_count < word_count; fifo_count++)
238 BIG_SUR_GE_WRITE(fifo->data_base_address,
239 buffer_data[fifo_count]);
240
241 if (extra_byte > 0) {
242 unsigned long last_word = 0;
243 int *extra_buffer_data =
244 (int *) (buffer_data + word_count);
245
246 if (extra_byte == 1)
247 last_word = extra_buffer_data[0] << 24;
248 else if (extra_byte == 2)
249 last_word = (extra_buffer_data[0] << 24 |
250 extra_buffer_data[1] << 16);
251
252 else if (extra_byte == 3)
253 last_word = (extra_buffer_data[0] << 24 |
254 extra_buffer_data[1] << 16 |
255 extra_buffer_data[2] << 8);
256
257
258 BIG_SUR_GE_WRITE(fifo->data_base_address, last_word);
259 }
260
261 return 0;
262 }
263
264 /*
265 * Start transmitting the packet
266 */
big_sur_tx(big_sur_ge * emac,u8 * buffer,unsigned long byte_cnt)267 int big_sur_tx(big_sur_ge *emac, u8 *buffer, unsigned long byte_cnt)
268 {
269 unsigned long int_status, reg_data, status_reg;
270
271 if ( (!emac->started) && (emac->polled) &&
272 (emac->dma_sg) )
273 return -1;
274
275 /* There is space in the FIFO */
276 int_status = BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
277 if (int_status & BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK) {
278 printk(KERN_ERR "Tx FIFO error: Queue is Full \n");
279 return -1;
280 }
281
282 /*
283 * Check if there is enough space for this packet
284 */
285 if ((BIG_SUR_GE_GET_COUNT(&emac->send_fifo) * sizeof(unsigned long)) < byte_cnt) {
286 printk(KERN_ERR "Send FIFO on chip is full \n");
287 return -1;
288 }
289
290 if (emac->has_dma == 0) {
291 /* Write to the Send FIFO */
292 if (packet_fifo_write(&emac->send_fifo, buffer, byte_cnt) == -1) {
293 printk(KERN_ERR "Error : Could not write to FIFO \n");
294 return -1;
295 }
296
297 /* Write the MSB of the length */
298 BIG_SUR_GE_WRITE(emac->base_address + 0x1FF4, (byte_cnt & 0xff00));
299
300 /* Write the LSB of the length */
301 BIG_SUR_GE_WRITE(emac->base_address + 0x1FF8, (byte_cnt & 0x00ff));
302
303 /* Write the Status bit */
304 BIG_SUR_GE_WRITE(emac->base_address + 0x1FFC, 0x80000000);
305
306 /* Make sure MAC has done transmitting */
307 status_reg = BIG_SUR_GE_READ(emac->base_address + 0x1FFC);
308 while (!(status_reg & 0x80000000)) {
309 status_reg = BIG_SUR_GE_READ(emac->base_address + 0x1FFC);
310 if (!(status_reg & 0x80000000))
311 break;
312 }
313
314 }
315 else {
316 /* DMA Engine is not buzy */
317 if (big_sur_ge_dma_status(&emac->send_channel) & BIG_SUR_GE_DMASR_BUSY_MASK) {
318 printk(KERN_ERR "Send channel FIFO engine busy \n");
319 return -1;
320 }
321
322 /* Get ready to transfer the data */
323 big_sur_ge_set_dma_control(&emac->send_channel,
324 BIG_SUR_GE_DMACR_SOURCE_INCR_MASK |
325 BIG_SUR_GE_DMACR_DEST_LOCAL_MASK |
326 BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
327
328 big_sur_ge_dma_transfer(&emac->send_channel, (unsigned long *)buffer,
329 (unsigned long *)(emac->base_address +
330 BIG_SUR_GE_PFIFO_TXDATA_OFFSET), byte_cnt);
331
332 /* Check the DMA Engine status */
333 reg_data = big_sur_ge_dma_status(&emac->send_channel);
334 while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
335 reg_data = big_sur_ge_dma_status(&emac->recv_channel);
336 if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
337 break;
338 }
339
340 /* Check for any DMA errors */
341 if ( (reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
342 (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
343 printk(KERN_ERR "Send side DMA error \n");
344 return -1;
345 }
346
347 /* Write the packet length */
348 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_TPLR_OFFSET, byte_cnt);
349 }
350
351 /* Good Send */
352 return 0;
353 }
354
355 /*
356 * Read the packet FIFO
357 */
packet_fifo_read(packet_fifo * fifo,u8 * buffer,unsigned int len)358 static int packet_fifo_read(packet_fifo * fifo, u8 * buffer, unsigned int len)
359 {
360 unsigned long fifo_count, word_count, extra_byte;
361 unsigned long *buffer_data = (unsigned long *) buffer;
362
363 fifo_count =
364 BIG_SUR_GE_READ(fifo->reg_base_addr +
365 BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
366 fifo_count &= BIG_SUR_GE_COUNT_MASK;
367
368 if ((fifo_count * BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT) < len)
369 return -1;
370
371 word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
372 extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
373
374 for (fifo_count = 0; fifo_count < word_count; fifo_count++)
375 buffer_data[fifo_count] =
376 BIG_SUR_GE_READ(fifo->reg_base_addr);
377
378 if (extra_byte > 0) {
379 unsigned long last_word;
380 int *extra_buffer_data =
381 (int *) (buffer_data + word_count);
382
383 last_word = BIG_SUR_GE_READ(fifo->data_base_address);
384 if (extra_byte == 1)
385 extra_buffer_data[0] = (int) (last_word << 24);
386 else if (extra_byte == 2) {
387 extra_buffer_data[0] = (int) (last_word << 24);
388 extra_buffer_data[1] = (int) (last_word << 16);
389 } else if (extra_byte == 3) {
390 extra_buffer_data[0] = (int) (last_word << 24);
391 extra_buffer_data[1] = (int) (last_word << 16);
392 extra_buffer_data[2] = (int) (last_word << 8);
393 }
394 }
395
396 return 0;
397 }
398
399 /*
400 * FIFO receive for Simple DMA case
401 */
big_sur_rx(big_sur_ge * emac,u8 * buffer,unsigned long * byte_cnt)402 int big_sur_rx(big_sur_ge *emac, u8 *buffer, unsigned long *byte_cnt)
403 {
404 unsigned long int_status, reg_data, packet_length;
405
406 if ( (!emac->started) && (emac->polled) &&
407 (emac->dma_sg) ) {
408 return -1;
409 }
410
411 /* Not enough space in the current buffer */
412 if (*byte_cnt < BIG_SUR_GE_MAX_FRAME_SIZE)
413 return -1;
414
415 int_status = BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
416
417 /* FIFO is empty */
418 if (int_status & BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK) {
419 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IISR_OFFSET,
420 BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK);
421 return -1;
422 }
423
424 packet_length = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET);
425
426 if (emac->has_dma == 0) {
427 reg_data = BIG_SUR_GE_READ(emac->base_address + 0x3FFC);
428 if (reg_data & 0x80000000) {
429 if (packet_fifo_read(&emac->recv_fifo, buffer, packet_length) == -1) {
430 printk(KERN_ERR "Could not read the packet fifo \n");
431 return -1;
432 }
433
434 BIG_SUR_GE_WRITE(emac->base_address + 0x3FFC, 0x0);
435 }
436 }
437 else {
438 /* Rx side DMA engine */
439 if (big_sur_ge_dma_status(&emac->recv_channel) & BIG_SUR_GE_DMASR_BUSY_MASK) {
440 printk(KERN_ERR "Rx side DMA Engine busy \n");
441 return -1;
442 }
443
444 if (packet_length == 0) {
445 printk(KERN_ERR "MAC has the FIFO packet length 0 \n");
446 return -1;
447 }
448
449 /* For the simple DMA case only */
450 big_sur_ge_set_dma_control(&emac->recv_channel,
451 BIG_SUR_GE_DMACR_DEST_INCR_MASK |
452 BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK |
453 BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
454
455 big_sur_ge_dma_transfer(&emac->recv_channel, (unsigned long *)
456 (emac->base_address +
457 BIG_SUR_GE_PFIFO_RXDATA_OFFSET), (unsigned long *)
458 buffer, packet_length);
459
460 reg_data = big_sur_ge_dma_status(&emac->recv_channel);
461 while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
462 reg_data = big_sur_ge_dma_status(&emac->recv_channel);
463 if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
464 break;
465 }
466
467 if ( (reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
468 (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
469 printk(KERN_ERR "DMA Bus Error \n");
470 return -1;
471 }
472 }
473
474 *byte_cnt = packet_length;
475
476 return 0;
477 }
478
479 /*
480 * Main FIFO Interrupt Handler
481 */
big_sur_ge_fifo_intr(unsigned long data)482 void big_sur_ge_fifo_intr(unsigned long data)
483 {
484 struct net_device *netdev = (struct net_device *)data;
485 struct big_sur_ge_enet *lp = (struct big_sur_ge_enet *)netdev->priv;
486 big_sur_ge *emac = (big_sur_ge *)lp->emac;
487
488 /* Read the interrupt status */
489 unsigned long int_status = BIG_SUR_GE_READ(emac->base_address +
490 XIIF_V123B_DIPR_OFFSET);
491
492 /* Handle Rx and Tx */
493 if (int_status & BIG_SUR_GE_IPIF_EMAC_MASK)
494 handle_intr(netdev, emac);
495
496 /* Handle Receive Error */
497 if (int_status & BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
498 big_sur_ge_check_fifo_recv_error(netdev, emac);
499
500 /* Handle Transmit Error */
501 if (int_status & BIG_SUR_GE_IPIF_SEND_FIFO_MASK)
502 big_sur_ge_check_fifo_send_error(netdev, emac);
503
504 /* Clear the errors */
505 if (int_status & XIIF_V123B_ERROR_MASK)
506 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DISR_OFFSET,
507 XIIF_V123B_ERROR_MASK);
508 }
509
510 /*
511 * Tasklet function to invoke interrupt
512 */
big_sur_tasklet_schedule(void * data)513 void big_sur_tasklet_schedule(void *data)
514 {
515 struct net_device *netdev = (struct net_device *)data;
516 struct big_sur_ge_enet *lp = (struct big_sur_ge_enet *)netdev->priv;
517
518 tasklet_schedule(&lp->big_sur_tasklet);
519
520 return;
521 }
522
523 /*
524 * Main intr handler
525 */
handle_intr(struct net_device * netdev,big_sur_ge * emac)526 static void handle_intr(struct net_device *netdev, big_sur_ge *emac)
527 {
528 unsigned long int_status = BIG_SUR_GE_READ(emac->base_address +
529 XIIF_V123B_IISR_OFFSET);
530
531 /* Process the Rx side */
532 if (int_status & BIG_SUR_GE_EIR_RECV_DONE_MASK) {
533 big_sur_receive(netdev);
534 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IISR_OFFSET,
535 BIG_SUR_GE_EIR_RECV_DONE_MASK);
536 }
537
538 /* Process the Tx side */
539 if (int_status & BIG_SUR_GE_EIR_XMIT_DONE_MASK) {
540 big_sur_tx_free_skb(netdev);
541 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IISR_OFFSET,
542 BIG_SUR_GE_EIR_XMIT_DONE_MASK);
543 }
544
545 big_sur_ge_check_mac_error(emac, int_status);
546 }
547 /*
548 * For now, the MAC address errors dont trigger a update of the
549 * stats. There is no stats framework in place. Hence, we just
550 * check for the errors below and do a reset if needed.
551 */
big_sur_ge_check_mac_error(big_sur_ge * emac,unsigned long int_status)552 void big_sur_ge_check_mac_error(big_sur_ge *emac, unsigned long int_status)
553 {
554 if (int_status & (BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |
555 BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK |
556 BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK |
557 BIG_SUR_GE_EIR_RECV_ERROR_MASK |
558 BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK |
559 BIG_SUR_GE_EIR_RECV_COLLISION_MASK |
560 BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK |
561 BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK |
562 BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK |
563 BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK |
564 BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK |
565 BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK |
566 BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK |
567 BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK |
568 BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK) ) {
569
570 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IIER_OFFSET, 0);
571 big_sur_ge_enet_reset(emac);
572 }
573 }
574
575 /*
576 * Check for FIFO Recv errors
577 */
big_sur_ge_check_fifo_recv_error(struct net_device * netdev,big_sur_ge * emac)578 void big_sur_ge_check_fifo_recv_error(struct net_device *netdev, big_sur_ge *emac)
579 {
580 if (BIG_SUR_GE_IS_DEADLOCKED(&emac->recv_fifo)) {
581 unsigned long intr_enable;
582
583 /*
584 * The only way to ack this interrupt is to reset the
585 * device. However, before we reset, we make sure this
586 * interrupt is disabled
587 */
588 intr_enable = BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_DIER_OFFSET);
589 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET,
590 (intr_enable & ~(BIG_SUR_GE_IPIF_RECV_FIFO_MASK)));
591
592 /* Reset the device */
593 big_sur_ge_reset(netdev, UNKNOWN);
594
595 /* Turn the interrupts back on */
596 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET,
597 (intr_enable | BIG_SUR_GE_IPIF_RECV_FIFO_MASK));
598
599 }
600 }
601
602 /*
603 * Check for FIFO Send errors
604 */
big_sur_ge_check_fifo_send_error(struct net_device * netdev,big_sur_ge * emac)605 void big_sur_ge_check_fifo_send_error(struct net_device *netdev, big_sur_ge *emac)
606 {
607 if (BIG_SUR_GE_IS_DEADLOCKED(&emac->send_fifo)) {
608 unsigned long intr_enable;
609
610 /* Disable the interrupt first */
611 intr_enable = BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_DIER_OFFSET);
612 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET,
613 (intr_enable & ~(BIG_SUR_GE_IPIF_SEND_FIFO_MASK)));
614
615 /* Reset the device */
616 big_sur_ge_reset(netdev, UNKNOWN);
617
618 /* Turn the interrupts back on */
619 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET,
620 (intr_enable | BIG_SUR_GE_IPIF_SEND_FIFO_MASK));
621 }
622 }
623
624 /*
625 * GE unit init
626 */
big_sur_ge_enet_init(big_sur_ge * emac,unsigned int device_id)627 int big_sur_ge_enet_init(big_sur_ge *emac, unsigned int device_id)
628 {
629 big_sur_ge_config *config;
630 int err;
631
632 /* Assume that the device has been stopped */
633 config = big_sur_ge_get_config(device_id);
634 if (config == NULL)
635 return -1;
636
637 emac->ready = 0;
638 emac->started = 0;
639 emac->dma_sg = 0;
640 emac->has_mii = config->has_mii;
641 emac->has_mcast_hash_table = 0;
642 emac->dma_config = config->dma_config;
643 emac->base_address = config->base_address;
644
645 if (big_sur_ge_config_dma(emac) == -1)
646 return -1;
647
648 if (emac->has_dma == 0) {
649 err = big_sur_ge_config_fifo(emac);
650 if (err == -1)
651 return err;
652 }
653
654 /* Now, we know that the FIFO initialized successfully. So, set the ready flag */
655 emac->ready = 1;
656
657 /* Do we need a PHY reset here also. It did cause problems on some boards */
658 big_sur_ge_enet_reset(emac);
659
660 /* PHY reset code. Remove if causes a problem on the board */
661 big_sur_ge_reset_phy(emac->base_address);
662
663 return 0;
664 }
665
666 /*
667 * Start the GE unit for Tx, Rx and Interrupts
668 */
big_sur_ge_start(big_sur_ge * emac)669 int big_sur_ge_start(big_sur_ge *emac)
670 {
671 unsigned long reg_data;
672
673 /*
674 * Basic mode of operation is polled and interrupt mode.
675 * We disable the polled mode for good. We may use the
676 * polled mode for Rx NAPI but that does not require all
677 * the interrupts to be disabled
678 */
679 emac->polled = 0;
680
681 /*
682 * DMA: Three modes of operation - simple, FIFO, SG.
683 * SG is surely not working and so is kept off using the
684 * dma_sg flag. Simple and FIFO work. But, we may not use FIFO
685 * at all. So, we enable the interrupts below
686 */
687 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET,
688 BIG_SUR_GE_IPIF_FIFO_DFT_MASK | XIIF_V123B_ERROR_MASK);
689
690 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IIER_OFFSET,
691 BIG_SUR_GE_EIR_DFT_FIFO_MASK);
692
693 /* Toggle the started flag */
694 emac->started = 1;
695
696 /* Start the Tx and Rx units respectively */
697 reg_data = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
698 reg_data &= ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK | BIG_SUR_GE_ECR_RECV_RESET_MASK);
699 reg_data |= (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
700
701 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET, reg_data);
702
703 return 0;
704 }
705
706 /*
707 * Stop the GE unit
708 */
big_sur_ge_stop(big_sur_ge * emac)709 int big_sur_ge_stop(big_sur_ge *emac)
710 {
711 unsigned long reg_data;
712
713 /* We assume that the device is not already stopped */
714 if (!emac->started)
715 return 0;
716
717 /* Disable the Tx and Rx unit respectively */
718 reg_data = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
719 reg_data &= ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
720 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET, reg_data);
721
722 /* Disable the interrupts */
723 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DGIER_OFFSET, 0);
724
725 /* Toggle the started flag */
726 emac->started = 0;
727
728 return 0;
729 }
730
731 /*
732 * Reset the GE MAC unit
733 */
big_sur_ge_enet_reset(big_sur_ge * emac)734 void big_sur_ge_enet_reset(big_sur_ge *emac)
735 {
736 unsigned long reg_data;
737
738 (void) big_sur_ge_stop(emac);
739
740 BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_RESETR_OFFSET,
741 XIIF_V123B_RESET_MASK);
742
743 /*
744 * For now, configure the receiver to not strip off
745 * FCS and padding since this is not currently supported.
746 * In the future, just take the default and provide the option
747 * for the user to change this behavior.
748 */
749 reg_data = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
750 reg_data &= ~(BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK);
751 reg_data &= ~(BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK);
752 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET, reg_data);
753 }
754
755 /*
756 * Set the MAC address of the GE mac unit
757 */
big_sur_ge_set_mac_address(big_sur_ge * emac,unsigned char * addr)758 int big_sur_ge_set_mac_address(big_sur_ge *emac, unsigned char *addr)
759 {
760 unsigned long mac_addr = 0;
761
762 /* Device is started and so mac address must be set */
763 if (emac->started == 1)
764 return 0;
765
766 /* Address High */
767 mac_addr = ( (addr[0] << 8) | addr[1]);
768 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAH_OFFSET, mac_addr);
769
770 /* Address Low */
771 mac_addr |= ( (addr[2] << 24) | (addr[3] << 16) |
772 (addr[4] << 8) | addr[5]);
773 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAL_OFFSET, mac_addr);
774
775 return 0;
776 }
777
778 /*
779 * Get the MAC address of the GE MAC unit
780 */
big_sur_ge_get_mac_unit(big_sur_ge * emac,unsigned int * addr)781 void big_sur_ge_get_mac_unit(big_sur_ge *emac, unsigned int *addr)
782 {
783 unsigned long mac_addr_hi, mac_addr_lo;
784
785 mac_addr_hi = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAH_OFFSET);
786 mac_addr_lo = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAL_OFFSET);
787
788 addr[0] = (mac_addr_hi >> 8);
789 addr[1] = mac_addr_hi;
790
791 addr[2] = (mac_addr_lo >> 24);
792 addr[3] = (mac_addr_lo >> 16);
793 addr[4] = (mac_addr_lo >> 8);
794 addr[5] = mac_addr_lo;
795 }
796
797 /*
798 * Configure the GE MAC for DMA capabilities, only Simple
799 */
big_sur_ge_config_dma(big_sur_ge * emac)800 static int big_sur_ge_config_dma(big_sur_ge *emac)
801 {
802 /* Supports Simple DMA */
803 emac->has_dma = 1;
804
805 if (big_sur_ge_dma_init(&emac->recv_channel, emac->base_address +
806 BIG_SUR_GE_DMA_RECV_OFFSET) == -1) {
807 printk(KERN_ERR "Could not initialize the DMA unit \n");
808 return -1;
809 }
810
811 if (big_sur_ge_dma_init(&emac->send_channel, emac->base_address +
812 BIG_SUR_GE_DMA_SEND_OFFSET) == -1) {
813 printk(KERN_ERR "Could not initialize the DMA unit \n");
814 return -1;
815 }
816
817 return 0;
818 }
819
820 /*
821 * Configure the FIFO for simple DMA
822 */
big_sur_ge_config_fifo(big_sur_ge * emac)823 static int big_sur_ge_config_fifo(big_sur_ge *emac)
824 {
825 int err = 0;
826
827 /* Receive side packet FIFO */
828 err = packet_fifo_init(&emac->recv_fifo, emac->base_address +
829 BIG_SUR_GE_PFIFO_RXREG_OFFSET, emac->base_address +
830 BIG_SUR_GE_PFIFO_RXDATA_OFFSET);
831
832 if (err == -1) {
833 printk(KERN_ERR "Could not initialize Rx packet FIFO for Simple DMA \n");
834 return err;
835 }
836
837 /* Send side Packet FIFO */
838 err = packet_fifo_init(&emac->send_fifo, emac->base_address +
839 BIG_SUR_GE_PFIFO_TXREG_OFFSET, emac->base_address +
840 BIG_SUR_GE_PFIFO_TXDATA_OFFSET);
841
842 if (err == -1) {
843 printk(KERN_ERR "Could not initialize Tx packet FIFO for Simple DMA \n");
844 }
845
846 return err;
847 }
848
849 typedef struct {
850 unsigned long option;
851 unsigned long mask;
852 } option_map;
853
854 static option_map option_table[] = {
855 {BIG_SUR_GE_UNICAST_OPTION, BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK},
856 {BIG_SUR_GE_BROADCAST_OPTION, BIG_SUR_GE_ECR_BROAD_ENABLE_MASK},
857 {BIG_SUR_GE_PROMISC_OPTION, BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK},
858 {BIG_SUR_GE_FDUPLEX_OPTION, BIG_SUR_GE_ECR_FULL_DUPLEX_MASK},
859 {BIG_SUR_GE_LOOPBACK_OPTION, BIG_SUR_GE_ECR_LOOPBACK_MASK},
860 {BIG_SUR_GE_MULTICAST_OPTION, BIG_SUR_GE_ECR_MULTI_ENABLE_MASK},
861 {BIG_SUR_GE_FLOW_CONTROL_OPTION, BIG_SUR_GE_ECR_PAUSE_FRAME_MASK},
862 {BIG_SUR_GE_INSERT_PAD_OPTION, BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK},
863 {BIG_SUR_GE_INSERT_FCS_OPTION, BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK},
864 {BIG_SUR_GE_INSERT_ADDR_OPTION, BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK},
865 {BIG_SUR_GE_OVWRT_ADDR_OPTION, BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK},
866 {BIG_SUR_GE_STRIP_PAD_OPTION, BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK},
867 {BIG_SUR_GE_STRIP_FCS_OPTION, BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK},
868 {BIG_SUR_GE_STRIP_PAD_FCS_OPTION, BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK}
869 };
870
871 #define BIG_SUR_GE_NUM_OPTIONS (sizeof(option_table) / sizeof(option_map))
872
873 /*
874 * Set the options for the GE
875 */
big_sur_ge_set_options(big_sur_ge * emac,unsigned long option_flag)876 int big_sur_ge_set_options(big_sur_ge *emac, unsigned long option_flag)
877 {
878 unsigned long reg_data;
879 unsigned int index;
880
881 /* Assume that the device is stopped before calling this function */
882
883 reg_data = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
884 for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
885 if (option_flag & option_table[index].option)
886 reg_data |= option_table[index].mask;
887 else
888 reg_data &= ~(option_table[index].mask);
889
890 }
891
892 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET, reg_data);
893
894 /* No polled option */
895 emac->polled = 0;
896 return 0;
897 }
898
899 /*
900 * Get the options from the GE
901 */
big_sur_ge_get_options(big_sur_ge * emac)902 unsigned long big_sur_ge_get_options(big_sur_ge *emac)
903 {
904 unsigned long option_flag = 0, reg_data;
905 unsigned int index;
906
907 reg_data = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
908
909 for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
910 if (option_flag & option_table[index].option)
911 reg_data |= option_table[index].mask;
912 }
913
914 return option_flag;
915 }
916
917 /*
918 * Set the Inter frame gap
919 */
big_sur_ge_set_frame_gap(big_sur_ge * emac,int part1,int part2)920 int big_sur_ge_set_frame_gap(big_sur_ge *emac, int part1, int part2)
921 {
922 unsigned long config;
923
924 /* Assume that the device is stopped before calling this */
925
926 config = ( (part1 << BIG_SUR_GE_IFGP_PART1_SHIFT) |
927 (part2 << BIG_SUR_GE_IFGP_PART2_SHIFT) );
928
929 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_IFGP_OFFSET, config);
930
931 return 0;
932 }
933
934 /*
935 * Get the Inter frame gap
936 */
big_sur_ge_get_frame_gap(big_sur_ge * emac,int * part1,int * part2)937 void big_sur_ge_get_frame_gap(big_sur_ge *emac, int *part1, int *part2)
938 {
939 unsigned long config;
940
941 config = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_IFGP_OFFSET);
942 *part1 = ((config & BIG_SUR_GE_IFGP_PART1_SHIFT) >> BIG_SUR_GE_IFGP_PART1_SHIFT);
943 *part2 = ((config & BIG_SUR_GE_IFGP_PART2_SHIFT) >> BIG_SUR_GE_IFGP_PART2_SHIFT);
944 }
945
946 /*
947 * PHY specific functions for the MAC
948 */
949 #define BIG_SUR_GE_MAX_PHY_ADDR 32
950 #define BIG_SUR_GE_MAX_PHY_REG 32
951
952 /*
953 * Read the PHY reg
954 */
big_sur_ge_phy_read(big_sur_ge * emac,unsigned long addr,unsigned long reg_num,unsigned int * data)955 int big_sur_ge_phy_read(big_sur_ge *emac, unsigned long addr,
956 unsigned long reg_num, unsigned int *data)
957 {
958 unsigned long mii_control, mii_data;
959
960 if (!emac->has_mii)
961 return -1;
962
963 mii_control = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
964 if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
965 printk(KERN_ERR "PHY busy \n");
966 return -1;
967 }
968
969 mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
970 mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
971 mii_control |= (BIG_SUR_GE_MGTCR_RW_NOT_MASK | BIG_SUR_GE_MGTCR_START_MASK |
972 BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
973
974 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET, mii_control);
975
976 while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
977 if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
978 break;
979
980 mii_data = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET);
981 *data = (unsigned int) mii_data;
982
983 return 0;
984 }
985
986 /*
987 * Write to the PHY register
988 */
big_sur_ge_phy_write(big_sur_ge * emac,unsigned long addr,unsigned long reg_num,unsigned int data)989 int big_sur_ge_phy_write(big_sur_ge *emac, unsigned long addr,
990 unsigned long reg_num, unsigned int data)
991 {
992 unsigned long mii_control;
993
994 if (!emac->has_mii)
995 return -1;
996
997 mii_control = BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
998 if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
999 printk(KERN_ERR "PHY busy \n");
1000 return -1;
1001 }
1002
1003 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET, (unsigned long)data);
1004
1005 mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
1006 mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
1007 mii_control |= (BIG_SUR_GE_MGTCR_START_MASK | BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
1008
1009 BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET, mii_control);
1010
1011 while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
1012 if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
1013 break;
1014
1015 return 0;
1016 }
1017
1018 /*
1019 * Reset the GE system
1020 */
big_sur_ge_reset(struct net_device * netdev,DUPLEX duplex)1021 static void big_sur_ge_reset(struct net_device *netdev, DUPLEX duplex)
1022 {
1023 struct big_sur_ge_enet *lp = (struct big_sur_ge_enet *)netdev->priv;
1024 struct sk_buff *skb;
1025 unsigned long options;
1026 int ifcfg1, ifcfg2;
1027
1028 /* Stop the queue */
1029 netif_stop_queue(netdev);
1030
1031 big_sur_ge_get_frame_gap(lp->emac, &ifcfg1, &ifcfg2);
1032 options = big_sur_ge_get_options(lp->emac);
1033 switch (duplex) {
1034 case HALF_DUPLEX:
1035 options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
1036 break;
1037
1038 case FULL_DUPLEX:
1039 options |= BIG_SUR_GE_FDUPLEX_OPTION;
1040 break;
1041
1042 case UNKNOWN:
1043 break;
1044 }
1045
1046 big_sur_ge_enet_reset(lp->emac);
1047
1048 /* Set the necessary options for the MAC unit */
1049 big_sur_ge_set_mac_address(lp->emac, netdev->dev_addr);
1050 big_sur_ge_set_frame_gap(lp->emac, ifcfg1, ifcfg2);
1051 big_sur_ge_set_options(lp->emac, options);
1052
1053 (void) big_sur_ge_start(lp->emac);
1054
1055 spin_lock_irq(lp->lock);
1056 skb = lp->saved_skb;
1057 lp->saved_skb = NULL;
1058 spin_unlock_irq(lp->lock);
1059
1060 if (skb)
1061 dev_kfree_skb(skb);
1062
1063 /* Start the queue, in case it was stopped */
1064 netif_wake_queue(netdev);
1065 }
1066
1067 /*
1068 * Get the PHY status and then configure the
1069 * speed, duplex, link status etc.
1070 */
big_sur_ge_get_phy_status(struct net_device * netdev,DUPLEX * duplex,int * linkup)1071 static int big_sur_ge_get_phy_status(struct net_device *netdev,
1072 DUPLEX *duplex, int *linkup)
1073 {
1074 struct big_sur_ge_enet *lp = netdev->priv;
1075 unsigned int reg_data;
1076 int err = 0;
1077
1078 err = big_sur_ge_phy_read(lp->emac, lp->mii_addr, MII_BMCR, ®_data);
1079 if (err == -1) {
1080 printk(KERN_ERR "%s: Could not read PHY control register", netdev->name);
1081 return err;
1082 }
1083
1084 if (!(reg_data & BMCR_ANENABLE)) {
1085 if (reg_data & BMCR_FULLDPLX)
1086 *duplex = FULL_DUPLEX;
1087 else
1088 *duplex = HALF_DUPLEX;
1089 }
1090 else {
1091 unsigned int advertise, partner, neg;
1092
1093 err = big_sur_ge_phy_read(lp->emac, lp->mii_addr, MII_ADVERTISE, &advertise);
1094 if (err == -1) {
1095 printk(KERN_ERR "%s: Could not read PHY control register", netdev->name);
1096 return err;
1097 }
1098
1099 err = big_sur_ge_phy_read(lp->emac, lp->mii_addr, MII_LPA, &partner);
1100 if (err == -1) {
1101 printk(KERN_ERR "%s: Could not read PHY control register", netdev->name);
1102 return err;
1103 }
1104
1105 neg = advertise & partner & ADVERTISE_ALL;
1106 if (neg & ADVERTISE_100FULL)
1107 *duplex = FULL_DUPLEX;
1108 else if (neg & ADVERTISE_100HALF)
1109 *duplex = HALF_DUPLEX;
1110 else if (neg & ADVERTISE_10FULL)
1111 *duplex = FULL_DUPLEX;
1112 else
1113 *duplex = HALF_DUPLEX;
1114
1115 err = big_sur_ge_phy_read(lp->emac, lp->mii_addr, MII_BMSR, ®_data);
1116 if (err == -1) {
1117 printk(KERN_ERR "%s: Could not read PHY control register", netdev->name);
1118 return err;
1119 }
1120
1121 *linkup = (reg_data & BMSR_LSTATUS) != 0;
1122
1123 }
1124 return 0;
1125 }
1126
1127 /*
1128 * Poll the MII for duplex and link status
1129 */
big_sur_ge_poll_mii(unsigned long data)1130 static void big_sur_ge_poll_mii(unsigned long data)
1131 {
1132 struct net_device *netdev = (struct net_device *) data;
1133 struct big_sur_ge_enet* lp = netdev->priv;
1134 unsigned long options;
1135 DUPLEX mac_duplex, phy_duplex;
1136 int phy_carrier, netif_carrier;
1137
1138 if (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier) == -1) {
1139 printk(KERN_ERR "%s: Terminating link monitoring.\n", netdev->name);
1140 return;
1141 }
1142
1143 options = big_sur_ge_get_options(lp->emac);
1144 if (options & BIG_SUR_GE_FDUPLEX_OPTION)
1145 mac_duplex = FULL_DUPLEX;
1146 else
1147 mac_duplex = HALF_DUPLEX;
1148
1149 if (mac_duplex != phy_duplex) {
1150 tasklet_disable(&lp->big_sur_tasklet);
1151 big_sur_ge_reset(netdev, phy_duplex);
1152 tasklet_enable(&lp->big_sur_tasklet);
1153 }
1154
1155 netif_carrier = netif_carrier_ok(netdev) != 0;
1156
1157 if (phy_carrier != netif_carrier) {
1158 if (phy_carrier) {
1159 printk(KERN_INFO "%s: Link carrier restored.\n",
1160 netdev->name);
1161 netif_carrier_on(netdev);
1162 } else {
1163 printk(KERN_INFO "%s: Link carrier lost.\n", netdev->name);
1164 netif_carrier_off(netdev);
1165 }
1166 }
1167
1168 /* Set up the timer so we'll get called again in 2 seconds. */
1169 lp->phy_timer.expires = jiffies + 2 * HZ;
1170 add_timer(&lp->phy_timer);
1171 }
1172
1173 /*
1174 * Open the network interface
1175 */
big_sur_ge_open(struct net_device * netdev)1176 static int big_sur_ge_open(struct net_device *netdev)
1177 {
1178 struct big_sur_ge_enet *lp = netdev->priv;
1179 unsigned long options;
1180 DUPLEX phy_duplex, mac_duplex;
1181 int phy_carrier;
1182
1183 (void) big_sur_ge_stop(lp->emac);
1184
1185 if (big_sur_ge_set_mac_address(lp->emac, netdev->dev_addr) == -1) {
1186 printk(KERN_ERR "%s: Could not set MAC address.\n", netdev->name);
1187 return -EIO;
1188 }
1189
1190 options = big_sur_ge_get_options(lp->emac);
1191
1192 /*
1193 * This MAC unit has no support for Interrupts. So, we initialize
1194 * a tasklet here that will be scheduled from the timer
1195 * interrupt handler. Note that we cannot run the receive
1196 * and the transmit functions as part of an interrupt handler. Since,
1197 * this will be disastrous for the timer under load. Hence, tasklet
1198 * is the best way to go
1199 */
1200 tasklet_init(&lp->big_sur_tasklet, big_sur_ge_fifo_intr, (unsigned long)netdev);
1201
1202 if (!(big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier))) {
1203 if (options & BIG_SUR_GE_FDUPLEX_OPTION)
1204 mac_duplex = FULL_DUPLEX;
1205 else
1206 mac_duplex = HALF_DUPLEX;
1207
1208 if (mac_duplex != phy_duplex) {
1209 switch (phy_duplex) {
1210 case HALF_DUPLEX:
1211 options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
1212 break;
1213 case FULL_DUPLEX:
1214 options |= BIG_SUR_GE_FDUPLEX_OPTION;
1215 break;
1216 case UNKNOWN:
1217 break;
1218 }
1219
1220 big_sur_ge_set_options(lp->emac, options);
1221 }
1222 }
1223
1224 if (big_sur_ge_start(lp->emac) == -1) {
1225 printk(KERN_ERR "%s: Could not start device.\n", netdev->name);
1226 tasklet_kill(&lp->big_sur_tasklet);
1227 return -EBUSY;
1228 }
1229
1230 MOD_INC_USE_COUNT;
1231 netif_start_queue(netdev);
1232
1233 lp->phy_timer.expires = jiffies + 2*HZ;
1234 lp->phy_timer.data = (unsigned long)netdev;
1235 lp->phy_timer.function = &big_sur_ge_poll_mii;
1236 add_timer(&lp->phy_timer);
1237
1238 return 0;
1239 }
1240
1241 /*
1242 * Close the network device interface
1243 */
big_sur_ge_close(struct net_device * netdev)1244 static int big_sur_ge_close(struct net_device *netdev)
1245 {
1246 struct big_sur_ge_enet *lp = netdev->priv;
1247
1248 del_timer_sync(&lp->phy_timer);
1249 netif_stop_queue(netdev);
1250
1251 if (big_sur_ge_stop(lp->emac) == -1) {
1252 printk(KERN_ERR "%s: Could not stop device.\n", netdev->name);
1253 return -EBUSY;
1254 }
1255
1256 tasklet_kill(&lp->big_sur_tasklet);
1257
1258 MOD_DEC_USE_COUNT;
1259 return 0;
1260 }
1261
1262 /*
1263 * Get the network device stats.
1264 */
big_sur_ge_get_stats(struct net_device * netdev)1265 static struct net_device_stats *big_sur_ge_get_stats(struct net_device *netdev)
1266 {
1267 struct big_sur_ge_enet *lp = netdev->priv;
1268
1269 return lp->stats;
1270 }
1271
1272 /*
1273 * FIFO send for a packet that needs to be transmitted
1274 */
big_sur_start_xmit(struct sk_buff * orig_skb,struct net_device * netdev)1275 static int big_sur_start_xmit(struct sk_buff *orig_skb, struct net_device *netdev)
1276 {
1277 struct big_sur_ge_enet *lp = netdev->priv;
1278 struct sk_buff *new_skb;
1279 unsigned int len, align;
1280 struct net_device_stats *stats = lp->stats;
1281
1282 /*
1283 * The FIFO takes a single request at a time. Stop the queue to
1284 * accomplish this. We'll wake the queue in the transmit
1285 * routine below or in the timeout routine
1286 */
1287 netif_stop_queue(netdev);
1288 len = orig_skb->len;
1289
1290 /*
1291 * Align the packet for the FIFO
1292 */
1293 if (!(new_skb = dev_alloc_skb(len + 4))) {
1294 dev_kfree_skb(orig_skb);
1295 printk(KERN_ERR "%s: Could not allocate transmit buffer.\n",
1296 netdev->name);
1297 netif_wake_queue(netdev);
1298 return -EBUSY;
1299 }
1300
1301 align = 4 - ((unsigned long) new_skb->data & 3);
1302 if (align != 4)
1303 skb_reserve(new_skb, align);
1304
1305 skb_put(new_skb, len);
1306 memcpy(new_skb->data, orig_skb->data, len);
1307
1308 dev_kfree_skb(orig_skb);
1309 lp->saved_skb = new_skb;
1310
1311 /* Do the actual transmit */
1312 if (big_sur_tx(lp->emac, (u8 *) new_skb->data, len) == -1) {
1313 spin_lock_irq(&lp->lock);
1314 new_skb = lp->saved_skb;
1315 lp->saved_skb = NULL;
1316 spin_unlock_irq(&lp->lock);
1317
1318 dev_kfree_skb(new_skb);
1319 printk(KERN_ERR "%s: Could not transmit buffer.\n", netdev->name);
1320 netif_wake_queue(netdev);
1321 return -EIO;
1322 }
1323
1324 stats->tx_bytes += len;
1325 stats->tx_packets++;
1326
1327 return 0;
1328 }
1329
1330 /*
1331 * Free the skb
1332 */
big_sur_tx_free_skb(struct net_device * netdev)1333 static void big_sur_tx_free_skb(struct net_device *netdev)
1334 {
1335 struct big_sur_ge_enet *lp = netdev->priv;
1336 struct sk_buff *skb;
1337
1338 spin_lock_irq(&lp->lock);
1339 skb = lp->saved_skb;
1340 lp->saved_skb = NULL;
1341 spin_unlock_irq(&lp->lock);
1342
1343 if (skb)
1344 dev_kfree_skb(skb);
1345
1346 /* Start the queue since we know that packet has been transmitted */
1347 netif_wake_queue(netdev);
1348 }
1349
1350 /*
1351 * Handle the timeout of the ethernet device
1352 */
big_sur_ge_tx_timeout(struct net_device * netdev)1353 static void big_sur_ge_tx_timeout(struct net_device *netdev)
1354 {
1355 struct big_sur_ge_enet *lp = (struct big_sur_ge_enet *)netdev;
1356
1357 printk("%s: Exceeded transmit timeout of %lu ms. Resetting mac.\n",
1358 netdev->name, TX_TIMEOUT * 1000UL / HZ);
1359
1360 tasklet_disable(&lp->big_sur_tasklet);
1361 big_sur_ge_reset(netdev, UNKNOWN);
1362 tasklet_enable(&lp->big_sur_tasklet);
1363 }
1364
1365 /*
1366 * Receive the packets
1367 */
big_sur_receive(struct net_device * netdev)1368 static void big_sur_receive(struct net_device *netdev)
1369 {
1370 struct big_sur_ge_enet *lp = (struct big_sur_ge_enet *)netdev->priv;
1371 struct sk_buff *skb;
1372 unsigned long len = BIG_SUR_GE_MAX_FRAME_SIZE;
1373 unsigned int align;
1374 struct net_device_stats *stats = lp->stats;
1375
1376 if (!(skb = dev_alloc_skb(len + 4))) {
1377 printk(KERN_ERR "%s: Could not allocate receive buffer.\n",
1378 netdev->name);
1379 return;
1380 }
1381
1382 align = 4 - ((unsigned long) skb->data & 3);
1383 if (align != 4)
1384 skb_reserve(skb, align);
1385
1386 if (big_sur_rx(lp->emac, (u8 *)skb->data, &len) == -1) {
1387 dev_kfree_skb(skb);
1388
1389 printk(KERN_ERR "%s: Could not receive buffer \n", netdev->name);
1390 netdev->tx_timeout = NULL;
1391 big_sur_ge_reset(netdev, UNKNOWN);
1392 netdev->tx_timeout = big_sur_ge_tx_timeout;
1393 }
1394
1395 skb_put(skb, len);
1396 skb->dev = netdev;
1397 skb->protocol = eth_type_trans(skb, netdev);
1398
1399 stats->rx_packets++;
1400 stats->rx_bytes += len;
1401
1402 /* Good Rx, send the packet upstream. */
1403 netif_rx(skb);
1404 }
1405
1406 /*
1407 * Set the Multicast Hash list
1408 */
big_sur_ge_set_multi(struct net_device * netdev)1409 static void big_sur_ge_set_multi(struct net_device *netdev)
1410 {
1411 struct big_sur_ge_enet *lp = (struct big_sur_ge_enet *)netdev->priv;
1412 unsigned long options;
1413
1414 tasklet_disable(&lp->big_sur_tasklet);
1415
1416 (void) big_sur_ge_stop(lp->emac);
1417 options = big_sur_ge_get_options(lp->emac);
1418 options &= ~(BIG_SUR_GE_PROMISC_OPTION | BIG_SUR_GE_MULTICAST_OPTION);
1419
1420 if (netdev->flags & IFF_PROMISC)
1421 options |= BIG_SUR_GE_PROMISC_OPTION;
1422
1423 (void) big_sur_ge_start(lp->emac);
1424
1425 tasklet_enable(&lp->big_sur_tasklet);
1426 }
1427
1428 /*
1429 * IOCTL support
1430 */
big_sur_ge_ioctl(struct net_device * netdev,struct ifreq * rq,int cmd)1431 static int big_sur_ge_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
1432 {
1433 struct big_sur_ge_enet *lp = netdev->priv;
1434 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &rq->ifr_data;
1435
1436 switch(cmd) {
1437 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1438 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
1439 data->phy_id = lp->mii_addr;
1440
1441 case SIOCGMIIREG: /* Read MII PHY register. */
1442 case SIOCDEVPRIVATE + 1: /* for binary compat, remove in 2.5 */
1443 if (data->phy_id > 31 || data->reg_num > 31)
1444 return -ENXIO;
1445
1446 del_timer_sync(&lp->phy_timer);
1447
1448 if (big_sur_ge_phy_read(lp->emac, data->phy_id,
1449 data->reg_num, &data->val_out) == -1) {
1450 printk(KERN_ERR "%s: Could not read from PHY", netdev->name);
1451 return -EBUSY;
1452 }
1453
1454 lp->phy_timer.expires = jiffies + 2*HZ;
1455 add_timer(&lp->phy_timer);
1456
1457 return 0;
1458
1459 case SIOCSMIIREG: /* Write MII PHY register. */
1460 case SIOCDEVPRIVATE + 2: /* for binary compat, remove in 2.5 */
1461 if (data->phy_id > 31 || data->reg_num > 31)
1462 return -ENXIO;
1463
1464 del_timer_sync(&lp->phy_timer);
1465
1466 if (big_sur_ge_phy_write(lp->emac, data->phy_id, data->reg_num,
1467 data->val_in) == -1) {
1468 printk(KERN_ERR "%s: Could not write to PHY", netdev->name);
1469 return -EBUSY;
1470 }
1471
1472 lp->phy_timer.expires = jiffies + 2*HZ;
1473 add_timer(&lp->phy_timer);
1474
1475 return 0;
1476
1477 default:
1478 return -EOPNOTSUPP;
1479 }
1480 }
1481
1482 /*
1483 * Get the config from the config table
1484 */
big_sur_ge_get_config(int index)1485 big_sur_ge_config *big_sur_ge_get_config(int index)
1486 {
1487 /* For port 0 only */
1488 big_sur_ge_config *config;
1489
1490 config->device_id = 0;
1491 config->base_address = BIG_SUR_GE_BASE; /* Base Address of the MAC */
1492 config->has_counters = 0;
1493 config->has_sg_dma = 0;
1494 config->dma_config = 0;
1495 config->has_mii = 1;
1496
1497 return (big_sur_ge_config *)config;
1498 }
1499
1500 /*
1501 * Release the network device structure
1502 */
big_sur_ge_remove_dev(struct net_device * netdev)1503 static void big_sur_ge_remove_dev(struct net_device *netdev)
1504 {
1505 struct big_sur_ge_enet *lp = (struct big_sur_ge_enet *)netdev;
1506 big_sur_ge_config *config;
1507
1508 config = big_sur_ge_get_config(lp->index);
1509 config->base_address = lp->save_base_address;
1510
1511 if (lp->saved_skb)
1512 dev_kfree_skb(lp->saved_skb);
1513 kfree(lp);
1514
1515 unregister_netdev(netdev);
1516 kfree(netdev);
1517 }
1518
1519 /*
1520 * Initial Function to probe the network interface
1521 */
big_sur_ge_probe(int index)1522 static int __init big_sur_ge_probe(int index)
1523 {
1524 struct net_device *netdev;
1525 struct big_sur_ge_enet *lp;
1526 big_sur_ge_config *config;
1527 unsigned long maddr;
1528
1529 config = big_sur_ge_get_config(index);
1530 if (!config)
1531 return -ENODEV;
1532
1533 netdev = alloc_etherdev(sizeof(struct big_sur_ge_enet));
1534
1535 if (!netdev) {
1536 printk(KERN_ERR "Could not allocate Big Sur Ethernet device %d.\n",index);
1537 return -ENOMEM;
1538 }
1539
1540 SET_MODULE_OWNER(netdev);
1541
1542 lp = (struct big_sur_ge_enet *)netdev->priv;
1543 memset(lp, 0, sizeof(struct big_sur_ge_enet));
1544 spin_lock_init(&lp->lock);
1545
1546 /* Use KSEG1 address */
1547 lp->save_base_address = config->base_address;
1548
1549 if (big_sur_ge_enet_init(lp->emac, config->device_id) == -1) {
1550 printk(KERN_ERR "%s: Could not initialize device.\n", netdev->name);
1551 big_sur_ge_remove_dev(netdev);
1552 return -ENODEV;
1553 }
1554
1555 memcpy(netdev->dev_addr, big_sur_mac_addr_base, 6);
1556 if (big_sur_ge_set_mac_address(lp->emac, netdev->dev_addr) == -1) {
1557 printk(KERN_ERR "%s: Could not set MAC address.\n", netdev->name);
1558 big_sur_ge_remove_dev(netdev);
1559 return -EIO;
1560 }
1561
1562 /* Check the PHY */
1563 lp->mii_addr = 0xff;
1564 for (maddr = 0; maddr < 31; maddr++) {
1565 unsigned int reg_data;
1566
1567 if (big_sur_ge_phy_read(lp->emac, maddr, MII_BMCR, ®_data) == 0) {
1568 lp->mii_addr = maddr;
1569 break;
1570 }
1571 }
1572
1573 if (lp->mii_addr == 0xff) {
1574 lp->mii_addr = 0;
1575 printk(KERN_WARNING
1576 "%s: No PHY detected. Assuming a PHY at address %d.\n",
1577 netdev->name, lp->mii_addr);
1578 }
1579
1580 netdev->open = big_sur_ge_open;
1581 netdev->stop = big_sur_ge_close;
1582 netdev->get_stats = big_sur_ge_get_stats;
1583 netdev->do_ioctl = big_sur_ge_ioctl;
1584 netdev->tx_timeout = big_sur_ge_tx_timeout;
1585 netdev->watchdog_timeo = TX_TIMEOUT;
1586 netdev->hard_start_xmit = big_sur_start_xmit;
1587 netdev->set_multicast_list = big_sur_ge_set_multi;
1588
1589 printk(KERN_INFO
1590 "%s: PMC-Sierra Big Sur Ethernet Device %d at 0x%08X mapped to 0x%08X\n",
1591 netdev->name, index,
1592 lp->save_base_address, config->base_address);
1593
1594 return 0;
1595 }
1596
big_sur_ge_init(void)1597 static int __init big_sur_ge_init(void)
1598 {
1599 int index = 0;
1600
1601 while (big_sur_ge_probe(index++) == 0);
1602
1603 return (index > 1) ? 0 : -ENODEV;
1604 }
1605
big_sur_ge_cleanup_module(void)1606 static void __init big_sur_ge_cleanup_module(void)
1607 {
1608 /* Nothing to do here */
1609 }
1610
1611 module_init(big_sur_ge_init);
1612 module_exit(big_sur_ge_cleanup_module);
1613
1614