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Searched refs:BC_Write_Reg (Results 1 – 25 of 35) sorted by relevance

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/linux-2.4.37.9/drivers/isdn/hisax/
Djade.c28 cs->BC_Write_Reg(cs, -1, 0x50, 0x19); in JadeVersion()
59 cs->BC_Write_Reg(cs, -1, COMM_JADE+1, value); in jade_write_indirect()
61 cs->BC_Write_Reg(cs, -1, COMM_JADE, reg); in jade_write_indirect()
97 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO:0x00)); in modejade()
98 cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU|jadeCCR0_ITF)); in modejade()
99 cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00); in modejade()
106 cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07); in modejade()
107 cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07); in modejade()
110 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00); in modejade()
111 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00); in modejade()
[all …]
Dhscx.c51 cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF); in modehscx()
52 cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF); in modehscx()
53 cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF); in modehscx()
54 cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0); in modehscx()
55 cs->BC_Write_Reg(cs, hscx, HSCX_RLCR, 0x0); in modehscx()
56 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1, in modehscx()
58 cs->BC_Write_Reg(cs, hscx, HSCX_CCR2, 0x30); in modehscx()
59 cs->BC_Write_Reg(cs, hscx, HSCX_XCCR, 7); in modehscx()
60 cs->BC_Write_Reg(cs, hscx, HSCX_RCCR, 7); in modehscx()
67 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, in modehscx()
[all …]
Dhfcscard.c74 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset On */ in reset_hfcs()
82 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset Off */ in reset_hfcs()
89 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); in reset_hfcs()
90 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CLKDEL, 0x0e); in reset_hfcs()
91 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_TEST, HFCD_AUTO_AWAKE); /* S/T Auto awake */ in reset_hfcs()
93 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); in reset_hfcs()
98 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M1, cs->hw.hfcD.int_m1); in reset_hfcs()
99 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M2, cs->hw.hfcD.int_m2); in reset_hfcs()
100 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, HFCD_LOAD_STATE | 2); /* HFC ST 2 */ in reset_hfcs()
102 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, 2); /* HFC ST 2 */ in reset_hfcs()
[all …]
Dipacx.c636 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC in bch_empty_fifo()
647 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC in bch_empty_fifo()
696 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++); in bch_fill_fifo()
697 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a)); in bch_fill_fifo()
740 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC in bch_int()
780 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES in bch_int()
820 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES in bch_int()
855 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off in bch_mode()
856 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj. in bch_mode()
857 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off in bch_mode()
[all …]
Dw6692.c243 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT); in W6692B_empty_fifo()
252 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT); in W6692B_empty_fifo()
295 …cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACT | W_B_CMDR_XMS | (more ? 0 : W_B_CMDR_X… in W6692B_fill_fifo()
334 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RRST | W_B_CMDR_RACT); in W6692B_interrupt()
403 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_XRST | W_B_CMDR_RACT); in W6692B_interrupt()
730 cs->BC_Write_Reg(cs, bchan, W_B_MODE, 0); in W6692Bmode()
733 cs->BC_Write_Reg(cs, bchan, W_B_MODE, W_B_MODE_MMS); in W6692Bmode()
736 cs->BC_Write_Reg(cs, bchan, W_B_MODE, W_B_MODE_ITF); in W6692Bmode()
737 cs->BC_Write_Reg(cs, bchan, W_B_ADM1, 0xff); in W6692Bmode()
738 cs->BC_Write_Reg(cs, bchan, W_B_ADM2, 0xff); in W6692Bmode()
[all …]
Disar.c64 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg); in sendmsg()
65 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len); in sendmsg()
66 cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0); in sendmsg()
68 cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]); in sendmsg()
70 cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]); in sendmsg()
86 cs->BC_Write_Reg(cs, 1, ISAR_HIS, his); in sendmsg()
98 cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0); in rcv_mbox()
118 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); in rcv_mbox()
171 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); in ISARVersion()
232 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); in isar_load_firmware()
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Dhfc_2bs0.c109 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip); in hfc_clear_fifo()
271 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip); in hfc_fill_fifo()
317 cs->BC_Write_Reg(cs, HFC_DATA_NODEB, cip, bcs->tx_skb->data[idx++]); in hfc_fill_fifo()
357 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip); in main_irq_hfc()
445 cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt); in mode_hfc()
469 cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt); in mode_hfc()
Dnj_s.c271 cs->BC_Write_Reg = &dummywr; in setup_netjet_s()
Dnj_u.c266 cs->BC_Write_Reg = &dummywr; in setup_netjet_u()
Dsportster.c263 cs->BC_Write_Reg = &WriteHSCX; in setup_sportster()
Dtelespci.c343 cs->BC_Write_Reg = &WriteHSCX; in setup_telespci()
Davm_a1p.c296 cs->BC_Write_Reg = &WriteHSCX; in setup_avm_a1_pcmcia()
Dmic.c241 cs->BC_Write_Reg = &WriteHSCX; in setup_mic()
Denternow_pci.c414 cs->BC_Write_Reg = &dummywr; in setup_enternow_pci()
Ds0box.c260 cs->BC_Write_Reg = &WriteHSCX; in setup_s0box()
Disurf.c314 cs->BC_Write_Reg = &WriteISAR; in setup_isurf()
Dsaphir.c304 cs->BC_Write_Reg = &WriteHSCX; in setup_saphir()
Dteles0.c359 cs->BC_Write_Reg = &WriteHSCX; in setup_teles0()
Dbkm_a4t.c347 cs->BC_Write_Reg = &WriteJADE; in setup_bkm_a4t()
Dix1_micro.c316 cs->BC_Write_Reg = &WriteHSCX; in setup_ix1micro()
Ddiva.c1158 cs->BC_Write_Reg = &WriteHSCX; in setup_diva()
1175 cs->BC_Write_Reg = &MemWriteHSCX; in setup_diva()
1186 cs->BC_Write_Reg = &MemWriteHSCX_IPACX; in setup_diva()
Davm_a1.c319 cs->BC_Write_Reg = &WriteHSCX; in setup_avm_a1()
Dteleint.c340 cs->BC_Write_Reg = &WriteHFC; in setup_TeleInt()
Dniccy.c389 cs->BC_Write_Reg = &WriteHSCX; in setup_niccy()
Dbkm_a8.c456 cs->BC_Write_Reg = &WriteHSCX; in setup_sct_quadro()

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