1 #ifndef __ASM_SH_UBC_H 2 #define __ASM_SH_UBC_H 3 4 /* User Break Controller */ 5 6 #if defined(CONFIG_CPU_SUBTYPE_SH7709) 7 #define UBC_TYPE_SH7729 (cpu_data->type == CPU_SH7729) 8 #else 9 #define UBC_TYPE_SH7729 0 10 #endif 11 12 #if defined(__sh3__) 13 #define UBC_BARA 0xffffffb0 14 #define UBC_BAMRA 0xffffffb4 15 #define UBC_BBRA 0xffffffb8 16 #define UBC_BASRA 0xffffffe4 17 #define UBC_BARB 0xffffffa0 18 #define UBC_BAMRB 0xffffffa4 19 #define UBC_BBRB 0xffffffa8 20 #define UBC_BASRB 0xffffffe8 21 #define UBC_BDRB 0xffffff90 22 #define UBC_BDMRB 0xffffff94 23 #define UBC_BRCR 0xffffff98 24 #elif defined(__SH4__) 25 #define UBC_BARA 0xff200000 26 #define UBC_BAMRA 0xff200004 27 #define UBC_BBRA 0xff200008 28 #define UBC_BASRA 0xff000014 29 #define UBC_BARB 0xff20000c 30 #define UBC_BAMRB 0xff200010 31 #define UBC_BBRB 0xff200014 32 #define UBC_BASRB 0xff000018 33 #define UBC_BDRB 0xff200018 34 #define UBC_BDMRB 0xff20001c 35 #define UBC_BRCR 0xff200020 36 #endif 37 38 #define BAMR_ASID (1 << 2) 39 #define BAMR_NONE 0 40 #define BAMR_10 0x1 41 #define BAMR_12 0x2 42 #define BAMR_ALL 0x3 43 #define BAMR_16 0x8 44 #define BAMR_20 0x9 45 46 #define BBR_INST (1 << 4) 47 #define BBR_DATA (2 << 4) 48 #define BBR_READ (1 << 2) 49 #define BBR_WRITE (2 << 2) 50 #define BBR_BYTE 0x1 51 #define BBR_HALF 0x2 52 #define BBR_LONG 0x3 53 #define BBR_QUAD (1 << 6) /* SH7750 */ 54 #define BBR_CPU (1 << 6) /* SH7709A,SH7729 */ 55 #define BBR_DMA (2 << 6) /* SH7709A,SH7729 */ 56 57 #define BRCR_CMFA (1 << 15) 58 #define BRCR_CMFB (1 << 14) 59 #define BRCR_PCTE (1 << 11) 60 #define BRCR_PCBA (1 << 10) /* 1: after execution */ 61 #define BRCR_DBEB (1 << 7) 62 #define BRCR_PCBB (1 << 6) 63 #define BRCR_SEQ (1 << 3) 64 #define BRCR_UBDE (1 << 0) 65 66 #ifndef __ASSEMBLY__ 67 /* arch/sh/kernel/ubc.S */ 68 extern void ubc_wakeup(void); 69 extern void ubc_sleep(void); 70 #endif 71 72 #endif /* __ASM_SH_UBC_H */ 73 74