Searched refs:B0_XS_CSR (Results 1 – 3 of 3) sorted by relevance
324 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XS_CSR) ;1014 outpd(ADDR(B0_XS_CSR),CSR_SET_RESET) ;1018 outpd(ADDR(B0_XS_CSR),CSR_CLR_RESET) ;
568 outpd(ADDR(B0_XS_CSR),CSR_START) ;1715 outpd(ADDR(B0_XS_CSR),CSR_START) ;
1093 #define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */ macro