Searched refs:B0_XA_CSR (Results 1 – 3 of 3) sorted by relevance
335 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XA_CSR) ;1013 outpd(ADDR(B0_XA_CSR),CSR_SET_RESET) ;1017 outpd(ADDR(B0_XA_CSR),CSR_CLR_RESET) ;
563 outpd(ADDR(B0_XA_CSR),CSR_START) ;1712 outpd(ADDR(B0_XA_CSR),CSR_START) ;1960 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1092 #define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */ macro