Searched refs:B0_R2_CSR (Results 1 – 6 of 6) sorted by relevance
520 SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_P); in SkGeHwErr()695 SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C); in SkGeSirqIsr()
1091 #define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/ macro
39 B0_R2_CSR = 0x0064, enumerator
2800 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); in skge_error_irq()
375 #define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */ macro
298 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R2_CSR) ;