1 // ---------------------------------------------------------------------------- 2 // ATMEL Microcontroller Software Support - ROUSSET - 3 // ---------------------------------------------------------------------------- 4 // The software is delivered "AS IS" without warranty or condition of any 5 // kind, either express, implied or statutory. This includes without 6 // limitation any warranty or condition with respect to merchantability or 7 // fitness for any particular purpose, or against the infringements of 8 // intellectual property rights of others. 9 // ---------------------------------------------------------------------------- 10 // File Name : AT91RM9200.h 11 // Object : AT91RM9200 / USART definitions 12 // Generated : AT91 SW Application Group 01/17/2003 (13:41:22) 13 // 14 // ---------------------------------------------------------------------------- 15 16 #ifndef AT91RM9200_USART_H 17 #define AT91RM9200_USART_H 18 19 // ***************************************************************************** 20 // SOFTWARE API DEFINITION FOR Usart 21 // ***************************************************************************** 22 #ifndef __ASSEMBLY__ 23 24 typedef struct _AT91S_USART { 25 AT91_REG US_CR; // Control Register 26 AT91_REG US_MR; // Mode Register 27 AT91_REG US_IER; // Interrupt Enable Register 28 AT91_REG US_IDR; // Interrupt Disable Register 29 AT91_REG US_IMR; // Interrupt Mask Register 30 AT91_REG US_CSR; // Channel Status Register 31 AT91_REG US_RHR; // Receiver Holding Register 32 AT91_REG US_THR; // Transmitter Holding Register 33 AT91_REG US_BRGR; // Baud Rate Generator Register 34 AT91_REG US_RTOR; // Receiver Time-out Register 35 AT91_REG US_TTGR; // Transmitter Time-guard Register 36 AT91_REG Reserved0[5]; // 37 AT91_REG US_FIDI; // FI_DI_Ratio Register 38 AT91_REG US_NER; // Nb Errors Register 39 AT91_REG US_XXR; // XON_XOFF Register 40 AT91_REG US_IF; // IRDA_FILTER Register 41 AT91_REG Reserved1[44]; // 42 AT91_REG US_RPR; // Receive Pointer Register 43 AT91_REG US_RCR; // Receive Counter Register 44 AT91_REG US_TPR; // Transmit Pointer Register 45 AT91_REG US_TCR; // Transmit Counter Register 46 AT91_REG US_RNPR; // Receive Next Pointer Register 47 AT91_REG US_RNCR; // Receive Next Counter Register 48 AT91_REG US_TNPR; // Transmit Next Pointer Register 49 AT91_REG US_TNCR; // Transmit Next Counter Register 50 AT91_REG US_PTCR; // PDC Transfer Control Register 51 AT91_REG US_PTSR; // PDC Transfer Status Register 52 } AT91S_USART, *AT91PS_USART; 53 54 #endif 55 56 // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 57 #define AT91C_US_RSTRX ( 0x1 << 2) // (USART) Reset Receiver 58 #define AT91C_US_RSTTX ( 0x1 << 3) // (USART) Reset Transmitter 59 #define AT91C_US_RXEN ( 0x1 << 4) // (USART) Receiver Enable 60 #define AT91C_US_RXDIS ( 0x1 << 5) // (USART) Receiver Disable 61 #define AT91C_US_TXEN ( 0x1 << 6) // (USART) Transmitter Enable 62 #define AT91C_US_TXDIS ( 0x1 << 7) // (USART) Transmitter Disable 63 #define AT91C_US_RSTSTA ( 0x1 << 8) // (USART) Reset Status Bits 64 #define AT91C_US_STTBRK ( 0x1 << 9) // (USART) Start Break 65 #define AT91C_US_STPBRK ( 0x1 << 10) // (USART) Stop Break 66 #define AT91C_US_STTTO ( 0x1 << 11) // (USART) Start Time-out 67 #define AT91C_US_SENDA ( 0x1 << 12) // (USART) Send Address 68 #define AT91C_US_RSTIT ( 0x1 << 13) // (USART) Reset Iterations 69 #define AT91C_US_RSTNACK ( 0x1 << 14) // (USART) Reset Non Acknowledge 70 #define AT91C_US_RETTO ( 0x1 << 15) // (USART) Rearm Time-out 71 #define AT91C_US_DTREN ( 0x1 << 16) // (USART) Data Terminal ready Enable 72 #define AT91C_US_DTRDIS ( 0x1 << 17) // (USART) Data Terminal ready Disable 73 #define AT91C_US_RTSEN ( 0x1 << 18) // (USART) Request to Send enable 74 #define AT91C_US_RTSDIS ( 0x1 << 19) // (USART) Request to Send Disable 75 // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 76 #define AT91C_US_USMODE ( 0xF << 0) // (USART) Usart mode 77 #define AT91C_US_USMODE_NORMAL ( 0x0) // (USART) Normal 78 #define AT91C_US_USMODE_RS485 ( 0x1) // (USART) RS485 79 #define AT91C_US_USMODE_HWHSH ( 0x2) // (USART) Hardware Handshaking 80 #define AT91C_US_USMODE_MODEM ( 0x3) // (USART) Modem 81 #define AT91C_US_USMODE_ISO7816_0 ( 0x4) // (USART) ISO7816 protocol: T = 0 82 #define AT91C_US_USMODE_ISO7816_1 ( 0x6) // (USART) ISO7816 protocol: T = 1 83 #define AT91C_US_USMODE_IRDA ( 0x8) // (USART) IrDA 84 #define AT91C_US_USMODE_SWHSH ( 0xC) // (USART) Software Handshaking 85 #define AT91C_US_CLKS ( 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock 86 #define AT91C_US_CLKS_CLOCK ( 0x0 << 4) // (USART) Clock 87 #define AT91C_US_CLKS_FDIV1 ( 0x1 << 4) // (USART) fdiv1 88 #define AT91C_US_CLKS_SLOW ( 0x2 << 4) // (USART) slow_clock (ARM) 89 #define AT91C_US_CLKS_EXT ( 0x3 << 4) // (USART) External (SCK) 90 #define AT91C_US_CHRL ( 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock 91 #define AT91C_US_CHRL_5_BITS ( 0x0 << 6) // (USART) Character Length: 5 bits 92 #define AT91C_US_CHRL_6_BITS ( 0x1 << 6) // (USART) Character Length: 6 bits 93 #define AT91C_US_CHRL_7_BITS ( 0x2 << 6) // (USART) Character Length: 7 bits 94 #define AT91C_US_CHRL_8_BITS ( 0x3 << 6) // (USART) Character Length: 8 bits 95 #define AT91C_US_SYNC ( 0x1 << 8) // (USART) Synchronous Mode Select 96 #define AT91C_US_PAR ( 0x7 << 9) // (USART) Parity type 97 #define AT91C_US_PAR_EVEN ( 0x0 << 9) // (USART) Even Parity 98 #define AT91C_US_PAR_ODD ( 0x1 << 9) // (USART) Odd Parity 99 #define AT91C_US_PAR_SPACE ( 0x2 << 9) // (USART) Parity forced to 0 (Space) 100 #define AT91C_US_PAR_MARK ( 0x3 << 9) // (USART) Parity forced to 1 (Mark) 101 #define AT91C_US_PAR_NONE ( 0x4 << 9) // (USART) No Parity 102 #define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9) // (USART) Multi-drop mode 103 #define AT91C_US_NBSTOP ( 0x3 << 12) // (USART) Number of Stop bits 104 #define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12) // (USART) 1 stop bit 105 #define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits 106 #define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12) // (USART) 2 stop bits 107 #define AT91C_US_CHMODE ( 0x3 << 14) // (USART) Channel Mode 108 #define AT91C_US_CHMODE_NORMAL ( 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART. 109 #define AT91C_US_CHMODE_AUTO ( 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin. 110 #define AT91C_US_CHMODE_LOCAL ( 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. 111 #define AT91C_US_CHMODE_REMOTE ( 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin. 112 #define AT91C_US_MSBF ( 0x1 << 16) // (USART) Bit Order 113 #define AT91C_US_MODE9 ( 0x1 << 17) // (USART) 9-bit Character length 114 #define AT91C_US_CKLO ( 0x1 << 18) // (USART) Clock Output Select 115 #define AT91C_US_OVER ( 0x1 << 19) // (USART) Over Sampling Mode 116 #define AT91C_US_INACK ( 0x1 << 20) // (USART) Inhibit Non Acknowledge 117 #define AT91C_US_DSNACK ( 0x1 << 21) // (USART) Disable Successive NACK 118 #define AT91C_US_MAX_ITER ( 0x1 << 24) // (USART) Number of Repetitions 119 #define AT91C_US_FILTER ( 0x1 << 28) // (USART) Receive Line Filter 120 // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 121 #define AT91C_US_RXRDY ( 0x1 << 0) // (USART) RXRDY Interrupt 122 #define AT91C_US_TXRDY ( 0x1 << 1) // (USART) TXRDY Interrupt 123 #define AT91C_US_RXBRK ( 0x1 << 2) // (USART) Break Received/End of Break 124 #define AT91C_US_ENDRX ( 0x1 << 3) // (USART) End of Receive Transfer Interrupt 125 #define AT91C_US_ENDTX ( 0x1 << 4) // (USART) End of Transmit Interrupt 126 #define AT91C_US_OVRE ( 0x1 << 5) // (USART) Overrun Interrupt 127 #define AT91C_US_FRAME ( 0x1 << 6) // (USART) Framing Error Interrupt 128 #define AT91C_US_PARE ( 0x1 << 7) // (USART) Parity Error Interrupt 129 #define AT91C_US_TIMEOUT ( 0x1 << 8) // (USART) Receiver Time-out 130 #define AT91C_US_TXEMPTY ( 0x1 << 9) // (USART) TXEMPTY Interrupt 131 #define AT91C_US_ITERATION ( 0x1 << 10) // (USART) Max number of Repetitions Reached 132 #define AT91C_US_TXBUFE ( 0x1 << 11) // (USART) TXBUFE Interrupt 133 #define AT91C_US_RXBUFF ( 0x1 << 12) // (USART) RXBUFF Interrupt 134 #define AT91C_US_NACK ( 0x1 << 13) // (USART) Non Acknowledge 135 #define AT91C_US_RIIC ( 0x1 << 16) // (USART) Ring INdicator Input Change Flag 136 #define AT91C_US_DSRIC ( 0x1 << 17) // (USART) Data Set Ready Input Change Flag 137 #define AT91C_US_DCDIC ( 0x1 << 18) // (USART) Data Carrier Flag 138 #define AT91C_US_CTSIC ( 0x1 << 19) // (USART) Clear To Send Input Change Flag 139 #define AT91C_US_COMM_TX ( 0x1 << 30) // (USART) COMM_TX Interrupt 140 #define AT91C_US_COMM_RX ( 0x1 << 31) // (USART) COMM_RX Interrupt 141 // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 142 // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 143 // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 144 #define AT91C_US_RI ( 0x1 << 20) // (USART) Image of RI Input 145 #define AT91C_US_DSR ( 0x1 << 21) // (USART) Image of DSR Input 146 #define AT91C_US_DCD ( 0x1 << 22) // (USART) Image of DCD Input 147 #define AT91C_US_CTS ( 0x1 << 23) // (USART) Image of CTS Input 148 149 #endif 150