1 // ---------------------------------------------------------------------------- 2 // ATMEL Microcontroller Software Support - ROUSSET - 3 // ---------------------------------------------------------------------------- 4 // The software is delivered "AS IS" without warranty or condition of any 5 // kind, either express, implied or statutory. This includes without 6 // limitation any warranty or condition with respect to merchantability or 7 // fitness for any particular purpose, or against the infringements of 8 // intellectual property rights of others. 9 // ---------------------------------------------------------------------------- 10 // File Name : AT91RM9200.h 11 // Object : AT91RM9200 / SPI definitions 12 // Generated : AT91 SW Application Group 12/03/2002 (10:48:02) 13 // 14 // ---------------------------------------------------------------------------- 15 16 #ifndef AT91RM9200_SPI_H 17 #define AT91RM9200_SPI_H 18 19 // ***************************************************************************** 20 // SOFTWARE API DEFINITION FOR Serial Parallel Interface 21 // ***************************************************************************** 22 #ifndef __ASSEMBLY__ 23 24 typedef struct _AT91S_SPI { 25 AT91_REG SPI_CR; // Control Register 26 AT91_REG SPI_MR; // Mode Register 27 AT91_REG SPI_RDR; // Receive Data Register 28 AT91_REG SPI_TDR; // Transmit Data Register 29 AT91_REG SPI_SR; // Status Register 30 AT91_REG SPI_IER; // Interrupt Enable Register 31 AT91_REG SPI_IDR; // Interrupt Disable Register 32 AT91_REG SPI_IMR; // Interrupt Mask Register 33 AT91_REG Reserved0[4]; // 34 AT91_REG SPI_CSR0; // Chip Select Register 0 35 AT91_REG SPI_CSR1; // Chip Select Register 1 36 AT91_REG SPI_CSR2; // Chip Select Register 2 37 AT91_REG SPI_CSR3; // Chip Select Register 3 38 AT91_REG Reserved1[48]; // 39 AT91_REG SPI_RPR; // Receive Pointer Register 40 AT91_REG SPI_RCR; // Receive Counter Register 41 AT91_REG SPI_TPR; // Transmit Pointer Register 42 AT91_REG SPI_TCR; // Transmit Counter Register 43 AT91_REG SPI_RNPR; // Receive Next Pointer Register 44 AT91_REG SPI_RNCR; // Receive Next Counter Register 45 AT91_REG SPI_TNPR; // Transmit Next Pointer Register 46 AT91_REG SPI_TNCR; // Transmit Next Counter Register 47 AT91_REG SPI_PTCR; // PDC Transfer Control Register 48 AT91_REG SPI_PTSR; // PDC Transfer Status Register 49 } AT91S_SPI, *AT91PS_SPI; 50 51 #endif 52 53 // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 54 #define AT91C_SPI_SPIEN ( 0x1 << 0) // (SPI) SPI Enable 55 #define AT91C_SPI_SPIDIS ( 0x1 << 1) // (SPI) SPI Disable 56 #define AT91C_SPI_SWRST ( 0x1 << 7) // (SPI) SPI Software reset 57 // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 58 #define AT91C_SPI_MSTR ( 0x1 << 0) // (SPI) Master/Slave Mode 59 #define AT91C_SPI_PS ( 0x1 << 1) // (SPI) Peripheral Select 60 #define AT91C_SPI_PS_FIXED ( 0x0 << 1) // (SPI) Fixed Peripheral Select 61 #define AT91C_SPI_PS_VARIABLE ( 0x1 << 1) // (SPI) Variable Peripheral Select 62 #define AT91C_SPI_PCSDEC ( 0x1 << 2) // (SPI) Chip Select Decode 63 #define AT91C_SPI_DIV32 ( 0x1 << 3) // (SPI) Clock Selection 64 #define AT91C_SPI_MODFDIS ( 0x1 << 4) // (SPI) Mode Fault Detection 65 #define AT91C_SPI_LLB ( 0x1 << 7) // (SPI) Clock Selection 66 #define AT91C_SPI_PCS ( 0xF << 16) // (SPI) Peripheral Chip Select 67 #define AT91C_SPI_DLYBCS ( 0xFF << 24) // (SPI) Delay Between Chip Selects 68 // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 69 #define AT91C_SPI_RD ( 0xFFFF << 0) // (SPI) Receive Data 70 #define AT91C_SPI_RPCS ( 0xF << 16) // (SPI) Peripheral Chip Select Status 71 // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 72 #define AT91C_SPI_TD ( 0xFFFF << 0) // (SPI) Transmit Data 73 #define AT91C_SPI_TPCS ( 0xF << 16) // (SPI) Peripheral Chip Select Status 74 // -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 75 #define AT91C_SPI_RDRF ( 0x1 << 0) // (SPI) Receive Data Register Full 76 #define AT91C_SPI_TDRE ( 0x1 << 1) // (SPI) Transmit Data Register Empty 77 #define AT91C_SPI_MODF ( 0x1 << 2) // (SPI) Mode Fault Error 78 #define AT91C_SPI_OVRES ( 0x1 << 3) // (SPI) Overrun Error Status 79 #define AT91C_SPI_SPENDRX ( 0x1 << 4) // (SPI) End of Receiver Transfer 80 #define AT91C_SPI_SPENDTX ( 0x1 << 5) // (SPI) End of Transmit Transfer 81 #define AT91C_SPI_RXBUFF ( 0x1 << 6) // (SPI) RXBUFF Interrupt 82 #define AT91C_SPI_TXBUFE ( 0x1 << 7) // (SPI) TXBUFE Interrupt 83 #define AT91C_SPI_SPIENS ( 0x1 << 16) // (SPI) Enable Status 84 // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 85 // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 86 // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 87 // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 88 #define AT91C_SPI_CPOL ( 0x1 << 0) // (SPI) Clock Polarity 89 #define AT91C_SPI_NCPHA ( 0x1 << 1) // (SPI) Clock Phase 90 #define AT91C_SPI_BITS ( 0xF << 4) // (SPI) Bits Per Transfer 91 #define AT91C_SPI_BITS_8 ( 0x0 << 4) // (SPI) 8 Bits Per transfer 92 #define AT91C_SPI_BITS_9 ( 0x1 << 4) // (SPI) 9 Bits Per transfer 93 #define AT91C_SPI_BITS_10 ( 0x2 << 4) // (SPI) 10 Bits Per transfer 94 #define AT91C_SPI_BITS_11 ( 0x3 << 4) // (SPI) 11 Bits Per transfer 95 #define AT91C_SPI_BITS_12 ( 0x4 << 4) // (SPI) 12 Bits Per transfer 96 #define AT91C_SPI_BITS_13 ( 0x5 << 4) // (SPI) 13 Bits Per transfer 97 #define AT91C_SPI_BITS_14 ( 0x6 << 4) // (SPI) 14 Bits Per transfer 98 #define AT91C_SPI_BITS_15 ( 0x7 << 4) // (SPI) 15 Bits Per transfer 99 #define AT91C_SPI_BITS_16 ( 0x8 << 4) // (SPI) 16 Bits Per transfer 100 #define AT91C_SPI_SCBR ( 0xFF << 8) // (SPI) Serial Clock Baud Rate 101 #define AT91C_SPI_DLYBS ( 0xFF << 16) // (SPI) Serial Clock Baud Rate 102 #define AT91C_SPI_DLYBCT ( 0xFF << 24) // (SPI) Delay Between Consecutive Transfers 103 104 #endif 105