Searched refs:ADCR1_D_CHSW (Results 1 – 2 of 2) sorted by relevance
105 #define ADCR1_D_CHSW 0x08 /* the specs are wrong. its bit 3, not 4 */ macro
607 outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1); in w83977af_dma_write()759 outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL, in w83977af_dma_receive()