Searched refs:rMEMP (Results 1 – 6 of 6) sorted by relevance
| /glibc-2.36/sysdeps/powerpc/powerpc32/power6/ |
| D | memset.S | 37 #define rMEMP r6 /* Address at which we are storing. */ macro
47 mr rMEMP, rMEMP0
55 add rMEMP, rMEMP, rALIGN
61 sth rCHR, -2(rMEMP)
70 andi. rALIGN, rMEMP, 0x1C
74 add rMEMP, rMEMP, rALIGN
77 mr rMEMP2, rMEMP
108 andi. rTMP,rMEMP,127
110 addi rMEMP3,rMEMP,32
113 stw rCHR,0(rMEMP)
[all …]
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| /glibc-2.36/sysdeps/powerpc/powerpc32/ |
| D | memset.S | 38 #define rMEMP r6 /* address at which we are storing */ macro
53 mr rMEMP, rMEMP0
61 add rMEMP, rMEMP, rALIGN
66 L(g0): sth rCHR, -2(rMEMP) /* 16th instruction from .align */
73 andi. rALIGN, rMEMP, 0x1C
77 add rMEMP, rMEMP, rALIGN
80 mr rMEMP2, rMEMP
111 add rMEMP, rMEMP, rALIGN
117 L(c3): dcbtst rNEG64, rMEMP
118 stw rCHR, -4(rMEMP)
[all …]
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| /glibc-2.36/sysdeps/powerpc/powerpc64/power6/ |
| D | memset.S | 40 #define rMEMP r6 /* Address at which we are storing. */ macro
48 mr rMEMP, rMEMP0
58 add rMEMP, rMEMP, rALIGN
67 sth rCHR, -6(rMEMP)
69 stw rCHR, -4(rMEMP)
78 sth rCHR, -2(rMEMP)
87 andi. rALIGN, rMEMP, 0x18
92 add rMEMP, rMEMP, rALIGN
95 mr rMEMP2, rMEMP
120 andi. rTMP,rMEMP,127
[all …]
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| /glibc-2.36/sysdeps/powerpc/powerpc32/power4/ |
| D | memset.S | 37 #define rMEMP r6 /* Address at which we are storing. */ macro
48 mr rMEMP, rMEMP0
57 add rMEMP, rMEMP, rALIGN
63 sth rCHR, -2(rMEMP)
71 andi. rALIGN, rMEMP, 0x1C
75 add rMEMP, rMEMP, rALIGN
78 mr rMEMP2, rMEMP
101 add rMEMP, rMEMP, rALIGN
106 L(c3): dcbtst rNEG64, rMEMP
107 stw rCHR, -4(rMEMP)
[all …]
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| /glibc-2.36/sysdeps/powerpc/powerpc64/ |
| D | memset.S | 47 #define rMEMP r6 /* Address at which we are storing. */ macro
58 mr rMEMP, rMEMP0
68 add rMEMP, rMEMP, rALIGN
77 sth rCHR, -6(rMEMP)
79 stw rCHR, -4(rMEMP)
88 sth rCHR, -2(rMEMP)
97 andi. rALIGN, rMEMP, 0x18
102 add rMEMP, rMEMP, rALIGN
105 mr rMEMP2, rMEMP
124 add rMEMP, rMEMP, rALIGN
[all …]
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| /glibc-2.36/sysdeps/powerpc/powerpc64/power4/ |
| D | memset.S | 40 #define rMEMP r6 /* Address at which we are storing. */ macro
51 mr rMEMP, rMEMP0
61 add rMEMP, rMEMP, rALIGN
70 sth rCHR, -6(rMEMP)
72 stw rCHR, -4(rMEMP)
81 sth rCHR, -2(rMEMP)
90 andi. rALIGN, rMEMP, 0x18
95 add rMEMP, rMEMP, rALIGN
98 mr rMEMP2, rMEMP
117 add rMEMP, rMEMP, rALIGN
[all …]
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