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/glibc-2.36/sysdeps/ia64/fpu/
De_powf.S411 pow_GR_rcs0_mask = r16 define
1481 mov pow_GR_rcs0_mask = 0x0c00 // Set mask for rc.s0
1514 (p7) and pow_GR_rcs0 = pow_GR_rcs0_mask, pow_GR_Fpsr // Isolate rc.s0