Searched refs:i7 (Results 1 – 22 of 22) sorted by relevance
| /glibc-2.36/sysdeps/sparc/sparc64/ |
| D | dl-trampoline.S | 37 cfi_register(%o7, %i7)
80 cfi_register(%o7, %i7)
129 stx %i7, [%sp + STACK_BIAS + (15 * 8)]
211 jmpl %i7 + 8, %g0
232 cfi_register(%o7, %i7)
254 mov %i7, %o2
294 cfi_register(%o7, %i7)
300 mov %i7, %o2
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| D | mul_1.S | 79 jmpl %i7+8,%g0
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| D | addmul_1.S | 80 jmpl %i7+8, %g0
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| D | submul_1.S | 79 jmpl %i7+8, %g0
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| /glibc-2.36/sysdeps/unix/sysv/linux/sparc/sparc32/ |
| D | ____longjmp_chk.S | 45 cfi_register(%o7, %i7)
105 PTR_DEMANGLE2 (%i7, %g1, %g4)
107 ld ENV(g1,JB_PC), %i7 /* Set return PC. */
110 jmp %i7 + 8
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| D | clone.S | 33 cfi_register(%o7, %i7)
62 jmpl %i7 + 8, %g0
71 jmpl %i7 + 8, %g0
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| D | getcontext.S | 39 add %i7, 8, %o0
70 st %i7, [%i0 + UC_MCONTEXT + MC_GREGS + GREG_O7]
79 jmpl %i7 + 8, %g0
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| D | swapcontext.S | 40 add %i7, 8, %o0
60 st %i7, [%i0 + UC_MCONTEXT + MC_GREGS + GREG_O7]
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| /glibc-2.36/sysdeps/sparc/sparc32/ |
| D | dl-trampoline.S | 37 cfi_register (%o7, %i7)
136 jmpl %i7 + 8, %g0
157 cfi_register(%o7, %i7)
161 mov %i7, %o2
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| D | __longjmp.S | 68 PTR_DEMANGLE2 (%i7, %g5, %g4)
71 ld ENV(g1,JB_PC), %i7 /* Set return PC. */
74 jmp %i7 + 8
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| D | strcmp.S | 212 4: jmpl %i7 + 8, %g0
230 jmpl %i7 + 8, %g0
255 jmpl %i7 + 8, %g0
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| /glibc-2.36/sysdeps/unix/sysv/linux/sparc/sparc64/ |
| D | clone.S | 37 cfi_register(%o7, %i7)
62 jmpl %i7 + 8, %g0
68 jmpl %i7 + 8, %g0
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| D | ____longjmp_chk.S | 46 cfi_register(%o7, %i7)
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| /glibc-2.36/sysdeps/sparc/ |
| D | backtrace.c | 88 unsigned long fp, i7; in __backtrace() local
91 asm volatile ("mov %%i7, %0" : "=r"(i7)); in __backtrace()
94 array[0] = (void *) i7; in __backtrace()
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| D | crtn.S | 40 jmp %i7 + 8
44 jmp %i7 + 8
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| D | sparc-mcount.S | 22 mov %i7, %o0
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| /glibc-2.36/sysdeps/sparc/sparc32/sparcv9/ |
| D | addmul_1.S | 78 jmpl %i7 + 0x8, %g0
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| D | submul_1.S | 79 jmpl %i7 + 0x8, %g0
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| /glibc-2.36/sysdeps/sparc/sparc64/multiarch/ |
| D | addmul_1-vis3.S | 84 jmpl %i7 + 8, %g0
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| D | submul_1-vis3.S | 84 jmpl %i7 + 8, %g0
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| /glibc-2.36/ChangeLog.old/ |
| D | ChangeLog.17 | 1344 on bit_Fast_Rep_String for Intel Core i7.
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| D | ChangeLog.18 | 91977 Use new sse2 version for core i3 - i7 as it's faster
93257 and i7.
93669 Enable unaligned load optimization for Intel Core i3, i5 and i7
93926 Assume Intel Core i3/i5/i7 processor if AVX is available.
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