| /glibc-2.36/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/ |
| D | s_rintf-vis3.S | 26 #define ZERO %f10 /* 0.0 */ macro
32 fzeros ZERO
34 fnegs ZERO, SIGN_BIT
41 fmovsuge %fcc3, ZERO, %f16
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| D | s_rint-vis3.S | 26 #define ZERO %f10 /* 0.0 */ macro
34 fzero ZERO
38 fnegd ZERO, SIGN_BIT
45 fmovduge %fcc3, ZERO, %f16
|
| D | s_llrintf-vis3.S | 26 #define ZERO %f10 /* 0.0 */ macro
32 fzeros ZERO
34 fnegs ZERO, SIGN_BIT
41 fmovsuge %fcc3, ZERO, %f16
|
| D | s_llrint-vis3.S | 26 #define ZERO %f10 /* 0.0 */ macro
34 fzero ZERO
38 fnegd ZERO, SIGN_BIT
45 fmovduge %fcc3, ZERO, %f16
|
| D | s_nearbyintf-vis3.S | 33 #define ZERO %f10 /* 0.0 */ macro
43 fzeros ZERO
45 fnegs ZERO, SIGN_BIT
52 fmovsuge %fcc3, ZERO, %f16
|
| D | s_nearbyint-vis3.S | 34 #define ZERO %f10 /* 0.0 */ macro
48 fzero ZERO
51 fnegd ZERO, SIGN_BIT
56 fmovduge %fcc3, ZERO, %f16
|
| /glibc-2.36/sysdeps/sparc/sparc64/fpu/multiarch/ |
| D | s_rintf-vis3.S | 26 #define ZERO %f10 /* 0.0 */ macro
31 fzeros ZERO
33 fnegs ZERO, SIGN_BIT
39 fmovsuge %fcc3, ZERO, %f16
|
| D | s_rint-vis3.S | 26 #define ZERO %f10 /* 0.0 */ macro
32 fzero ZERO
34 fnegd ZERO, SIGN_BIT
40 fmovduge %fcc3, ZERO, %f16
|
| D | s_lrint-vis3.S | 26 #define ZERO %f10 /* 0.0 */ macro
32 fzero ZERO
34 fnegd ZERO, SIGN_BIT
40 fmovduge %fcc3, ZERO, %f16
|
| D | s_lrintf-vis3.S | 26 #define ZERO %f10 /* 0.0 */ macro
31 fzeros ZERO
33 fnegs ZERO, SIGN_BIT
39 fmovsuge %fcc3, ZERO, %f16
|
| D | s_nearbyint-vis3.S | 33 #define ZERO %f10 /* 0.0 */ macro
43 fzero ZERO
45 fnegd ZERO, SIGN_BIT
52 fmovduge %fcc3, ZERO, %f16
|
| D | s_nearbyintf-vis3.S | 33 #define ZERO %f10 /* 0.0 */ macro
43 fzeros ZERO
45 fnegs ZERO, SIGN_BIT
51 fmovsuge %fcc3, ZERO, %f16
|
| /glibc-2.36/sysdeps/sparc/sparc64/fpu/ |
| D | s_rint.S | 32 #define ZERO %f10 /* 0.0 */ macro
38 fzero ZERO
40 fnegd ZERO, SIGN_BIT
47 fmovduge %fcc3, ZERO, %f16
|
| D | s_rintf.S | 32 #define ZERO %f10 /* 0.0 */ macro
37 fzeros ZERO
39 fnegs ZERO, SIGN_BIT
46 fmovsuge %fcc3, ZERO, %f16
|
| D | s_lrint.S | 32 #define ZERO %f10 /* 0.0 */ macro
38 fzero ZERO
40 fnegd ZERO, SIGN_BIT
47 fmovduge %fcc3, ZERO, %f16
|
| D | s_lrintf.S | 32 #define ZERO %f10 /* 0.0 */ macro
37 fzeros ZERO
39 fnegs ZERO, SIGN_BIT
46 fmovsuge %fcc3, ZERO, %f16
|
| D | s_nearbyint.S | 34 #define ZERO %f10 /* 0.0 */ macro
44 fzero ZERO
46 fnegd ZERO, SIGN_BIT
54 fmovduge %fcc3, ZERO, %f16
|
| D | s_nearbyintf.S | 34 #define ZERO %f10 /* 0.0 */ macro
44 fzeros ZERO
46 fnegs ZERO, SIGN_BIT
53 fmovsuge %fcc3, ZERO, %f16
|
| /glibc-2.36/sysdeps/sparc/sparc32/sparcv9/fpu/ |
| D | s_rintf.S | 32 #define ZERO %f10 /* 0.0 */ macro
38 fzeros ZERO
41 fnegs ZERO, SIGN_BIT
49 fmovsuge %fcc3, ZERO, %f16
|
| D | s_llrintf.S | 32 #define ZERO %f10 /* 0.0 */ macro
38 fzeros ZERO
41 fnegs ZERO, SIGN_BIT
49 fmovsuge %fcc3, ZERO, %f16
|
| D | s_lrintf.S | 32 #define ZERO %f10 /* 0.0 */ macro
38 fzeros ZERO
41 fnegs ZERO, SIGN_BIT
49 fmovsuge %fcc3, ZERO, %f16
|
| D | s_rint.S | 33 #define ZERO %f10 /* 0.0 */ macro
41 fzero ZERO
45 fnegd ZERO, SIGN_BIT
55 fmovduge %fcc3, ZERO, %f16
|
| D | s_llrint.S | 33 #define ZERO %f10 /* 0.0 */ macro
41 fzero ZERO
45 fnegd ZERO, SIGN_BIT
55 fmovduge %fcc3, ZERO, %f16
|
| D | s_nearbyintf.S | 34 #define ZERO %f10 /* 0.0 */ macro
45 fzeros ZERO
47 fnegs ZERO, SIGN_BIT
55 fmovsuge %fcc3, ZERO, %f16
|
| D | s_nearbyint.S | 35 #define ZERO %f10 /* 0.0 */ macro
50 fzero ZERO
53 fnegd ZERO, SIGN_BIT
59 fmovduge %fcc3, ZERO, %f16
|