| /glibc-2.36/sysdeps/x86_64/fpu/multiarch/ |
| D | svml_s_log1pf8_core_avx2.S | 33 #define SgnMask 0 macro
57 vmovups SgnMask+__svml_slog1p_data_internal(%rip), %ymm4
210 __declspec(align(32)) VUINT32 SgnMask[8][1];
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| D | svml_s_log1pf4_core_sse4.S | 33 #define SgnMask 0 macro
91 movups SgnMask+__svml_slog1p_data_internal(%rip), %xmm11
208 __declspec(align(16)) VUINT32 SgnMask[4][1];
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| D | svml_s_expm1f16_core_avx512.S | 39 #define SgnMask 448 macro
82 vandps SgnMask+__svml_sexpm1_data_internal_avx512(%rip), %zmm1, %zmm0
219 __declspec(align(64)) VUINT32 SgnMask[16][1];
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| D | svml_s_atanhf8_core_avx2.S | 38 #define SgnMask 0 macro
54 vmovaps ATANHF_DATA(SgnMask)(%rip), %ymm2
270 __declspec(align(32)) VUINT32 SgnMask[8][1];
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| D | svml_s_log1pf16_core_avx512.S | 33 #define SgnMask 0 macro
64 vmovups SgnMask+__svml_slog1p_data_internal(%rip), %zmm4
227 __declspec(align(64)) VUINT32 SgnMask[16][1];
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| D | svml_s_atanhf4_core_sse4.S | 39 #define SgnMask 16 macro
59 movups ATANHF_DATA(SgnMask)(%rip), %xmm1
275 __declspec(align(16)) VUINT32 SgnMask[4][1];
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| D | svml_d_log1p8_core_avx512.S | 35 #define SgnMask 192 macro
59 vmovups SgnMask+__svml_dlog1p_data_internal_avx512(%rip), %zmm14
247 __declspec(align(64)) VUINT32 SgnMask[8][2];
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| D | svml_d_expm18_core_avx512.S | 39 #define SgnMask 448 macro
89 vandpd SgnMask+__svml_dexpm1_data_internal_avx512(%rip), %zmm2, %zmm1
236 __declspec(align(64)) VUINT32 SgnMask[8][2];
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| D | svml_s_asinhf8_core_avx2.S | 34 #define SgnMask 0 macro
100 vandps SgnMask+__svml_sasinh_data_internal(%rip), %ymm9, %ymm6
381 __declspec(align(32)) VUINT32 SgnMask[8][1];
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| D | svml_s_asinhf4_core_sse4.S | 34 #define SgnMask 0 macro
135 movups SgnMask+__svml_sasinh_data_internal(%rip), %xmm6
429 __declspec(align(16)) VUINT32 SgnMask[4][1];
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| D | svml_d_log1p2_core_sse4.S | 41 #define SgnMask 12464 macro
68 movups SgnMask+__svml_dlog1p_data_internal(%rip), %xmm6
299 __declspec(align(16)) VUINT32 SgnMask[2][2];
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| D | svml_d_log1p4_core_avx2.S | 41 #define SgnMask 12640 macro
68 vmovupd SgnMask+__svml_dlog1p_data_internal(%rip), %ymm12
291 __declspec(align(32)) VUINT32 SgnMask[4][2];
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| D | svml_d_acosh2_core_sse4.S | 44 #define SgnMask 12464 macro
111 movups SgnMask+__svml_dacosh_data_internal(%rip), %xmm12
355 __declspec(align(16)) VUINT32 SgnMask[2][2];
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| D | svml_d_atanh2_core_sse4.S | 43 #define SgnMask 12464 macro
73 movups SgnMask+__svml_datanh_data_internal(%rip), %xmm7
401 __declspec(align(16)) VUINT32 SgnMask[2][2];
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| D | svml_d_atanh4_core_avx2.S | 43 #define SgnMask 12640 macro
73 vmovupd SgnMask+__svml_datanh_data_internal(%rip), %ymm7
367 __declspec(align(32)) VUINT32 SgnMask[4][2];
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| D | svml_d_asinh4_core_avx2.S | 42 #define SgnMask 12640 macro
81 vmovupd SgnMask+__svml_dasinh_data_internal(%rip), %ymm9
457 __declspec(align(32)) VUINT32 SgnMask[4][2];
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| D | svml_d_acosh4_core_avx2.S | 44 #define SgnMask 12640 macro
185 vandpd SgnMask+__svml_dacosh_data_internal(%rip), %ymm6, %ymm14
400 __declspec(align(32)) VUINT32 SgnMask[4][2];
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| D | svml_d_asinh2_core_sse4.S | 42 #define SgnMask 12464 macro
182 movups SgnMask+__svml_dasinh_data_internal(%rip), %xmm9
508 __declspec(align(16)) VUINT32 SgnMask[2][2];
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