1 #pragma once 2 #include <driver/usb/usb.h> 3 #include <driver/pci/pci.h> 4 #include <driver/pci/msi.h> 5 // #pragma GCC optimize("O0") 6 #define XHCI_MAX_HOST_CONTROLLERS 4 // 本驱动程序最大支持4个xhci root hub controller 7 #define XHCI_MAX_ROOT_HUB_PORTS 128 // 本驱动程序最大支持127个root hub 端口（第0个保留） 8 9 // ========== irq BEGIN =========== 10 11 #define XHCI_IRQ_DONE (1U << 31) // 当command trb 的status的第31位被驱动程序置位时，表明该trb已经执行完成（这是由于xhci规定，第31位可以由驱动程序自行决定用途） 12 /** 13 * @brief 每个xhci控制器的中断向量号 14 * 15 */ 16 const uint8_t xhci_controller_irq_num[XHCI_MAX_HOST_CONTROLLERS] = {157, 158, 159, 160}; 17 18 /** 19 * @brief 通过irq号寻找对应的主机控制器id 20 * 21 */ 22 #define xhci_find_hcid_by_irq_num(irq_num) ({ \ 23 int retval = -1; \ 24 for (int i = 0; i < XHCI_MAX_HOST_CONTROLLERS; ++i) \ 25 if (xhci_controller_irq_num[i] == irq_num) \ 26 retval = i; \ 27 retval; \ 28 }) 29 30 struct xhci_hc_irq_install_info_t 31 { 32 int processor; // 中断目标处理器 33 int8_t edge_trigger; // 是否边缘触发 34 int8_t assert; // 是否高电平触发 35 }; 36 // ========== irq END =========== 37 38 // ======== Capability Register Set BEGIN ============ 39 40 // xhci Capability Registers offset 41 #define XHCI_CAPS_CAPLENGTH 0x00 // Cap 寄存器组的长度 42 #define XHCI_CAPS_RESERVED 0x01 43 #define XHCI_CAPS_HCIVERSION 0x02 // 接口版本号 44 #define XHCI_CAPS_HCSPARAMS1 0x04 45 #define XHCI_CAPS_HCSPARAMS2 0x08 46 #define XHCI_CAPS_HCSPARAMS3 0x0c 47 #define XHCI_CAPS_HCCPARAMS1 0x10 // capability params 1 48 #define XHCI_CAPS_DBOFF 0x14 // Doorbell offset 49 #define XHCI_CAPS_RTSOFF 0x18 // Runtime register space offset 50 #define XHCI_CAPS_HCCPARAMS2 0x1c // capability params 2 51 52 struct xhci_caps_HCSPARAMS1_reg_t 53 { 54 unsigned max_slots : 8; // 最大插槽数 55 unsigned max_intrs : 11; // 最大中断数 56 unsigned reserved : 5; 57 unsigned max_ports : 8; // 最大端口数 58 } __attribute__((packed)); 59 60 struct xhci_caps_HCSPARAMS2_reg_t 61 { 62 unsigned ist : 4; // 同步调度阈值 63 unsigned ERST_Max : 4; // Event Ring Segment Table: Max segs 64 unsigned Reserved : 13; 65 unsigned max_scratchpad_buf_HI5 : 5; // 草稿行buffer地址（高5bit） 66 unsigned spr : 1; // scratchpad restore 67 unsigned max_scratchpad_buf_LO5 : 5; // 草稿行buffer地址（低5bit） 68 } __attribute__((packed)); 69 70 struct xhci_caps_HCSPARAMS3_reg_t 71 { 72 uint8_t u1_device_exit_latency; // 0~10ms 73 uint8_t Reserved; 74 uint16_t u2_device_exit_latency; // 0~2047ms 75 } __attribute__((packed)); 76 77 struct xhci_caps_HCCPARAMS1_reg_t 78 { 79 unsigned int ac64 : 1; // 64-bit addressing capability 80 unsigned int bnc : 1; // bw negotiation capability 81 unsigned int csz : 1; // context size 82 unsigned int ppc : 1; // 端口电源控制 83 unsigned int pind : 1; // port indicators 84 unsigned int lhrc : 1; // Light HC reset capability 85 unsigned int ltc : 1; // latency tolerance messaging capability 86 unsigned int nss : 1; // no secondary SID support 87 88 unsigned int pae : 1; // parse all event data 89 unsigned int spc : 1; // Stopped - Short packet capability 90 unsigned int sec : 1; // Stopped EDTLA capability 91 unsigned int cfc : 1; // Continuous Frame ID capability 92 unsigned int MaxPSASize : 4; // Max Primary Stream Array Size 93 94 uint16_t xECP; // xhci extended capabilities pointer 95 96 } __attribute__((packed)); 97 98 struct xhci_caps_HCCPARAMS2_reg_t 99 { 100 unsigned u3c : 1; // U3 Entry Capability 101 unsigned cmc : 1; // ConfigEP command Max exit latency too large 102 unsigned fsc : 1; // Force Save Context Capability 103 unsigned ctc : 1; // Compliance Transition Capability 104 unsigned lec : 1; // large ESIT payload capability 105 unsigned cic : 1; // configuration information capability 106 unsigned Reserved : 26; 107 } __attribute__((packed)); 108 // ======== Capability Register Set END ============ 109 110 // ======== Operational Register Set BEGIN ========= 111 112 // xhci operational registers offset 113 #define XHCI_OPS_USBCMD 0x00 // USB Command 114 #define XHCI_OPS_USBSTS 0x04 // USB status 115 #define XHCI_OPS_PAGESIZE 0x08 // Page size 116 #define XHCI_OPS_DNCTRL 0x14 // Device notification control 117 #define XHCI_OPS_CRCR 0x18 // Command ring control 118 #define XHCI_OPS_DCBAAP 0x30 // Device context base address array pointer 119 #define XHCI_OPS_CONFIG 0x38 // configuire 120 #define XHCI_OPS_PRS 0x400 // Port register sets 121 122 struct xhci_ops_usbcmd_reg_t 123 { 124 unsigned rs : 1; // Run/Stop 125 unsigned hcrst : 1; // host controller reset 126 unsigned inte : 1; // Interrupt enable 127 unsigned hsee : 1; // Host system error enable 128 unsigned rsvd_psvd1 : 3; // Reserved and preserved 129 unsigned lhcrst : 1; // light host controller reset 130 unsigned css : 1; // controller save state 131 unsigned crs : 1; // controller restore state 132 unsigned ewe : 1; // enable wrap event 133 unsigned ue3s : 1; // enable U3 MFINDEX Stop 134 unsigned spe : 1; // stopped short packet enable 135 unsigned cme : 1; // CEM Enable 136 unsigned rsvd_psvd2 : 18; // Reserved and preserved 137 } __attribute__((packed)); 138 139 struct xhci_ops_usbsts_reg_t 140 { 141 unsigned HCHalted : 1; 142 unsigned rsvd_psvd1 : 1; // Reserved and preserved 143 unsigned hse : 1; // Host system error 144 unsigned eint : 1; // event interrupt 145 unsigned pcd : 1; // Port change detected 146 unsigned rsvd_zerod : 3; // Reserved and Zero'd 147 unsigned sss : 1; // Save State Status 148 unsigned rss : 1; // restore state status 149 unsigned sre : 1; // save/restore error 150 unsigned cnr : 1; // controller not ready 151 unsigned hce : 1; // host controller error 152 unsigned rsvd_psvd2 : 19; // Reserved and Preserved 153 } __attribute__((packed)); 154 155 struct xhci_ops_pagesize_reg_t 156 { 157 uint16_t page_size; // The actual pagesize is ((this field)<<12) 158 uint16_t reserved; 159 } __attribute__((packed)); 160 161 struct xhci_ops_dnctrl_reg_t 162 { 163 uint16_t value; 164 uint16_t reserved; 165 } __attribute__((packed)); 166 167 struct xhci_ops_config_reg_t 168 { 169 uint8_t MaxSlotsEn; // Max slots enabled 170 unsigned u3e : 1; // U3 Entry Enable 171 unsigned cie : 1; // Configuration information enable 172 unsigned rsvd_psvd : 22; // Reserved and Preserved 173 } __attribute__((packed)); 174 175 // ======== Operational Register Set END ========= 176 // ========= TRB begin =========== 177 178 // TRB的Transfer Type可用值定义 179 #define XHCI_TRB_TRT_NO_DATA 0 180 #define XHCI_TRB_TRT_RESERVED 1 181 #define XHCI_TRB_TRT_OUT_DATA 2 182 #define XHCI_TRB_TRT_IN_DATA 3 183 184 #define XHCI_CMND_RING_TRBS 128 // TRB num of command ring, not more than 4096 185 186 #define XHCI_TRBS_PER_RING 256 187 188 #define XHCI_TRB_CYCLE_OFF 0 189 #define XHCI_TRB_CYCLE_ON 1 190 191 // 获取、设置trb中的status部分的complete code 192 #define xhci_get_comp_code(status) (((status) >> 24) & 0x7f) 193 #define xhci_set_comp_code(code) ((code & 0x7f) << 24) 194 195 /** 196 * @brief xhci通用TRB结构 197 * 198 */ 199 struct xhci_TRB_t 200 { 201 uint64_t param; // 参数 202 uint32_t status; 203 uint32_t command; 204 } __attribute__((packed)); 205 struct xhci_TRB_normal_t 206 { 207 uint64_t buf_paddr; // 数据缓冲区物理地址 208 209 unsigned transfer_length : 17; // 传输数据长度 210 unsigned TD_size : 5; // 传输描述符中剩余的数据包的数量 211 unsigned intr_target : 10; // 中断目标 [0:MaxIntrs-1] 212 213 unsigned cycle : 1; // used to mark the enqueue pointer of transfer ring 214 unsigned ent : 1; // evaluate next TRB before updating the endpoint's state 215 unsigned isp : 1; // Interrupt on short packet bit 216 unsigned ns : 1; // No snoop 217 unsigned chain : 1; // The chain bit is used to tell the controller that this 218 // TRB is associated with the next TRB in the TD 219 unsigned ioc : 1; // 完成时发起中断 220 unsigned idt : 1; // Immediate Data 221 unsigned resv : 2; // Reserved and zero'd 222 unsigned bei : 1; // Block event interrupt 223 unsigned TRB_type : 6; // TRB类型 224 uint16_t Reserved; // 保留且置为0 225 } __attribute__((packed)); 226 227 struct xhci_TRB_setup_stage_t 228 { 229 uint8_t bmRequestType; 230 uint8_t bRequest; 231 uint16_t wValue; 232 233 uint16_t wIndex; 234 uint16_t wLength; 235 236 unsigned transfer_legth : 17; // TRB transfer length 237 unsigned resv1 : 5; // Reserved and zero'd 238 unsigned intr_target : 10; 239 240 unsigned cycle : 1; 241 unsigned resv2 : 4; // Reserved and zero'd 242 unsigned ioc : 1; // interrupt on complete 243 unsigned idt : 1; // immediate data (should always set for setup TRB) 244 unsigned resv3 : 3; // Reserved and zero'd 245 unsigned TRB_type : 6; 246 unsigned trt : 2; // Transfer type 247 unsigned resv4 : 14; // Reserved and zero'd 248 249 } __attribute__((packed)); 250 251 struct xhci_TRB_data_stage_t 252 { 253 uint64_t buf_paddr; // 数据缓冲区物理地址 254 255 unsigned transfer_length : 17; // 传输数据长度 256 unsigned TD_size : 5; // 传输描述符中剩余的数据包的数量 257 unsigned intr_target : 10; // 中断目标 [0:MaxIntrs-1] 258 259 unsigned cycle : 1; // used to mark the enqueue pointer of transfer ring 260 unsigned ent : 1; // evaluate next TRB before updating the endpoint's state 261 unsigned isp : 1; // Interrupt on short packet bit 262 unsigned ns : 1; // No snoop 263 unsigned chain : 1; // The chain bit is used to tell the controller that this 264 // TRB is associated with the next TRB in the TD 265 unsigned ioc : 1; // 完成时发起中断 266 unsigned idt : 1; // Immediate Data 267 unsigned resv : 3; // Reserved and zero'd 268 unsigned TRB_type : 6; // TRB类型 269 unsigned dir : 1; // 0 -> out packet 270 // 1 -> in packet 271 unsigned Reserved : 15; // 保留且置为0 272 } __attribute__((packed)); 273 274 struct xhci_TRB_status_stage_t 275 { 276 uint64_t resv1; // Reserved and zero'd 277 278 unsigned resv2 : 22; // Reserved and zero'd 279 unsigned intr_target : 10; // 中断目标 [0:MaxIntrs-1] 280 281 unsigned cycle : 1; // used to mark the enqueue pointer of transfer ring 282 unsigned ent : 1; // evaluate next TRB before updating the endpoint's state 283 unsigned resv3 : 2; // Reserved and zero'd 284 unsigned chain : 1; // The chain bit is used to tell the controller that this 285 // TRB is associated with the next TRB in the TD 286 unsigned ioc : 1; // 完成时发起中断 287 unsigned resv4 : 4; // Reserved and zero'd 288 unsigned TRB_type : 6; // TRB类型 289 unsigned dir : 1; // 0 -> out packet 290 // 1 -> in packet 291 unsigned Reserved : 15; // 保留且置为0 292 } __attribute__((packed)); 293 294 struct xhci_TRB_cmd_complete_t 295 { 296 uint64_t cmd_trb_pointer_paddr; // 指向生成当前Event TRB的TRB的物理地址（16bytes对齐） 297 298 unsigned resv1 : 24; // Reserved and zero'd 299 uint8_t code; // Completion code 300 301 unsigned cycle : 1; // cycle bit 302 unsigned resv2 : 9; // Reserved and zero'd 303 unsigned TRB_type : 6; // TRB类型 304 uint8_t VF_ID; 305 uint8_t slot_id; // the id of the slot associated with the 306 // command that generated the event 307 } __attribute__((packed)); 308 // ========= TRB end =========== 309 310 // ======== Runtime Register Set Begin ========= 311 312 #define XHCI_RT_IR0 0x20 // 中断寄存器组0距离runtime Register set起始位置的偏移量 313 #define XHCI_IR_SIZE 32 // 中断寄存器组大小 314 315 // 中断寄存器组内的偏移量 316 #define XHCI_IR_MAN 0x00 // Interrupter Management Register 317 #define XHCI_IR_MOD 0x04 // Interrupter Moderation 318 #define XHCI_IR_TABLE_SIZE 0x08 // Event Ring Segment Table size (count of segments) 319 #define XHCI_IR_TABLE_ADDR 0x10 // Event Ring Segment Table Base Address 320 #define XHCI_IR_DEQUEUE 0x18 // Event Ring Dequeue Pointer 321 322 // MAN寄存器内的bit的含义 323 #define XHCI_IR_IMR_PENDING (1 << 0) // Interrupt pending bit in Management Register 324 #define XHCI_IR_IMR_ENABLE (1 << 1) // Interrupt enable bit in Management Register 325 326 struct xhci_intr_moderation_t 327 { 328 uint16_t interval; // 产生一个中断的时间，是interval*250ns (wait before next interrupt) 329 uint16_t counter; 330 } __attribute__((packed)); 331 // ======== Runtime Register Set END ========= 332 333 // ======= xhci Extended Capabilities List BEGIN======== 334 335 // ID 部分的含义定义 336 #define XHCI_XECP_ID_RESERVED 0 337 #define XHCI_XECP_ID_LEGACY 1 // USB Legacy Support 338 #define XHCI_XECP_ID_PROTOCOL 2 // Supported protocol 339 #define XHCI_XECP_ID_POWER 3 // Extended power management 340 #define XHCI_XECP_ID_IOVIRT 4 // I/0 virtualization 341 #define XHCI_XECP_ID_MSG 5 // Message interrupt 342 #define XHCI_XECP_ID_LOCAL_MEM 6 // local memory 343 #define XHCI_XECP_ID_DEBUG 10 // USB Debug capability 344 #define XHCI_XECP_ID_EXTMSG 17 // Extended message interrupt 345 346 #define XHCI_XECP_LEGACY_TIMEOUT 10 // 设置legacy状态的等待时间 347 #define XHCI_XECP_LEGACY_BIOS_OWNED (1 << 16) // 当bios控制着该hc时，该位被置位 348 #define XHCI_XECP_LEGACY_OS_OWNED (1 << 24) // 当系统控制着该hc时，该位被置位 349 #define XHCI_XECP_LEGACY_OWNING_MASK (XHCI_XECP_LEGACY_BIOS_OWNED | XHCI_XECP_LEGACY_OS_OWNED) 350 351 // ======= xhci Extended Capabilities List END ======== 352 353 // ======= Port status and control registers BEGIN ==== 354 #define XHCI_PORT_PORTSC 0x00 // Port status and control 355 #define XHCI_PORT_PORTPMSC 0x04 // Port power management status and control 356 #define XHCI_PORT_PORTLI 0x08 // Port Link info 357 #define XHCI_PORT_PORTHLMPC 0x0c // Port hardware LPM control (version 1.10 only 358 359 #define XHCI_PORTUSB_CHANGE_BITS ((1 << 17) | (1 << 18) | (1 << 20) | (1 << 21) | (1 << 22)) 360 361 // 存储于portsc中的端口速度的可用值 362 #define XHCI_PORT_SPEED_FULL 1 363 #define XHCI_PORT_SPEED_LOW 2 364 #define XHCI_PORT_SPEED_HI 3 365 #define XHCI_PORT_SPEED_SUPER 4 366 367 // ======= Port status and control registers END ==== 368 369 // ======= Device Slot Context BEGIN ==== 370 371 /** 372 * @brief 设备上下文结构体 373 * 374 */ 375 struct xhci_slot_context_t 376 { 377 unsigned route_string : 20; 378 unsigned speed : 4; 379 unsigned Rsvd0 : 1; // Reserved and zero'd 380 unsigned mtt : 1; // multi-TT 381 unsigned hub : 1; 382 unsigned entries : 5; // count of context entries 383 384 uint16_t max_exit_latency; 385 uint8_t rh_port_num; // root hub port number 386 uint8_t num_ports; // number of ports 387 388 uint8_t tt_hub_slot_id; 389 uint8_t tt_port_num; 390 unsigned ttt : 2; // TT Think Time 391 unsigned Rsvd2 : 4; 392 unsigned int_target : 10; // Interrupter target 393 394 uint8_t device_address; 395 unsigned Rsvd1 : 19; 396 unsigned slot_state : 5; 397 } __attribute__((packed)); 398 399 #define XHCI_SLOT_STATE_DISABLED_OR_ENABLED 0 400 #define XHCI_SLOT_STATE_DEFAULT 1 401 #define XHCI_SLOT_STATE_ADDRESSED 2 402 #define XHCI_SLOT_STATE_CONFIGURED 3 403 404 // ======= Device Slot Context END ==== 405 406 // ======= Device Endpoint Context BEGIN ==== 407 408 #define XHCI_EP_STATE_DISABLED 0 409 #define XHCI_EP_STATE_RUNNING 1 410 #define XHCI_EP_STATE_HALTED 2 411 #define XHCI_EP_STATE_STOPPED 3 412 #define XHCI_EP_STATE_ERROR 4 413 414 // End Point Doorbell numbers 415 #define XHCI_SLOT_CNTX 0 416 #define XHCI_EP_CONTROL 1 417 #define XHCI_EP1_OUT 2 418 #define XHCI_EP1_IN 3 419 #define XHCI_EP2_OUT 4 420 #define XHCI_EP2_IN 5 421 #define XHCI_EP3_OUT 6 422 #define XHCI_EP3_IN 7 423 #define XHCI_EP4_OUT 8 424 #define XHCI_EP4_IN 9 425 #define XHCI_EP5_OUT 10 426 #define XHCI_EP5_IN 11 427 #define XHCI_EP6_OUT 12 428 #define XHCI_EP6_IN 13 429 #define XHCI_EP7_OUT 14 430 #define XHCI_EP7_IN 15 431 #define XHCI_EP8_OUT 16 432 #define XHCI_EP8_IN 17 433 #define XHCI_EP9_OUT 18 434 #define XHCI_EP9_IN 19 435 #define XHCI_EP10_OUT 20 436 #define XHCI_EP10_IN 21 437 #define XHCI_EP11_OUT 22 438 #define XHCI_EP11_IN 23 439 #define XHCI_EP12_OUT 24 440 #define XHCI_EP12_IN 25 441 #define XHCI_EP13_OUT 26 442 #define XHCI_EP13_IN 27 443 #define XHCI_EP14_OUT 28 444 #define XHCI_EP14_IN 29 445 #define XHCI_EP15_OUT 30 446 #define XHCI_EP15_IN 31 447 448 // xhci 传输方向(用于setup stage TRB) 449 #define XHCI_DIR_NO_DATA 0 450 #define XHCI_DIR_OUT 2 451 #define XHCI_DIR_IN 3 452 453 // xhci传输方向（单个bit的表示） 454 #define XHCI_DIR_OUT_BIT 0 455 #define XHCI_DIR_IN_BIT 1 456 457 /** 458 * @brief xhci 端点上下文结构体 459 * 460 */ 461 struct xhci_ep_context_t 462 { 463 unsigned ep_state : 3; 464 unsigned Rsvd0 : 5; // Reserved and zero'd 465 unsigned mult : 2; // the maximum supported number of bursts within an interval 466 unsigned max_primary_streams : 5; 467 unsigned linear_stream_array : 1; 468 uint8_t interval; 469 uint8_t max_esti_payload_hi; // Max Endpoint Service Time Interval Payload (High 8bit) 470 471 unsigned Rsvd1 : 1; 472 unsigned err_cnt : 2; // error count. 当错误发生时，该位会自减。当减为0时，控制器会把这个端点挂起 473 unsigned ep_type : 3; // endpoint type 474 unsigned Rsvd2 : 1; 475 unsigned hid : 1; // Host Initiate Disable 476 uint8_t max_burst_size; 477 uint16_t max_packet_size; 478 479 uint64_t tr_dequeue_ptr; // 第0bit为dequeue cycle state， 第1~3bit应保留。 480 481 uint16_t average_trb_len; // 平均TRB长度。该部分不应为0 482 uint16_t max_esti_payload_lo; // Max Endpoint Service Time Interval Payload (Low 16bit) 483 } __attribute__((packed)); 484 485 // ======= Device Endpoint Context END ==== 486 487 // 端口信息标志位 488 #define XHCI_PROTOCOL_USB2 0 489 #define XHCI_PROTOCOL_USB3 1 490 #define XHCI_PROTOCOL_INFO (1 << 0) // 1->usb3, 0->usb2 491 #define XHCI_PROTOCOL_HSO (1 << 1) // 1-> usb2 high speed only 492 #define XHCI_PROTOCOL_HAS_PAIR (1 << 2) // 当前位被置位，意味着当前端口具有一个与之配对的端口 493 #define XHCI_PROTOCOL_ACTIVE (1 << 3) // 当前端口是这个配对中，被激活的端口 494 495 struct xhci_ep_info_t 496 { 497 uint64_t ep_ring_vbase; // transfer ring的基地址 498 uint64_t current_ep_ring_vaddr; // transfer ring下一个要写入的地址 499 uint8_t current_ep_ring_cycle; // 当前ep的cycle bit 500 }; 501 502 /** 503 * @brief xhci端口信息 504 * 505 */ 506 struct xhci_port_info_t 507 { 508 uint8_t flags; // port flags 509 uint8_t paired_port_num; // 与当前端口所配对的另一个端口（相同物理接口的不同速度的port） 510 uint8_t offset; // offset of this port within this protocal 511 uint8_t reserved; 512 uint8_t slot_id; // address device获得的slot id 513 struct usb_device_desc *dev_desc; // 指向设备描述符结构体的指针 514 struct xhci_ep_info_t ep_info[32]; // 各个端点的信息 515 } __attribute__((packed)); 516 517 struct xhci_host_controller_t 518 { 519 struct pci_device_structure_general_device_t *pci_dev_hdr; // 指向pci header结构体的指针 520 int controller_id; // 操作系统给controller的编号 521 uint64_t vbase; // 虚拟地址base（bar0映射到的虚拟地址） 522 uint64_t vbase_op; // Operational registers 起始虚拟地址 523 uint32_t rts_offset; // Runtime Register Space offset 524 uint32_t db_offset; // Doorbell offset 525 526 uint32_t ext_caps_off; // 扩展能力寄存器偏移量 527 uint16_t port_num; // 总的端口数量 528 uint8_t context_size; // 设备上下文大小 529 uint8_t port_num_u2; // usb 2.0端口数量 530 531 uint8_t port_num_u3; // usb 3端口数量 532 uint8_t current_event_ring_cycle; // 当前event ring cycle 533 uint8_t cmd_trb_cycle; // 当前command ring cycle 534 uint32_t page_size; // page size 535 536 uint64_t dcbaap_vaddr; // Device Context Base Address Array Pointer的虚拟地址 537 uint64_t cmd_ring_vaddr; // command ring的虚拟地址 538 uint64_t cmd_trb_vaddr; // 下一个要写入的trb的虚拟地址 539 uint64_t event_ring_vaddr; // event ring的虚拟地址 540 uint64_t event_ring_table_vaddr; // event ring table的虚拟地址 541 uint64_t current_event_ring_vaddr; // 下一个要读取的event TRB的虚拟地址 542 uint64_t scratchpad_buf_array_vaddr; // 草稿行缓冲区数组的虚拟地址 543 struct xhci_port_info_t ports[XHCI_MAX_ROOT_HUB_PORTS]; // 指向端口信息数组的指针(由于端口offset是从1开始的，因此该数组第0项为空) 544 }; 545 546 // Common TRB types 547 enum 548 { 549 TRB_TYPE_NORMAL = 1, 550 TRB_TYPE_SETUP_STAGE, 551 TRB_TYPE_DATA_STAGE, 552 TRB_TYPE_STATUS_STAGE, 553 TRB_TYPE_ISOCH, 554 TRB_TYPE_LINK, 555 TRB_TYPE_EVENT_DATA, 556 TRB_TYPE_NO_OP, 557 TRB_TYPE_ENABLE_SLOT, 558 TRB_TYPE_DISABLE_SLOT = 10, 559 560 TRB_TYPE_ADDRESS_DEVICE = 11, 561 TRB_TYPE_CONFIG_EP, 562 TRB_TYPE_EVALUATE_CONTEXT, 563 TRB_TYPE_RESET_EP, 564 TRB_TYPE_STOP_EP = 15, 565 TRB_TYPE_SET_TR_DEQUEUE, 566 TRB_TYPE_RESET_DEVICE, 567 TRB_TYPE_FORCE_EVENT, 568 TRB_TYPE_DEG_BANDWIDTH, 569 TRB_TYPE_SET_LAT_TOLERANCE = 20, 570 571 TRB_TYPE_GET_PORT_BAND = 21, 572 TRB_TYPE_FORCE_HEADER, 573 TRB_TYPE_NO_OP_CMD, // 24 - 31 = reserved 574 575 TRB_TYPE_TRANS_EVENT = 32, 576 TRB_TYPE_COMMAND_COMPLETION, 577 TRB_TYPE_PORT_STATUS_CHANGE, 578 TRB_TYPE_BANDWIDTH_REQUEST, 579 TRB_TYPE_DOORBELL_EVENT, 580 TRB_TYPE_HOST_CONTROLLER_EVENT = 37, 581 TRB_TYPE_DEVICE_NOTIFICATION, 582 TRB_TYPE_MFINDEX_WRAP, 583 // 40 - 47 = reserved 584 // 48 - 63 = Vendor Defined 585 }; 586 587 // event ring trb的完成码 588 enum 589 { 590 TRB_COMP_TRB_SUCCESS = 1, 591 TRB_COMP_DATA_BUFFER_ERROR, 592 TRB_COMP_BABBLE_DETECTION, 593 TRB_COMP_TRANSACTION_ERROR, 594 TRB_COMP_TRB_ERROR, 595 TRB_COMP_STALL_ERROR, 596 TRB_COMP_RESOURCE_ERROR = 7, 597 TRB_COMP_BANDWIDTH_ERROR, 598 TRB_COMP_NO_SLOTS_ERROR, 599 TRB_COMP_INVALID_STREAM_TYPE, 600 TRB_COMP_SLOT_NOT_ENABLED, 601 TRB_COMP_EP_NOT_ENABLED, 602 TRB_COMP_SHORT_PACKET = 13, 603 TRB_COMP_RING_UNDERRUN, 604 TRB_COMP_RUNG_OVERRUN, 605 TRB_COMP_VF_EVENT_RING_FULL, 606 TRB_COMP_PARAMETER_ERROR, 607 TRB_COMP_BANDWITDH_OVERRUN, 608 TRB_COMP_CONTEXT_STATE_ERROR = 19, 609 TRB_COMP_NO_PING_RESPONSE, 610 TRB_COMP_EVENT_RING_FULL, 611 TRB_COMP_INCOMPATIBLE_DEVICE, 612 TRB_COMP_MISSED_SERVICE, 613 TRB_COMP_COMMAND_RING_STOPPED = 24, 614 TRB_COMP_COMMAND_ABORTED, 615 TRB_COMP_STOPPED, 616 TRB_COMP_STOPPER_LENGTH_ERROR, 617 TRB_COMP_RESERVED, 618 TRB_COMP_ISOCH_BUFFER_OVERRUN, 619 TRB_COMP_EVERN_LOST = 32, 620 TRB_COMP_UNDEFINED, 621 TRB_COMP_INVALID_STREAM_ID, 622 TRB_COMP_SECONDARY_BANDWIDTH, 623 TRB_COMP_SPLIT_TRANSACTION 624 /* 37 - 191 reserved */ 625 /* 192 - 223 vender defined errors */ 626 /* 224 - 225 vendor defined info */ 627 }; 628 629 /** 630 * @brief xhci endpoint类型 631 * 632 */ 633 enum 634 { 635 XHCI_EP_TYPE_INVALID = 0, 636 XHCI_EP_TYPE_ISO_OUT, 637 XHCI_EP_TYPE_BULK_OUT, 638 XHCI_EP_TYPE_INTR_OUT, 639 XHCI_EP_TYPE_CONTROL, 640 XHCI_EP_TYPE_ISO_IN, 641 XHCI_EP_TYPE_BULK_IN, 642 XHCI_EP_TYPE_INTR_IN, 643 }; 644 /** 645 * @brief 初始化xhci控制器 646 * 647 * @param header 指定控制器的pci device头部 648 */ 649 void xhci_init(struct pci_device_structure_general_device_t *header);