Searched refs:ports (Results 1 – 3 of 3) sorted by relevance
134 ports: RwLock<Vec<Arc<dyn TtyPort>>>, field155 let mut ports: Vec<Arc<dyn TtyPort>> = Vec::with_capacity(count as usize); in new() localVariable157 ports.push(Arc::new(DefaultTtyPort::new())) in new()174 ports: RwLock::new(ports), in new()320 let ports = self.ports.read(); in init_tty_device() localVariable321 ports[core.index()].setup_internal_tty(Arc::downgrade(&tty)); in init_tty_device()322 tty.set_port(ports[core.index()].clone()); in init_tty_device()
80 let hba_mem_port = &mut hba_mem.ports[j]; in ahci_init()139 let port: &HbaPort = &list[ctrl_num as usize].ports[port_num as usize]; in _port()
84 pub ports: [HbaPort; 32], // 0x100 - 0x10FF, Port control registers field