1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Zoran zr36057/zr36067 PCI controller driver, for the
4 * Pinnacle/Miro DC10/DC10+/DC30/DC30+, Iomega Buz, Linux
5 * Media Labs LML33/LML33R10.
6 *
7 * This part handles device access (PCI/I2C/codec/...)
8 *
9 * Copyright (C) 2000 Serguei Miridonov <mirsev@cicese.mx>
10 */
11
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15
16 #include <linux/interrupt.h>
17 #include <linux/i2c.h>
18 #include <linux/i2c-algo-bit.h>
19 #include <linux/videodev2.h>
20 #include <media/v4l2-common.h>
21 #include <linux/spinlock.h>
22
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/wait.h>
26 #include <linux/dma-mapping.h>
27
28 #include <linux/io.h>
29
30 #include "videocodec.h"
31 #include "zoran.h"
32 #include "zoran_device.h"
33 #include "zoran_card.h"
34
35 #define IRQ_MASK (ZR36057_ISR_GIRQ0 | \
36 ZR36057_ISR_GIRQ1 | \
37 ZR36057_ISR_JPEG_REP_IRQ)
38
39 static bool lml33dpath; /* default = 0
40 * 1 will use digital path in capture
41 * mode instead of analog. It can be
42 * used for picture adjustments using
43 * tool like xawtv while watching image
44 * on TV monitor connected to the output.
45 * However, due to absence of 75 Ohm
46 * load on Bt819 input, there will be
47 * some image imperfections
48 */
49
50 module_param(lml33dpath, bool, 0644);
51 MODULE_PARM_DESC(lml33dpath, "Use digital path capture mode (on LML33 cards)");
52
53 int zr_set_buf(struct zoran *zr);
54 /*
55 * initialize video front end
56 */
zr36057_init_vfe(struct zoran * zr)57 static void zr36057_init_vfe(struct zoran *zr)
58 {
59 u32 reg;
60
61 reg = btread(ZR36057_VFESPFR);
62 reg |= ZR36057_VFESPFR_LITTLE_ENDIAN;
63 reg &= ~ZR36057_VFESPFR_VCLK_POL;
64 reg |= ZR36057_VFESPFR_EXT_FL;
65 reg |= ZR36057_VFESPFR_TOP_FIELD;
66 btwrite(reg, ZR36057_VFESPFR);
67 reg = btread(ZR36057_VDCR);
68 if (pci_pci_problems & PCIPCI_TRITON)
69 // || zr->revision < 1) // Revision 1 has also Triton support
70 reg &= ~ZR36057_VDCR_TRITON;
71 else
72 reg |= ZR36057_VDCR_TRITON;
73 btwrite(reg, ZR36057_VDCR);
74 }
75
76 /*
77 * General Purpose I/O and Guest bus access
78 */
79
80 /*
81 * This is a bit tricky. When a board lacks a GPIO function, the corresponding
82 * GPIO bit number in the card_info structure is set to 0.
83 */
84
GPIO(struct zoran * zr,int bit,unsigned int value)85 void GPIO(struct zoran *zr, int bit, unsigned int value)
86 {
87 u32 reg;
88 u32 mask;
89
90 /* Make sure the bit number is legal
91 * A bit number of -1 (lacking) gives a mask of 0,
92 * making it harmless
93 */
94 mask = (1 << (24 + bit)) & 0xff000000;
95 reg = btread(ZR36057_GPPGCR1) & ~mask;
96 if (value)
97 reg |= mask;
98
99 btwrite(reg, ZR36057_GPPGCR1);
100 udelay(1);
101 }
102
103 /*
104 * Wait til post office is no longer busy
105 */
106
post_office_wait(struct zoran * zr)107 int post_office_wait(struct zoran *zr)
108 {
109 u32 por;
110
111 // while (((por = btread(ZR36057_POR)) & (ZR36057_POR_PO_PEN | ZR36057_POR_PO_TIME)) == ZR36057_POR_PO_PEN) {
112 while ((por = btread(ZR36057_POR)) & ZR36057_POR_PO_PEN) {
113 /* wait for something to happen */
114 /* TODO add timeout */
115 }
116 if ((por & ZR36057_POR_PO_TIME) && !zr->card.gws_not_connected) {
117 /* In LML33/BUZ \GWS line is not connected, so it has always timeout set */
118 pci_info(zr->pci_dev, "pop timeout %08x\n", por);
119 return -1;
120 }
121
122 return 0;
123 }
124
post_office_write(struct zoran * zr,unsigned int guest,unsigned int reg,unsigned int value)125 int post_office_write(struct zoran *zr, unsigned int guest,
126 unsigned int reg, unsigned int value)
127 {
128 u32 por;
129
130 por =
131 ZR36057_POR_PO_DIR | ZR36057_POR_PO_TIME | ((guest & 7) << 20) |
132 ((reg & 7) << 16) | (value & 0xFF);
133 btwrite(por, ZR36057_POR);
134
135 return post_office_wait(zr);
136 }
137
post_office_read(struct zoran * zr,unsigned int guest,unsigned int reg)138 int post_office_read(struct zoran *zr, unsigned int guest, unsigned int reg)
139 {
140 u32 por;
141
142 por = ZR36057_POR_PO_TIME | ((guest & 7) << 20) | ((reg & 7) << 16);
143 btwrite(por, ZR36057_POR);
144 if (post_office_wait(zr) < 0)
145 return -1;
146
147 return btread(ZR36057_POR) & 0xFF;
148 }
149
150 /*
151 * JPEG Codec access
152 */
153
jpeg_codec_sleep(struct zoran * zr,int sleep)154 void jpeg_codec_sleep(struct zoran *zr, int sleep)
155 {
156 GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_SLEEP], !sleep);
157 if (!sleep) {
158 pci_dbg(zr->pci_dev, "%s() - wake GPIO=0x%08x\n", __func__, btread(ZR36057_GPPGCR1));
159 udelay(500);
160 } else {
161 pci_dbg(zr->pci_dev, "%s() - sleep GPIO=0x%08x\n", __func__, btread(ZR36057_GPPGCR1));
162 udelay(2);
163 }
164 }
165
jpeg_codec_reset(struct zoran * zr)166 int jpeg_codec_reset(struct zoran *zr)
167 {
168 /* Take the codec out of sleep */
169 jpeg_codec_sleep(zr, 0);
170
171 if (zr->card.gpcs[GPCS_JPEG_RESET] != 0xff) {
172 post_office_write(zr, zr->card.gpcs[GPCS_JPEG_RESET], 0,
173 0);
174 udelay(2);
175 } else {
176 GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_RESET], 0);
177 udelay(2);
178 GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_RESET], 1);
179 udelay(2);
180 }
181
182 return 0;
183 }
184
185 /*
186 * Set the registers for the size we have specified. Don't bother
187 * trying to understand this without the ZR36057 manual in front of
188 * you [AC].
189 */
zr36057_adjust_vfe(struct zoran * zr,enum zoran_codec_mode mode)190 static void zr36057_adjust_vfe(struct zoran *zr, enum zoran_codec_mode mode)
191 {
192 u32 reg;
193
194 switch (mode) {
195 case BUZ_MODE_MOTION_DECOMPRESS:
196 btand(~ZR36057_VFESPFR_EXT_FL, ZR36057_VFESPFR);
197 reg = btread(ZR36057_VFEHCR);
198 if ((reg & (1 << 10)) && zr->card.type != LML33R10)
199 reg += ((1 << 10) | 1);
200
201 btwrite(reg, ZR36057_VFEHCR);
202 break;
203 case BUZ_MODE_MOTION_COMPRESS:
204 case BUZ_MODE_IDLE:
205 default:
206 if ((zr->norm & V4L2_STD_NTSC) ||
207 (zr->card.type == LML33R10 &&
208 (zr->norm & V4L2_STD_PAL)))
209 btand(~ZR36057_VFESPFR_EXT_FL, ZR36057_VFESPFR);
210 else
211 btor(ZR36057_VFESPFR_EXT_FL, ZR36057_VFESPFR);
212 reg = btread(ZR36057_VFEHCR);
213 if (!(reg & (1 << 10)) && zr->card.type != LML33R10)
214 reg -= ((1 << 10) | 1);
215
216 btwrite(reg, ZR36057_VFEHCR);
217 break;
218 }
219 }
220
221 /*
222 * set geometry
223 */
224
zr36057_set_vfe(struct zoran * zr,int video_width,int video_height,const struct zoran_format * format)225 static void zr36057_set_vfe(struct zoran *zr, int video_width, int video_height,
226 const struct zoran_format *format)
227 {
228 const struct tvnorm *tvn;
229 unsigned int h_start, h_end, v_start, v_end;
230 unsigned int disp_mode;
231 unsigned int vid_win_wid, vid_win_ht;
232 unsigned int hcrop1, hcrop2, vcrop1, vcrop2;
233 unsigned int wa, we, ha, he;
234 unsigned int X, Y, hor_dcm, ver_dcm;
235 u32 reg;
236
237 tvn = zr->timing;
238
239 wa = tvn->wa;
240 ha = tvn->ha;
241
242 pci_dbg(zr->pci_dev, "set_vfe() - width = %d, height = %d\n", video_width, video_height);
243
244 if (video_width < BUZ_MIN_WIDTH ||
245 video_height < BUZ_MIN_HEIGHT ||
246 video_width > wa || video_height > ha) {
247 pci_err(zr->pci_dev, "set_vfe: w=%d h=%d not valid\n", video_width, video_height);
248 return;
249 }
250
251 /**** zr36057 ****/
252
253 /* horizontal */
254 vid_win_wid = video_width;
255 X = DIV_ROUND_UP(vid_win_wid * 64, tvn->wa);
256 we = (vid_win_wid * 64) / X;
257 hor_dcm = 64 - X;
258 hcrop1 = 2 * ((tvn->wa - we) / 4);
259 hcrop2 = tvn->wa - we - hcrop1;
260 h_start = tvn->h_start ? tvn->h_start : 1;
261 /* (Ronald) Original comment:
262 * "| 1 Doesn't have any effect, tested on both a DC10 and a DC10+"
263 * this is false. It inverses chroma values on the LML33R10 (so Cr
264 * suddenly is shown as Cb and reverse, really cool effect if you
265 * want to see blue faces, not useful otherwise). So don't use |1.
266 * However, the DC10 has '0' as h_start, but does need |1, so we
267 * use a dirty check...
268 */
269 h_end = h_start + tvn->wa - 1;
270 h_start += hcrop1;
271 h_end -= hcrop2;
272 reg = ((h_start & ZR36057_VFEHCR_HMASK) << ZR36057_VFEHCR_H_START)
273 | ((h_end & ZR36057_VFEHCR_HMASK) << ZR36057_VFEHCR_H_END);
274 if (zr->card.vfe_pol.hsync_pol)
275 reg |= ZR36057_VFEHCR_HS_POL;
276 btwrite(reg, ZR36057_VFEHCR);
277
278 /* Vertical */
279 disp_mode = !(video_height > BUZ_MAX_HEIGHT / 2);
280 vid_win_ht = disp_mode ? video_height : video_height / 2;
281 Y = DIV_ROUND_UP(vid_win_ht * 64 * 2, tvn->ha);
282 he = (vid_win_ht * 64) / Y;
283 ver_dcm = 64 - Y;
284 vcrop1 = (tvn->ha / 2 - he) / 2;
285 vcrop2 = tvn->ha / 2 - he - vcrop1;
286 v_start = tvn->v_start;
287 v_end = v_start + tvn->ha / 2; // - 1; FIXME SnapShot times out with -1 in 768*576 on the DC10 - LP
288 v_start += vcrop1;
289 v_end -= vcrop2;
290 reg = ((v_start & ZR36057_VFEVCR_VMASK) << ZR36057_VFEVCR_V_START)
291 | ((v_end & ZR36057_VFEVCR_VMASK) << ZR36057_VFEVCR_V_END);
292 if (zr->card.vfe_pol.vsync_pol)
293 reg |= ZR36057_VFEVCR_VS_POL;
294 btwrite(reg, ZR36057_VFEVCR);
295
296 /* scaler and pixel format */
297 reg = 0;
298 reg |= (hor_dcm << ZR36057_VFESPFR_HOR_DCM);
299 reg |= (ver_dcm << ZR36057_VFESPFR_VER_DCM);
300 reg |= (disp_mode << ZR36057_VFESPFR_DISP_MODE);
301 /* RJ: I don't know, why the following has to be the opposite
302 * of the corresponding ZR36060 setting, but only this way
303 * we get the correct colors when uncompressing to the screen */
304 //reg |= ZR36057_VFESPFR_VCLK_POL; /**/
305 /* RJ: Don't know if that is needed for NTSC also */
306 if (!(zr->norm & V4L2_STD_NTSC))
307 reg |= ZR36057_VFESPFR_EXT_FL; // NEEDED!!!!!!! Wolfgang
308 reg |= ZR36057_VFESPFR_TOP_FIELD;
309 if (hor_dcm >= 48)
310 reg |= 3 << ZR36057_VFESPFR_H_FILTER; /* 5 tap filter */
311 else if (hor_dcm >= 32)
312 reg |= 2 << ZR36057_VFESPFR_H_FILTER; /* 4 tap filter */
313 else if (hor_dcm >= 16)
314 reg |= 1 << ZR36057_VFESPFR_H_FILTER; /* 3 tap filter */
315
316 reg |= format->vfespfr;
317 btwrite(reg, ZR36057_VFESPFR);
318
319 /* display configuration */
320 reg = (16 << ZR36057_VDCR_MIN_PIX)
321 | (vid_win_ht << ZR36057_VDCR_VID_WIN_HT)
322 | (vid_win_wid << ZR36057_VDCR_VID_WIN_WID);
323 if (pci_pci_problems & PCIPCI_TRITON)
324 // || zr->revision < 1) // Revision 1 has also Triton support
325 reg &= ~ZR36057_VDCR_TRITON;
326 else
327 reg |= ZR36057_VDCR_TRITON;
328 btwrite(reg, ZR36057_VDCR);
329
330 zr36057_adjust_vfe(zr, zr->codec_mode);
331 }
332
333 /* Enable/Disable uncompressed memory grabbing of the 36057 */
zr36057_set_memgrab(struct zoran * zr,int mode)334 void zr36057_set_memgrab(struct zoran *zr, int mode)
335 {
336 if (mode) {
337 /* We only check SnapShot and not FrameGrab here. SnapShot==1
338 * means a capture is already in progress, but FrameGrab==1
339 * doesn't necessary mean that. It's more correct to say a 1
340 * to 0 transition indicates a capture completed. If a
341 * capture is pending when capturing is tuned off, FrameGrab
342 * will be stuck at 1 until capturing is turned back on.
343 */
344 if (btread(ZR36057_VSSFGR) & ZR36057_VSSFGR_SNAP_SHOT)
345 pci_warn(zr->pci_dev, "zr36057_set_memgrab(1) with SnapShot on!?\n");
346
347 /* switch on VSync interrupts */
348 btwrite(IRQ_MASK, ZR36057_ISR); // Clear Interrupts
349 btor(zr->card.vsync_int, ZR36057_ICR); // SW
350
351 /* enable SnapShot */
352 btor(ZR36057_VSSFGR_SNAP_SHOT, ZR36057_VSSFGR);
353
354 /* Set zr36057 video front end and enable video */
355 zr36057_set_vfe(zr, zr->v4l_settings.width,
356 zr->v4l_settings.height,
357 zr->v4l_settings.format);
358 } else {
359 /* switch off VSync interrupts */
360 btand(~zr->card.vsync_int, ZR36057_ICR); // SW
361
362 /* re-enable grabbing to screen if it was running */
363 btand(~ZR36057_VDCR_VID_EN, ZR36057_VDCR);
364 btand(~ZR36057_VSSFGR_SNAP_SHOT, ZR36057_VSSFGR);
365 }
366 }
367
368 /*****************************************************************************
369 * *
370 * Set up the Buz-specific MJPEG part *
371 * *
372 *****************************************************************************/
373
set_frame(struct zoran * zr,int val)374 static inline void set_frame(struct zoran *zr, int val)
375 {
376 GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_FRAME], val);
377 }
378
set_videobus_dir(struct zoran * zr,int val)379 static void set_videobus_dir(struct zoran *zr, int val)
380 {
381 switch (zr->card.type) {
382 case LML33:
383 case LML33R10:
384 if (!lml33dpath)
385 GPIO(zr, 5, val);
386 else
387 GPIO(zr, 5, 1);
388 break;
389 default:
390 GPIO(zr, zr->card.gpio[ZR_GPIO_VID_DIR],
391 zr->card.gpio_pol[ZR_GPIO_VID_DIR] ? !val : val);
392 break;
393 }
394 }
395
init_jpeg_queue(struct zoran * zr)396 static void init_jpeg_queue(struct zoran *zr)
397 {
398 int i;
399
400 /* re-initialize DMA ring stuff */
401 zr->jpg_que_head = 0;
402 zr->jpg_dma_head = 0;
403 zr->jpg_dma_tail = 0;
404 zr->jpg_que_tail = 0;
405 zr->jpg_seq_num = 0;
406 zr->jpeg_error = 0;
407 zr->num_errors = 0;
408 zr->jpg_err_seq = 0;
409 zr->jpg_err_shift = 0;
410 zr->jpg_queued_num = 0;
411 for (i = 0; i < BUZ_NUM_STAT_COM; i++)
412 zr->stat_com[i] = cpu_to_le32(1); /* mark as unavailable to zr36057 */
413 }
414
zr36057_set_jpg(struct zoran * zr,enum zoran_codec_mode mode)415 static void zr36057_set_jpg(struct zoran *zr, enum zoran_codec_mode mode)
416 {
417 const struct tvnorm *tvn;
418 u32 reg;
419
420 tvn = zr->timing;
421
422 /* assert P_Reset, disable code transfer, deassert Active */
423 btwrite(0, ZR36057_JPC);
424
425 /* MJPEG compression mode */
426 switch (mode) {
427 case BUZ_MODE_MOTION_COMPRESS:
428 default:
429 reg = ZR36057_JMC_MJPG_CMP_MODE;
430 break;
431
432 case BUZ_MODE_MOTION_DECOMPRESS:
433 reg = ZR36057_JMC_MJPG_EXP_MODE;
434 reg |= ZR36057_JMC_SYNC_MSTR;
435 /* RJ: The following is experimental - improves the output to screen */
436 //if(zr->jpg_settings.VFIFO_FB) reg |= ZR36057_JMC_VFIFO_FB; // No, it doesn't. SM
437 break;
438
439 case BUZ_MODE_STILL_COMPRESS:
440 reg = ZR36057_JMC_JPG_CMP_MODE;
441 break;
442
443 case BUZ_MODE_STILL_DECOMPRESS:
444 reg = ZR36057_JMC_JPG_EXP_MODE;
445 break;
446 }
447 reg |= ZR36057_JMC_JPG;
448 if (zr->jpg_settings.field_per_buff == 1)
449 reg |= ZR36057_JMC_FLD_PER_BUFF;
450 btwrite(reg, ZR36057_JMC);
451
452 /* vertical */
453 btor(ZR36057_VFEVCR_VS_POL, ZR36057_VFEVCR);
454 reg = (6 << ZR36057_VSP_VSYNC_SIZE) |
455 (tvn->ht << ZR36057_VSP_FRM_TOT);
456 btwrite(reg, ZR36057_VSP);
457 reg = ((zr->jpg_settings.img_y + tvn->v_start) << ZR36057_FVAP_NAY) |
458 (zr->jpg_settings.img_height << ZR36057_FVAP_PAY);
459 btwrite(reg, ZR36057_FVAP);
460
461 /* horizontal */
462 if (zr->card.vfe_pol.hsync_pol)
463 btor(ZR36057_VFEHCR_HS_POL, ZR36057_VFEHCR);
464 else
465 btand(~ZR36057_VFEHCR_HS_POL, ZR36057_VFEHCR);
466 reg = ((tvn->h_sync_start) << ZR36057_HSP_HSYNC_START) |
467 (tvn->wt << ZR36057_HSP_LINE_TOT);
468 btwrite(reg, ZR36057_HSP);
469 reg = ((zr->jpg_settings.img_x +
470 tvn->h_start + 4) << ZR36057_FHAP_NAX) |
471 (zr->jpg_settings.img_width << ZR36057_FHAP_PAX);
472 btwrite(reg, ZR36057_FHAP);
473
474 /* field process parameters */
475 if (zr->jpg_settings.odd_even)
476 reg = ZR36057_FPP_ODD_EVEN;
477 else
478 reg = 0;
479
480 btwrite(reg, ZR36057_FPP);
481
482 /* Set proper VCLK Polarity, else colors will be wrong during playback */
483 //btor(ZR36057_VFESPFR_VCLK_POL, ZR36057_VFESPFR);
484
485 /* code base address */
486 btwrite(zr->p_sc, ZR36057_JCBA);
487
488 /* FIFO threshold (FIFO is 160. double words) */
489 /* NOTE: decimal values here */
490 switch (mode) {
491 case BUZ_MODE_STILL_COMPRESS:
492 case BUZ_MODE_MOTION_COMPRESS:
493 if (zr->card.type != BUZ)
494 reg = 140;
495 else
496 reg = 60;
497 break;
498
499 case BUZ_MODE_STILL_DECOMPRESS:
500 case BUZ_MODE_MOTION_DECOMPRESS:
501 reg = 20;
502 break;
503
504 default:
505 reg = 80;
506 break;
507 }
508 btwrite(reg, ZR36057_JCFT);
509 zr36057_adjust_vfe(zr, mode);
510 }
511
clear_interrupt_counters(struct zoran * zr)512 void clear_interrupt_counters(struct zoran *zr)
513 {
514 zr->intr_counter_GIRQ1 = 0;
515 zr->intr_counter_GIRQ0 = 0;
516 zr->intr_counter_cod_rep_irq = 0;
517 zr->intr_counter_jpeg_rep_irq = 0;
518 zr->field_counter = 0;
519 zr->irq1_in = 0;
520 zr->irq1_out = 0;
521 zr->jpeg_in = 0;
522 zr->jpeg_out = 0;
523 zr->JPEG_0 = 0;
524 zr->JPEG_1 = 0;
525 zr->end_event_missed = 0;
526 zr->jpeg_missed = 0;
527 zr->jpeg_max_missed = 0;
528 zr->jpeg_min_missed = 0x7fffffff;
529 }
530
count_reset_interrupt(struct zoran * zr)531 static u32 count_reset_interrupt(struct zoran *zr)
532 {
533 u32 isr;
534
535 isr = btread(ZR36057_ISR) & 0x78000000;
536 if (isr) {
537 if (isr & ZR36057_ISR_GIRQ1) {
538 btwrite(ZR36057_ISR_GIRQ1, ZR36057_ISR);
539 zr->intr_counter_GIRQ1++;
540 }
541 if (isr & ZR36057_ISR_GIRQ0) {
542 btwrite(ZR36057_ISR_GIRQ0, ZR36057_ISR);
543 zr->intr_counter_GIRQ0++;
544 }
545 if (isr & ZR36057_ISR_COD_REP_IRQ) {
546 btwrite(ZR36057_ISR_COD_REP_IRQ, ZR36057_ISR);
547 zr->intr_counter_cod_rep_irq++;
548 }
549 if (isr & ZR36057_ISR_JPEG_REP_IRQ) {
550 btwrite(ZR36057_ISR_JPEG_REP_IRQ, ZR36057_ISR);
551 zr->intr_counter_jpeg_rep_irq++;
552 }
553 }
554 return isr;
555 }
556
jpeg_start(struct zoran * zr)557 void jpeg_start(struct zoran *zr)
558 {
559 int reg;
560
561 zr->frame_num = 0;
562
563 /* deassert P_reset, disable code transfer, deassert Active */
564 btwrite(ZR36057_JPC_P_RESET, ZR36057_JPC);
565 /* stop flushing the internal code buffer */
566 btand(~ZR36057_MCTCR_C_FLUSH, ZR36057_MCTCR);
567 /* enable code transfer */
568 btor(ZR36057_JPC_COD_TRNS_EN, ZR36057_JPC);
569
570 /* clear IRQs */
571 btwrite(IRQ_MASK, ZR36057_ISR);
572 /* enable the JPEG IRQs */
573 btwrite(zr->card.jpeg_int | ZR36057_ICR_JPEG_REP_IRQ | ZR36057_ICR_INT_PIN_EN,
574 ZR36057_ICR);
575
576 set_frame(zr, 0); // \FRAME
577
578 /* set the JPEG codec guest ID */
579 reg = (zr->card.gpcs[1] << ZR36057_JCGI_JPE_GUEST_ID) |
580 (0 << ZR36057_JCGI_JPE_GUEST_REG);
581 btwrite(reg, ZR36057_JCGI);
582
583 if (zr->card.video_vfe == CODEC_TYPE_ZR36016 &&
584 zr->card.video_codec == CODEC_TYPE_ZR36050) {
585 /* Enable processing on the ZR36016 */
586 if (zr->vfe)
587 zr36016_write(zr->vfe, 0, 1);
588
589 /* load the address of the GO register in the ZR36050 latch */
590 post_office_write(zr, 0, 0, 0);
591 }
592
593 /* assert Active */
594 btor(ZR36057_JPC_ACTIVE, ZR36057_JPC);
595
596 /* enable the Go generation */
597 btor(ZR36057_JMC_GO_EN, ZR36057_JMC);
598 udelay(30);
599
600 set_frame(zr, 1); // /FRAME
601
602 pci_dbg(zr->pci_dev, "jpeg_start\n");
603 }
604
zr36057_enable_jpg(struct zoran * zr,enum zoran_codec_mode mode)605 void zr36057_enable_jpg(struct zoran *zr, enum zoran_codec_mode mode)
606 {
607 struct vfe_settings cap;
608 int field_size = zr->buffer_size / zr->jpg_settings.field_per_buff;
609
610 zr->codec_mode = mode;
611
612 cap.x = zr->jpg_settings.img_x;
613 cap.y = zr->jpg_settings.img_y;
614 cap.width = zr->jpg_settings.img_width;
615 cap.height = zr->jpg_settings.img_height;
616 cap.decimation =
617 zr->jpg_settings.hor_dcm | (zr->jpg_settings.ver_dcm << 8);
618 cap.quality = zr->jpg_settings.jpg_comp.quality;
619
620 switch (mode) {
621 case BUZ_MODE_MOTION_COMPRESS: {
622 struct jpeg_app_marker app;
623 struct jpeg_com_marker com;
624
625 /* In motion compress mode, the decoder output must be enabled, and
626 * the video bus direction set to input.
627 */
628 set_videobus_dir(zr, 0);
629 decoder_call(zr, video, s_stream, 1);
630 encoder_call(zr, video, s_routing, 0, 0, 0);
631
632 /* Take the JPEG codec and the VFE out of sleep */
633 jpeg_codec_sleep(zr, 0);
634
635 /* set JPEG app/com marker */
636 app.appn = zr->jpg_settings.jpg_comp.APPn;
637 app.len = zr->jpg_settings.jpg_comp.APP_len;
638 memcpy(app.data, zr->jpg_settings.jpg_comp.APP_data, 60);
639 zr->codec->control(zr->codec, CODEC_S_JPEG_APP_DATA,
640 sizeof(struct jpeg_app_marker), &app);
641
642 com.len = zr->jpg_settings.jpg_comp.COM_len;
643 memcpy(com.data, zr->jpg_settings.jpg_comp.COM_data, 60);
644 zr->codec->control(zr->codec, CODEC_S_JPEG_COM_DATA,
645 sizeof(struct jpeg_com_marker), &com);
646
647 /* Setup the JPEG codec */
648 zr->codec->control(zr->codec, CODEC_S_JPEG_TDS_BYTE,
649 sizeof(int), &field_size);
650 zr->codec->set_video(zr->codec, zr->timing, &cap,
651 &zr->card.vfe_pol);
652 zr->codec->set_mode(zr->codec, CODEC_DO_COMPRESSION);
653
654 /* Setup the VFE */
655 if (zr->vfe) {
656 zr->vfe->control(zr->vfe, CODEC_S_JPEG_TDS_BYTE,
657 sizeof(int), &field_size);
658 zr->vfe->set_video(zr->vfe, zr->timing, &cap,
659 &zr->card.vfe_pol);
660 zr->vfe->set_mode(zr->vfe, CODEC_DO_COMPRESSION);
661 }
662
663 init_jpeg_queue(zr);
664 zr36057_set_jpg(zr, mode); // \P_Reset, ... Video param, FIFO
665
666 clear_interrupt_counters(zr);
667 pci_dbg(zr->pci_dev, "enable_jpg(MOTION_COMPRESS)\n");
668 break;
669 }
670
671 case BUZ_MODE_MOTION_DECOMPRESS:
672 /* In motion decompression mode, the decoder output must be disabled, and
673 * the video bus direction set to output.
674 */
675 decoder_call(zr, video, s_stream, 0);
676 set_videobus_dir(zr, 1);
677 encoder_call(zr, video, s_routing, 1, 0, 0);
678
679 /* Take the JPEG codec and the VFE out of sleep */
680 jpeg_codec_sleep(zr, 0);
681 /* Setup the VFE */
682 if (zr->vfe) {
683 zr->vfe->set_video(zr->vfe, zr->timing, &cap,
684 &zr->card.vfe_pol);
685 zr->vfe->set_mode(zr->vfe, CODEC_DO_EXPANSION);
686 }
687 /* Setup the JPEG codec */
688 zr->codec->set_video(zr->codec, zr->timing, &cap,
689 &zr->card.vfe_pol);
690 zr->codec->set_mode(zr->codec, CODEC_DO_EXPANSION);
691
692 init_jpeg_queue(zr);
693 zr36057_set_jpg(zr, mode); // \P_Reset, ... Video param, FIFO
694
695 clear_interrupt_counters(zr);
696 pci_dbg(zr->pci_dev, "enable_jpg(MOTION_DECOMPRESS)\n");
697 break;
698
699 case BUZ_MODE_IDLE:
700 default:
701 /* shut down processing */
702 btand(~(zr->card.jpeg_int | ZR36057_ICR_JPEG_REP_IRQ),
703 ZR36057_ICR);
704 btwrite(zr->card.jpeg_int | ZR36057_ICR_JPEG_REP_IRQ,
705 ZR36057_ISR);
706 btand(~ZR36057_JMC_GO_EN, ZR36057_JMC); // \Go_en
707
708 msleep(50);
709
710 set_videobus_dir(zr, 0);
711 set_frame(zr, 1); // /FRAME
712 btor(ZR36057_MCTCR_C_FLUSH, ZR36057_MCTCR); // /CFlush
713 btwrite(0, ZR36057_JPC); // \P_Reset,\CodTrnsEn,\Active
714 btand(~ZR36057_JMC_VFIFO_FB, ZR36057_JMC);
715 btand(~ZR36057_JMC_SYNC_MSTR, ZR36057_JMC);
716 jpeg_codec_reset(zr);
717 jpeg_codec_sleep(zr, 1);
718 zr36057_adjust_vfe(zr, mode);
719
720 decoder_call(zr, video, s_stream, 1);
721 encoder_call(zr, video, s_routing, 0, 0, 0);
722
723 pci_dbg(zr->pci_dev, "enable_jpg(IDLE)\n");
724 break;
725 }
726 }
727
728 /* when this is called the spinlock must be held */
zoran_feed_stat_com(struct zoran * zr)729 void zoran_feed_stat_com(struct zoran *zr)
730 {
731 /* move frames from pending queue to DMA */
732
733 int i, max_stat_com;
734 struct zr_buffer *buf;
735 struct vb2_v4l2_buffer *vbuf;
736 dma_addr_t phys_addr = 0;
737 unsigned long flags;
738 unsigned long payload;
739
740 max_stat_com =
741 (zr->jpg_settings.tmp_dcm ==
742 1) ? BUZ_NUM_STAT_COM : (BUZ_NUM_STAT_COM >> 1);
743
744 spin_lock_irqsave(&zr->queued_bufs_lock, flags);
745 while ((zr->jpg_dma_head - zr->jpg_dma_tail) < max_stat_com) {
746 buf = list_first_entry_or_null(&zr->queued_bufs, struct zr_buffer, queue);
747 if (!buf) {
748 pci_err(zr->pci_dev, "No buffer available to queue\n");
749 spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
750 return;
751 }
752 list_del(&buf->queue);
753 zr->buf_in_reserve--;
754 vbuf = &buf->vbuf;
755 vbuf->vb2_buf.state = VB2_BUF_STATE_ACTIVE;
756 phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
757 payload = vb2_get_plane_payload(&vbuf->vb2_buf, 0);
758 if (payload == 0)
759 payload = zr->buffer_size;
760 if (zr->jpg_settings.tmp_dcm == 1) {
761 /* fill 1 stat_com entry */
762 i = (zr->jpg_dma_head -
763 zr->jpg_err_shift) & BUZ_MASK_STAT_COM;
764 if (!(zr->stat_com[i] & cpu_to_le32(1)))
765 break;
766 zr->stat_comb[i * 2] = cpu_to_le32(phys_addr);
767 zr->stat_comb[i * 2 + 1] = cpu_to_le32((payload >> 1) | 1);
768 zr->inuse[i] = buf;
769 zr->stat_com[i] = cpu_to_le32(zr->p_scb + i * 2 * 4);
770 } else {
771 /* fill 2 stat_com entries */
772 i = ((zr->jpg_dma_head -
773 zr->jpg_err_shift) & 1) * 2;
774 if (!(zr->stat_com[i] & cpu_to_le32(1)))
775 break;
776 zr->stat_com[i] = cpu_to_le32(zr->p_scb + i * 2 * 4);
777 zr->stat_com[i + 1] = cpu_to_le32(zr->p_scb + i * 2 * 4);
778
779 zr->stat_comb[i * 2] = cpu_to_le32(phys_addr);
780 zr->stat_comb[i * 2 + 1] = cpu_to_le32((payload >> 1) | 1);
781
782 zr->inuse[i] = buf;
783 zr->inuse[i + 1] = NULL;
784 }
785 zr->jpg_dma_head++;
786 }
787 spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
788 if (zr->codec_mode == BUZ_MODE_MOTION_DECOMPRESS)
789 zr->jpg_queued_num++;
790 }
791
792 /* when this is called the spinlock must be held */
zoran_reap_stat_com(struct zoran * zr)793 static void zoran_reap_stat_com(struct zoran *zr)
794 {
795 /* move frames from DMA queue to done queue */
796
797 int i;
798 u32 stat_com;
799 unsigned int seq;
800 unsigned int dif;
801 unsigned long flags;
802 struct zr_buffer *buf;
803 unsigned int size = 0;
804 u32 fcnt;
805
806 /* In motion decompress we don't have a hardware frame counter,
807 * we just count the interrupts here */
808
809 if (zr->codec_mode == BUZ_MODE_MOTION_DECOMPRESS)
810 zr->jpg_seq_num++;
811
812 spin_lock_irqsave(&zr->queued_bufs_lock, flags);
813 while (zr->jpg_dma_tail < zr->jpg_dma_head) {
814 if (zr->jpg_settings.tmp_dcm == 1)
815 i = (zr->jpg_dma_tail - zr->jpg_err_shift) & BUZ_MASK_STAT_COM;
816 else
817 i = ((zr->jpg_dma_tail - zr->jpg_err_shift) & 1) * 2;
818
819 stat_com = le32_to_cpu(zr->stat_com[i]);
820 if ((stat_com & 1) == 0) {
821 spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
822 return;
823 }
824
825 fcnt = (stat_com & GENMASK(31, 24)) >> 24;
826 size = (stat_com & GENMASK(22, 1)) >> 1;
827
828 buf = zr->inuse[i];
829 if (!buf) {
830 spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
831 pci_err(zr->pci_dev, "No buffer at slot %d\n", i);
832 return;
833 }
834 buf->vbuf.vb2_buf.timestamp = ktime_get_ns();
835
836 if (zr->codec_mode == BUZ_MODE_MOTION_COMPRESS) {
837 vb2_set_plane_payload(&buf->vbuf.vb2_buf, 0, size);
838
839 /* update sequence number with the help of the counter in stat_com */
840 seq = (fcnt + zr->jpg_err_seq) & 0xff;
841 dif = (seq - zr->jpg_seq_num) & 0xff;
842 zr->jpg_seq_num += dif;
843 }
844 buf->vbuf.sequence = zr->jpg_settings.tmp_dcm ==
845 2 ? (zr->jpg_seq_num >> 1) : zr->jpg_seq_num;
846 zr->inuse[i] = NULL;
847 if (zr->jpg_settings.tmp_dcm != 1)
848 buf->vbuf.field = zr->jpg_settings.odd_even ?
849 V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM;
850 else
851 buf->vbuf.field = zr->jpg_settings.odd_even ?
852 V4L2_FIELD_SEQ_TB : V4L2_FIELD_SEQ_BT;
853 vb2_buffer_done(&buf->vbuf.vb2_buf, VB2_BUF_STATE_DONE);
854
855 zr->jpg_dma_tail++;
856 }
857 spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
858 }
859
zoran_irq(int irq,void * dev_id)860 irqreturn_t zoran_irq(int irq, void *dev_id)
861 {
862 struct zoran *zr = dev_id;
863 u32 stat, astat;
864
865 stat = count_reset_interrupt(zr);
866 astat = stat & IRQ_MASK;
867 if (astat & zr->card.vsync_int) {
868 if (zr->running == ZORAN_MAP_MODE_RAW) {
869 if ((btread(ZR36057_VSSFGR) & ZR36057_VSSFGR_SNAP_SHOT) == 0)
870 pci_warn(zr->pci_dev, "BuzIRQ with SnapShot off ???\n");
871 if ((btread(ZR36057_VSSFGR) & ZR36057_VSSFGR_FRAME_GRAB) == 0)
872 zr_set_buf(zr);
873 return IRQ_HANDLED;
874 }
875 if (astat & ZR36057_ISR_JPEG_REP_IRQ) {
876 if (zr->codec_mode != BUZ_MODE_MOTION_DECOMPRESS &&
877 zr->codec_mode != BUZ_MODE_MOTION_COMPRESS) {
878 pci_err(zr->pci_dev, "JPG IRQ when not in good mode\n");
879 return IRQ_HANDLED;
880 }
881 zr->frame_num++;
882 zoran_reap_stat_com(zr);
883 zoran_feed_stat_com(zr);
884 return IRQ_HANDLED;
885 }
886 /* unused interrupts */
887 }
888 zr->ghost_int++;
889 return IRQ_HANDLED;
890 }
891
zoran_set_pci_master(struct zoran * zr,int set_master)892 void zoran_set_pci_master(struct zoran *zr, int set_master)
893 {
894 if (set_master) {
895 pci_set_master(zr->pci_dev);
896 } else {
897 u16 command;
898
899 pci_read_config_word(zr->pci_dev, PCI_COMMAND, &command);
900 command &= ~PCI_COMMAND_MASTER;
901 pci_write_config_word(zr->pci_dev, PCI_COMMAND, command);
902 }
903 }
904
zoran_init_hardware(struct zoran * zr)905 void zoran_init_hardware(struct zoran *zr)
906 {
907 /* Enable bus-mastering */
908 zoran_set_pci_master(zr, 1);
909
910 /* Initialize the board */
911 if (zr->card.init)
912 zr->card.init(zr);
913
914 decoder_call(zr, core, init, 0);
915 decoder_call(zr, video, s_std, zr->norm);
916 decoder_call(zr, video, s_routing,
917 zr->card.input[zr->input].muxsel, 0, 0);
918
919 encoder_call(zr, core, init, 0);
920 encoder_call(zr, video, s_std_output, zr->norm);
921 encoder_call(zr, video, s_routing, 0, 0, 0);
922
923 /* toggle JPEG codec sleep to sync PLL */
924 jpeg_codec_sleep(zr, 1);
925 jpeg_codec_sleep(zr, 0);
926
927 /*
928 * set individual interrupt enables (without GIRQ1)
929 * but don't global enable until zoran_open()
930 */
931 zr36057_init_vfe(zr);
932
933 zr36057_enable_jpg(zr, BUZ_MODE_IDLE);
934
935 btwrite(IRQ_MASK, ZR36057_ISR); // Clears interrupts
936 }
937
zr36057_restart(struct zoran * zr)938 void zr36057_restart(struct zoran *zr)
939 {
940 btwrite(0, ZR36057_SPGPPCR);
941 udelay(1000);
942 btor(ZR36057_SPGPPCR_SOFT_RESET, ZR36057_SPGPPCR);
943 udelay(1000);
944
945 /* assert P_Reset */
946 btwrite(0, ZR36057_JPC);
947 /* set up GPIO direction - all output */
948 btwrite(ZR36057_SPGPPCR_SOFT_RESET | 0, ZR36057_SPGPPCR);
949
950 /* set up GPIO pins and guest bus timing */
951 btwrite((0x81 << 24) | 0x8888, ZR36057_GPPGCR1);
952 }
953
954