1 /*
2 *
3 * Copyrigh t(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
4 *
5 * Copyright 2000-2002 MontaVista Software Inc.
6 * Completed implementation.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * Module name: walnut.c
10 *
11 * Description:
12 * Architecture- / platform-specific boot-time initialization code for
13 * IBM PowerPC 4xx based boards. Adapted from original
14 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
15 * <dan@net4x.com>.
16 *
17 * Please read the COPYING file for all license details.
18 */
19 #include <linux/config.h>
20 #include <linux/init.h>
21 #include <linux/smp.h>
22 #include <linux/threads.h>
23 #include <linux/param.h>
24 #include <linux/string.h>
25 #include <linux/blk.h>
26 #include <linux/pci.h>
27 #include <linux/rtc.h>
28
29 #include <asm/system.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/processor.h>
32 #include <asm/machdep.h>
33 #include <asm/page.h>
34 #include <asm/time.h>
35 #include <asm/io.h>
36 #include <asm/todc.h>
37 #include <platforms/ibm_ocp.h>
38
39 #undef DEBUG
40
41 #ifdef DEBUG
42 #define DBG(x...) printk(x)
43 #else
44 #define DBG(x...)
45 #endif
46
47 void *kb_cs;
48 void *kb_data;
49 void *walnut_rtc_base;
50
51 #ifdef CONFIG_PCI
52 /* Some IRQs unique to Walnut.
53 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
54 */
55 int __init
ppc405_map_irq(struct pci_dev * dev,unsigned char idsel,unsigned char pin)56 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
57 {
58 static char pci_irq_table[][4] =
59 /*
60 * PCI IDSEL/INTPIN->INTLINE
61 * A B C D
62 */
63 {
64 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
65 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
66 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
67 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
68 };
69
70 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
71 return PCI_IRQ_TABLE_LOOKUP;
72 };
73 #endif
74
75 void __init
board_setup_arch(void)76 board_setup_arch(void)
77 {
78 #define WALNUT_PS2_BASE 0xF0100000
79 #define WALNUT_FPGA_BASE 0xF0300000
80
81 void *fpga_brdc;
82 unsigned char fpga_brdc_data;
83 void *fpga_enable;
84 void *fpga_polarity;
85 void *fpga_status;
86 void *fpga_trigger;
87
88 kb_data = ioremap(WALNUT_PS2_BASE, 8);
89 if (!kb_data) {
90 printk(KERN_CRIT
91 "walnut_setup_arch() kb_data ioremap failed\n");
92 return;
93 }
94
95 kb_cs = kb_data + 1;
96
97 fpga_status = ioremap(WALNUT_FPGA_BASE, 8);
98 if (!fpga_status) {
99 printk(KERN_CRIT
100 "walnut_setup_arch() fpga_status ioremap failed\n");
101 return;
102 }
103
104 fpga_enable = fpga_status + 1;
105 fpga_polarity = fpga_status + 2;
106 fpga_trigger = fpga_status + 3;
107 fpga_brdc = fpga_status + 4;
108
109 /* split the keyboard and mouse interrupts */
110 fpga_brdc_data = readb(fpga_brdc);
111 fpga_brdc_data |= 0x80;
112 writeb(fpga_brdc_data, fpga_brdc);
113
114 writeb(0x3, fpga_enable);
115
116 writeb(0x3, fpga_polarity);
117
118 writeb(0x3, fpga_trigger);
119
120 /* RTC step for the walnut */
121 walnut_rtc_base = (void *) WALNUT_RTC_VADDR;
122 TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base,
123 walnut_rtc_base, 8);
124 /* Identify the system */
125 printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. (source@mvista.com)\n");
126 }
127
128 #ifdef CONFIG_PCI
129 void __init
bios_fixup(struct pci_controller * hose,struct pcil0_regs * pcip)130 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
131 {
132
133 unsigned int bar_response, bar;
134 /*
135 * Expected PCI mapping:
136 *
137 * PLB addr PCI memory addr
138 * --------------------- ---------------------
139 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
140 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
141 *
142 * PLB addr PCI io addr
143 * --------------------- ---------------------
144 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
145 *
146 * The following code is simplified by assuming that the bootrom
147 * has been well behaved in following this mapping.
148 */
149
150 #ifdef DEBUG
151 int i;
152
153 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
154 printk("PCI bridge regs before fixup \n");
155 for (i = 0; i <= 3; i++) {
156 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
157 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
158 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
159 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
160 }
161 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
162 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
163 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
164 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
165
166 #endif
167
168 /* added for IBM boot rom version 1.15 bios bar changes -AK */
169
170 /* Disable region first */
171 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
172 /* PLB starting addr, PCI: 0x80000000 */
173 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
174 /* PCI start addr, 0x80000000 */
175 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
176 /* 512MB range of PLB to PCI */
177 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
178 /* Enable no pre-fetch, enable region */
179 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
180 (PPC405_PCI_UPPER_MEM -
181 PPC405_PCI_MEM_BASE)) | 0x01));
182
183 /* Disable region one */
184 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
185 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
186 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
187 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
188 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
189 out_le32((void *) &(pcip->ptm1ms), 0x00000000);
190
191 /* Disable region two */
192 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
193 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
194 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
195 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
196 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
197 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
198
199 /* Zero config bars */
200 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
201 early_write_config_dword(hose, hose->first_busno,
202 PCI_FUNC(hose->first_busno), bar,
203 0x00000000);
204 early_read_config_dword(hose, hose->first_busno,
205 PCI_FUNC(hose->first_busno), bar,
206 &bar_response);
207 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
208 hose->first_busno, PCI_SLOT(hose->first_busno),
209 PCI_FUNC(hose->first_busno), bar, bar_response);
210 }
211 /* end work arround */
212
213 #ifdef DEBUG
214 printk("PCI bridge regs after fixup \n");
215 for (i = 0; i <= 3; i++) {
216 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
217 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
218 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
219 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
220 }
221 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
222 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
223 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
224 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
225
226 #endif
227 }
228 #endif
229
230 void __init
board_io_mapping(void)231 board_io_mapping(void)
232 {
233 io_block_mapping(WALNUT_RTC_VADDR,
234 WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO);
235 }
236
237 void __init
board_setup_irq(void)238 board_setup_irq(void)
239 {
240 }
241
242 void __init
board_init(void)243 board_init(void)
244 {
245 ppc_md.time_init = todc_time_init;
246 ppc_md.set_rtc_time = todc_set_rtc_time;
247 ppc_md.get_rtc_time = todc_get_rtc_time;
248 ppc_md.nvram_read_val = todc_direct_read_val;
249 ppc_md.nvram_write_val = todc_direct_write_val;
250 }
251