1 /* 2 * Copyright (C) 2008 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __OMAP_OMAPDSS_H 19 #define __OMAP_OMAPDSS_H 20 21 #include <linux/list.h> 22 #include <linux/kobject.h> 23 #include <linux/device.h> 24 25 #define DISPC_IRQ_FRAMEDONE (1 << 0) 26 #define DISPC_IRQ_VSYNC (1 << 1) 27 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) 28 #define DISPC_IRQ_EVSYNC_ODD (1 << 3) 29 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) 30 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) 31 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) 32 #define DISPC_IRQ_GFX_END_WIN (1 << 7) 33 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) 34 #define DISPC_IRQ_OCP_ERR (1 << 9) 35 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) 36 #define DISPC_IRQ_VID1_END_WIN (1 << 11) 37 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) 38 #define DISPC_IRQ_VID2_END_WIN (1 << 13) 39 #define DISPC_IRQ_SYNC_LOST (1 << 14) 40 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) 41 #define DISPC_IRQ_WAKEUP (1 << 16) 42 #define DISPC_IRQ_SYNC_LOST2 (1 << 17) 43 #define DISPC_IRQ_VSYNC2 (1 << 18) 44 #define DISPC_IRQ_VID3_END_WIN (1 << 19) 45 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) 46 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) 47 #define DISPC_IRQ_FRAMEDONE2 (1 << 22) 48 #define DISPC_IRQ_FRAMEDONEWB (1 << 23) 49 #define DISPC_IRQ_FRAMEDONETV (1 << 24) 50 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) 51 52 struct omap_dss_device; 53 struct omap_overlay_manager; 54 55 enum omap_display_type { 56 OMAP_DISPLAY_TYPE_NONE = 0, 57 OMAP_DISPLAY_TYPE_DPI = 1 << 0, 58 OMAP_DISPLAY_TYPE_DBI = 1 << 1, 59 OMAP_DISPLAY_TYPE_SDI = 1 << 2, 60 OMAP_DISPLAY_TYPE_DSI = 1 << 3, 61 OMAP_DISPLAY_TYPE_VENC = 1 << 4, 62 OMAP_DISPLAY_TYPE_HDMI = 1 << 5, 63 }; 64 65 enum omap_plane { 66 OMAP_DSS_GFX = 0, 67 OMAP_DSS_VIDEO1 = 1, 68 OMAP_DSS_VIDEO2 = 2, 69 OMAP_DSS_VIDEO3 = 3, 70 }; 71 72 enum omap_channel { 73 OMAP_DSS_CHANNEL_LCD = 0, 74 OMAP_DSS_CHANNEL_DIGIT = 1, 75 OMAP_DSS_CHANNEL_LCD2 = 2, 76 }; 77 78 enum omap_color_mode { 79 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ 80 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ 81 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ 82 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ 83 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ 84 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ 85 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ 86 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ 87 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ 88 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ 89 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ 90 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ 91 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ 92 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ 93 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ 94 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */ 95 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */ 96 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */ 97 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ 98 }; 99 100 enum omap_lcd_display_type { 101 OMAP_DSS_LCD_DISPLAY_STN, 102 OMAP_DSS_LCD_DISPLAY_TFT, 103 }; 104 105 enum omap_dss_load_mode { 106 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, 107 OMAP_DSS_LOAD_CLUT_ONLY = 1, 108 OMAP_DSS_LOAD_FRAME_ONLY = 2, 109 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, 110 }; 111 112 enum omap_dss_trans_key_type { 113 OMAP_DSS_COLOR_KEY_GFX_DST = 0, 114 OMAP_DSS_COLOR_KEY_VID_SRC = 1, 115 }; 116 117 enum omap_rfbi_te_mode { 118 OMAP_DSS_RFBI_TE_MODE_1 = 1, 119 OMAP_DSS_RFBI_TE_MODE_2 = 2, 120 }; 121 122 enum omap_panel_config { 123 OMAP_DSS_LCD_IVS = 1<<0, 124 OMAP_DSS_LCD_IHS = 1<<1, 125 OMAP_DSS_LCD_IPC = 1<<2, 126 OMAP_DSS_LCD_IEO = 1<<3, 127 OMAP_DSS_LCD_RF = 1<<4, 128 OMAP_DSS_LCD_ONOFF = 1<<5, 129 130 OMAP_DSS_LCD_TFT = 1<<20, 131 }; 132 133 enum omap_dss_venc_type { 134 OMAP_DSS_VENC_TYPE_COMPOSITE, 135 OMAP_DSS_VENC_TYPE_SVIDEO, 136 }; 137 138 enum omap_dss_dsi_pixel_format { 139 OMAP_DSS_DSI_FMT_RGB888, 140 OMAP_DSS_DSI_FMT_RGB666, 141 OMAP_DSS_DSI_FMT_RGB666_PACKED, 142 OMAP_DSS_DSI_FMT_RGB565, 143 }; 144 145 enum omap_dss_dsi_mode { 146 OMAP_DSS_DSI_CMD_MODE = 0, 147 OMAP_DSS_DSI_VIDEO_MODE, 148 }; 149 150 enum omap_display_caps { 151 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, 152 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, 153 }; 154 155 enum omap_dss_display_state { 156 OMAP_DSS_DISPLAY_DISABLED = 0, 157 OMAP_DSS_DISPLAY_ACTIVE, 158 OMAP_DSS_DISPLAY_SUSPENDED, 159 }; 160 161 /* XXX perhaps this should be removed */ 162 enum omap_dss_overlay_managers { 163 OMAP_DSS_OVL_MGR_LCD, 164 OMAP_DSS_OVL_MGR_TV, 165 OMAP_DSS_OVL_MGR_LCD2, 166 }; 167 168 enum omap_dss_rotation_type { 169 OMAP_DSS_ROT_DMA = 0, 170 OMAP_DSS_ROT_VRFB = 1, 171 }; 172 173 /* clockwise rotation angle */ 174 enum omap_dss_rotation_angle { 175 OMAP_DSS_ROT_0 = 0, 176 OMAP_DSS_ROT_90 = 1, 177 OMAP_DSS_ROT_180 = 2, 178 OMAP_DSS_ROT_270 = 3, 179 }; 180 181 enum omap_overlay_caps { 182 OMAP_DSS_OVL_CAP_SCALE = 1 << 0, 183 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, 184 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, 185 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, 186 }; 187 188 enum omap_overlay_manager_caps { 189 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ 190 }; 191 192 enum omap_dss_clk_source { 193 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK 194 * OMAP4: DSS_FCLK */ 195 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK 196 * OMAP4: PLL1_CLK1 */ 197 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK 198 * OMAP4: PLL1_CLK2 */ 199 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ 200 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ 201 }; 202 203 enum omap_hdmi_flags { 204 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, 205 }; 206 207 /* RFBI */ 208 209 struct rfbi_timings { 210 int cs_on_time; 211 int cs_off_time; 212 int we_on_time; 213 int we_off_time; 214 int re_on_time; 215 int re_off_time; 216 int we_cycle_time; 217 int re_cycle_time; 218 int cs_pulse_width; 219 int access_time; 220 221 int clk_div; 222 223 u32 tim[5]; /* set by rfbi_convert_timings() */ 224 225 int converted; 226 }; 227 228 void omap_rfbi_write_command(const void *buf, u32 len); 229 void omap_rfbi_read_data(void *buf, u32 len); 230 void omap_rfbi_write_data(const void *buf, u32 len); 231 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, 232 u16 x, u16 y, 233 u16 w, u16 h); 234 int omap_rfbi_enable_te(bool enable, unsigned line); 235 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, 236 unsigned hs_pulse_time, unsigned vs_pulse_time, 237 int hs_pol_inv, int vs_pol_inv, int extif_div); 238 void rfbi_bus_lock(void); 239 void rfbi_bus_unlock(void); 240 241 /* DSI */ 242 243 struct omap_dss_dsi_videomode_data { 244 /* DSI video mode blanking data */ 245 /* Unit: byte clock cycles */ 246 u16 hsa; 247 u16 hfp; 248 u16 hbp; 249 /* Unit: line clocks */ 250 u16 vsa; 251 u16 vfp; 252 u16 vbp; 253 254 /* DSI blanking modes */ 255 int blanking_mode; 256 int hsa_blanking_mode; 257 int hbp_blanking_mode; 258 int hfp_blanking_mode; 259 260 /* Video port sync events */ 261 int vp_de_pol; 262 int vp_hsync_pol; 263 int vp_vsync_pol; 264 bool vp_vsync_end; 265 bool vp_hsync_end; 266 267 bool ddr_clk_always_on; 268 int window_sync; 269 }; 270 271 void dsi_bus_lock(struct omap_dss_device *dssdev); 272 void dsi_bus_unlock(struct omap_dss_device *dssdev); 273 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, 274 int len); 275 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, 276 int len); 277 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd); 278 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel); 279 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 280 u8 param); 281 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, 282 u8 param); 283 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, 284 u8 param1, u8 param2); 285 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 286 u8 *data, int len); 287 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, 288 u8 *data, int len); 289 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 290 u8 *buf, int buflen); 291 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, 292 int buflen); 293 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, 294 u8 *buf, int buflen); 295 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, 296 u8 param1, u8 param2, u8 *buf, int buflen); 297 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 298 u16 len); 299 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); 300 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel); 301 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel); 302 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel); 303 304 /* Board specific data */ 305 struct omap_dss_board_info { 306 int (*get_context_loss_count)(struct device *dev); 307 int num_devices; 308 struct omap_dss_device **devices; 309 struct omap_dss_device *default_device; 310 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask); 311 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask); 312 }; 313 314 /* Init with the board info */ 315 extern int omap_display_init(struct omap_dss_board_info *board_data); 316 /* HDMI mux init*/ 317 extern int omap_hdmi_init(enum omap_hdmi_flags flags); 318 319 struct omap_display_platform_data { 320 struct omap_dss_board_info *board_data; 321 /* TODO: Additional members to be added when PM is considered */ 322 }; 323 324 struct omap_video_timings { 325 /* Unit: pixels */ 326 u16 x_res; 327 /* Unit: pixels */ 328 u16 y_res; 329 /* Unit: KHz */ 330 u32 pixel_clock; 331 /* Unit: pixel clocks */ 332 u16 hsw; /* Horizontal synchronization pulse width */ 333 /* Unit: pixel clocks */ 334 u16 hfp; /* Horizontal front porch */ 335 /* Unit: pixel clocks */ 336 u16 hbp; /* Horizontal back porch */ 337 /* Unit: line clocks */ 338 u16 vsw; /* Vertical synchronization pulse width */ 339 /* Unit: line clocks */ 340 u16 vfp; /* Vertical front porch */ 341 /* Unit: line clocks */ 342 u16 vbp; /* Vertical back porch */ 343 }; 344 345 #ifdef CONFIG_OMAP2_DSS_VENC 346 /* Hardcoded timings for tv modes. Venc only uses these to 347 * identify the mode, and does not actually use the configs 348 * itself. However, the configs should be something that 349 * a normal monitor can also show */ 350 extern const struct omap_video_timings omap_dss_pal_timings; 351 extern const struct omap_video_timings omap_dss_ntsc_timings; 352 #endif 353 354 struct omap_dss_cpr_coefs { 355 s16 rr, rg, rb; 356 s16 gr, gg, gb; 357 s16 br, bg, bb; 358 }; 359 360 struct omap_overlay_info { 361 u32 paddr; 362 u32 p_uv_addr; /* for NV12 format */ 363 u16 screen_width; 364 u16 width; 365 u16 height; 366 enum omap_color_mode color_mode; 367 u8 rotation; 368 enum omap_dss_rotation_type rotation_type; 369 bool mirror; 370 371 u16 pos_x; 372 u16 pos_y; 373 u16 out_width; /* if 0, out_width == width */ 374 u16 out_height; /* if 0, out_height == height */ 375 u8 global_alpha; 376 u8 pre_mult_alpha; 377 u8 zorder; 378 }; 379 380 struct omap_overlay { 381 struct kobject kobj; 382 struct list_head list; 383 384 /* static fields */ 385 const char *name; 386 enum omap_plane id; 387 enum omap_color_mode supported_modes; 388 enum omap_overlay_caps caps; 389 390 /* dynamic fields */ 391 struct omap_overlay_manager *manager; 392 393 /* 394 * The following functions do not block: 395 * 396 * is_enabled 397 * set_overlay_info 398 * get_overlay_info 399 * 400 * The rest of the functions may block and cannot be called from 401 * interrupt context 402 */ 403 404 int (*enable)(struct omap_overlay *ovl); 405 int (*disable)(struct omap_overlay *ovl); 406 bool (*is_enabled)(struct omap_overlay *ovl); 407 408 int (*set_manager)(struct omap_overlay *ovl, 409 struct omap_overlay_manager *mgr); 410 int (*unset_manager)(struct omap_overlay *ovl); 411 412 int (*set_overlay_info)(struct omap_overlay *ovl, 413 struct omap_overlay_info *info); 414 void (*get_overlay_info)(struct omap_overlay *ovl, 415 struct omap_overlay_info *info); 416 417 int (*wait_for_go)(struct omap_overlay *ovl); 418 }; 419 420 struct omap_overlay_manager_info { 421 u32 default_color; 422 423 enum omap_dss_trans_key_type trans_key_type; 424 u32 trans_key; 425 bool trans_enabled; 426 427 bool partial_alpha_enabled; 428 429 bool cpr_enable; 430 struct omap_dss_cpr_coefs cpr_coefs; 431 }; 432 433 struct omap_overlay_manager { 434 struct kobject kobj; 435 436 /* static fields */ 437 const char *name; 438 enum omap_channel id; 439 enum omap_overlay_manager_caps caps; 440 struct list_head overlays; 441 enum omap_display_type supported_displays; 442 443 /* dynamic fields */ 444 struct omap_dss_device *device; 445 446 /* 447 * The following functions do not block: 448 * 449 * set_manager_info 450 * get_manager_info 451 * apply 452 * 453 * The rest of the functions may block and cannot be called from 454 * interrupt context 455 */ 456 457 int (*set_device)(struct omap_overlay_manager *mgr, 458 struct omap_dss_device *dssdev); 459 int (*unset_device)(struct omap_overlay_manager *mgr); 460 461 int (*set_manager_info)(struct omap_overlay_manager *mgr, 462 struct omap_overlay_manager_info *info); 463 void (*get_manager_info)(struct omap_overlay_manager *mgr, 464 struct omap_overlay_manager_info *info); 465 466 int (*apply)(struct omap_overlay_manager *mgr); 467 int (*wait_for_go)(struct omap_overlay_manager *mgr); 468 int (*wait_for_vsync)(struct omap_overlay_manager *mgr); 469 }; 470 471 struct omap_dss_device { 472 struct device dev; 473 474 enum omap_display_type type; 475 476 enum omap_channel channel; 477 478 union { 479 struct { 480 u8 data_lines; 481 } dpi; 482 483 struct { 484 u8 channel; 485 u8 data_lines; 486 } rfbi; 487 488 struct { 489 u8 datapairs; 490 } sdi; 491 492 struct { 493 u8 clk_lane; 494 u8 clk_pol; 495 u8 data1_lane; 496 u8 data1_pol; 497 u8 data2_lane; 498 u8 data2_pol; 499 u8 data3_lane; 500 u8 data3_pol; 501 u8 data4_lane; 502 u8 data4_pol; 503 504 int module; 505 506 bool ext_te; 507 u8 ext_te_gpio; 508 } dsi; 509 510 struct { 511 enum omap_dss_venc_type type; 512 bool invert_polarity; 513 } venc; 514 } phy; 515 516 struct { 517 struct { 518 struct { 519 u16 lck_div; 520 u16 pck_div; 521 enum omap_dss_clk_source lcd_clk_src; 522 } channel; 523 524 enum omap_dss_clk_source dispc_fclk_src; 525 } dispc; 526 527 struct { 528 /* regn is one greater than TRM's REGN value */ 529 u16 regn; 530 u16 regm; 531 u16 regm_dispc; 532 u16 regm_dsi; 533 534 u16 lp_clk_div; 535 enum omap_dss_clk_source dsi_fclk_src; 536 } dsi; 537 538 struct { 539 /* regn is one greater than TRM's REGN value */ 540 u16 regn; 541 u16 regm2; 542 } hdmi; 543 } clocks; 544 545 struct { 546 struct omap_video_timings timings; 547 548 int acbi; /* ac-bias pin transitions per interrupt */ 549 /* Unit: line clocks */ 550 int acb; /* ac-bias pin frequency */ 551 552 enum omap_panel_config config; 553 554 enum omap_dss_dsi_pixel_format dsi_pix_fmt; 555 enum omap_dss_dsi_mode dsi_mode; 556 struct omap_dss_dsi_videomode_data dsi_vm_data; 557 } panel; 558 559 struct { 560 u8 pixel_size; 561 struct rfbi_timings rfbi_timings; 562 } ctrl; 563 564 int reset_gpio; 565 566 int max_backlight_level; 567 568 const char *name; 569 570 /* used to match device to driver */ 571 const char *driver_name; 572 573 void *data; 574 575 struct omap_dss_driver *driver; 576 577 /* helper variable for driver suspend/resume */ 578 bool activate_after_resume; 579 580 enum omap_display_caps caps; 581 582 struct omap_overlay_manager *manager; 583 584 enum omap_dss_display_state state; 585 586 /* platform specific */ 587 int (*platform_enable)(struct omap_dss_device *dssdev); 588 void (*platform_disable)(struct omap_dss_device *dssdev); 589 int (*set_backlight)(struct omap_dss_device *dssdev, int level); 590 int (*get_backlight)(struct omap_dss_device *dssdev); 591 }; 592 593 struct omap_dss_hdmi_data 594 { 595 int hpd_gpio; 596 }; 597 598 struct omap_dss_driver { 599 struct device_driver driver; 600 601 int (*probe)(struct omap_dss_device *); 602 void (*remove)(struct omap_dss_device *); 603 604 int (*enable)(struct omap_dss_device *display); 605 void (*disable)(struct omap_dss_device *display); 606 int (*suspend)(struct omap_dss_device *display); 607 int (*resume)(struct omap_dss_device *display); 608 int (*run_test)(struct omap_dss_device *display, int test); 609 610 int (*update)(struct omap_dss_device *dssdev, 611 u16 x, u16 y, u16 w, u16 h); 612 int (*sync)(struct omap_dss_device *dssdev); 613 614 int (*enable_te)(struct omap_dss_device *dssdev, bool enable); 615 int (*get_te)(struct omap_dss_device *dssdev); 616 617 u8 (*get_rotate)(struct omap_dss_device *dssdev); 618 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); 619 620 bool (*get_mirror)(struct omap_dss_device *dssdev); 621 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); 622 623 int (*memory_read)(struct omap_dss_device *dssdev, 624 void *buf, size_t size, 625 u16 x, u16 y, u16 w, u16 h); 626 627 void (*get_resolution)(struct omap_dss_device *dssdev, 628 u16 *xres, u16 *yres); 629 void (*get_dimensions)(struct omap_dss_device *dssdev, 630 u32 *width, u32 *height); 631 int (*get_recommended_bpp)(struct omap_dss_device *dssdev); 632 633 int (*check_timings)(struct omap_dss_device *dssdev, 634 struct omap_video_timings *timings); 635 void (*set_timings)(struct omap_dss_device *dssdev, 636 struct omap_video_timings *timings); 637 void (*get_timings)(struct omap_dss_device *dssdev, 638 struct omap_video_timings *timings); 639 640 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); 641 u32 (*get_wss)(struct omap_dss_device *dssdev); 642 643 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); 644 bool (*detect)(struct omap_dss_device *dssdev); 645 }; 646 647 int omap_dss_register_driver(struct omap_dss_driver *); 648 void omap_dss_unregister_driver(struct omap_dss_driver *); 649 650 void omap_dss_get_device(struct omap_dss_device *dssdev); 651 void omap_dss_put_device(struct omap_dss_device *dssdev); 652 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) 653 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); 654 struct omap_dss_device *omap_dss_find_device(void *data, 655 int (*match)(struct omap_dss_device *dssdev, void *data)); 656 657 int omap_dss_start_device(struct omap_dss_device *dssdev); 658 void omap_dss_stop_device(struct omap_dss_device *dssdev); 659 660 int omap_dss_get_num_overlay_managers(void); 661 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); 662 663 int omap_dss_get_num_overlays(void); 664 struct omap_overlay *omap_dss_get_overlay(int num); 665 666 void omapdss_default_get_resolution(struct omap_dss_device *dssdev, 667 u16 *xres, u16 *yres); 668 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); 669 670 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); 671 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 672 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 673 674 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout); 675 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, 676 unsigned long timeout); 677 678 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) 679 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev) 680 681 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 682 bool enable); 683 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); 684 685 int omap_dsi_update(struct omap_dss_device *dssdev, int channel, 686 void (*callback)(int, void *), void *data); 687 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); 688 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); 689 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); 690 691 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); 692 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, 693 bool disconnect_lanes, bool enter_ulps); 694 695 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev); 696 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev); 697 void dpi_set_timings(struct omap_dss_device *dssdev, 698 struct omap_video_timings *timings); 699 int dpi_check_timings(struct omap_dss_device *dssdev, 700 struct omap_video_timings *timings); 701 702 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev); 703 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev); 704 705 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev); 706 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev); 707 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev, 708 u16 *x, u16 *y, u16 *w, u16 *h); 709 int omap_rfbi_update(struct omap_dss_device *dssdev, 710 u16 x, u16 y, u16 w, u16 h, 711 void (*callback)(void *), void *data); 712 int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size, 713 int data_lines); 714 715 #endif 716