1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) ST-Ericsson SA 2012 4 * 5 * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 6 * for ST-Ericsson. 7 */ 8 9 10 #ifndef UX500_MSP_I2S_H 11 #define UX500_MSP_I2S_H 12 13 #include <linux/platform_device.h> 14 #include <linux/platform_data/asoc-ux500-msp.h> 15 16 #define MSP_INPUT_FREQ_APB 48000000 17 18 /*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono), 19 * 32 bits accesses (stereo). 20 ***/ 21 enum msp_stereo_mode { 22 MSP_MONO, 23 MSP_STEREO 24 }; 25 26 /* Direction (Transmit/Receive mode) */ 27 enum msp_direction { 28 MSP_TX = 1, 29 MSP_RX = 2 30 }; 31 32 /* Transmit and receive configuration register */ 33 #define MSP_BIG_ENDIAN 0x00000000 34 #define MSP_LITTLE_ENDIAN 0x00001000 35 #define MSP_UNEXPECTED_FS_ABORT 0x00000000 36 #define MSP_UNEXPECTED_FS_IGNORE 0x00008000 37 #define MSP_NON_MODE_BIT_MASK 0x00009000 38 39 /* Global configuration register */ 40 #define RX_ENABLE 0x00000001 41 #define RX_FIFO_ENABLE 0x00000002 42 #define RX_SYNC_SRG 0x00000010 43 #define RX_CLK_POL_RISING 0x00000020 44 #define RX_CLK_SEL_SRG 0x00000040 45 #define TX_ENABLE 0x00000100 46 #define TX_FIFO_ENABLE 0x00000200 47 #define TX_SYNC_SRG_PROG 0x00001800 48 #define TX_SYNC_SRG_AUTO 0x00001000 49 #define TX_CLK_POL_RISING 0x00002000 50 #define TX_CLK_SEL_SRG 0x00004000 51 #define TX_EXTRA_DELAY_ENABLE 0x00008000 52 #define SRG_ENABLE 0x00010000 53 #define FRAME_GEN_ENABLE 0x00100000 54 #define SRG_CLK_SEL_APB 0x00000000 55 #define RX_FIFO_SYNC_HI 0x00000000 56 #define TX_FIFO_SYNC_HI 0x00000000 57 #define SPI_CLK_MODE_NORMAL 0x00000000 58 59 #define MSP_FRAME_SIZE_AUTO -1 60 61 #define MSP_DR 0x00 62 #define MSP_GCR 0x04 63 #define MSP_TCF 0x08 64 #define MSP_RCF 0x0c 65 #define MSP_SRG 0x10 66 #define MSP_FLR 0x14 67 #define MSP_DMACR 0x18 68 69 #define MSP_IMSC 0x20 70 #define MSP_RIS 0x24 71 #define MSP_MIS 0x28 72 #define MSP_ICR 0x2c 73 #define MSP_MCR 0x30 74 #define MSP_RCV 0x34 75 #define MSP_RCM 0x38 76 77 #define MSP_TCE0 0x40 78 #define MSP_TCE1 0x44 79 #define MSP_TCE2 0x48 80 #define MSP_TCE3 0x4c 81 82 #define MSP_RCE0 0x60 83 #define MSP_RCE1 0x64 84 #define MSP_RCE2 0x68 85 #define MSP_RCE3 0x6c 86 #define MSP_IODLY 0x70 87 88 #define MSP_ITCR 0x80 89 #define MSP_ITIP 0x84 90 #define MSP_ITOP 0x88 91 #define MSP_TSTDR 0x8c 92 93 #define MSP_PID0 0xfe0 94 #define MSP_PID1 0xfe4 95 #define MSP_PID2 0xfe8 96 #define MSP_PID3 0xfec 97 98 #define MSP_CID0 0xff0 99 #define MSP_CID1 0xff4 100 #define MSP_CID2 0xff8 101 #define MSP_CID3 0xffc 102 103 /* Protocol dependant parameters list */ 104 #define RX_ENABLE_MASK BIT(0) 105 #define RX_FIFO_ENABLE_MASK BIT(1) 106 #define RX_FSYNC_MASK BIT(2) 107 #define DIRECT_COMPANDING_MASK BIT(3) 108 #define RX_SYNC_SEL_MASK BIT(4) 109 #define RX_CLK_POL_MASK BIT(5) 110 #define RX_CLK_SEL_MASK BIT(6) 111 #define LOOPBACK_MASK BIT(7) 112 #define TX_ENABLE_MASK BIT(8) 113 #define TX_FIFO_ENABLE_MASK BIT(9) 114 #define TX_FSYNC_MASK BIT(10) 115 #define TX_MSP_TDR_TSR BIT(11) 116 #define TX_SYNC_SEL_MASK (BIT(12) | BIT(11)) 117 #define TX_CLK_POL_MASK BIT(13) 118 #define TX_CLK_SEL_MASK BIT(14) 119 #define TX_EXTRA_DELAY_MASK BIT(15) 120 #define SRG_ENABLE_MASK BIT(16) 121 #define SRG_CLK_POL_MASK BIT(17) 122 #define SRG_CLK_SEL_MASK (BIT(19) | BIT(18)) 123 #define FRAME_GEN_EN_MASK BIT(20) 124 #define SPI_CLK_MODE_MASK (BIT(22) | BIT(21)) 125 #define SPI_BURST_MODE_MASK BIT(23) 126 127 #define RXEN_SHIFT 0 128 #define RFFEN_SHIFT 1 129 #define RFSPOL_SHIFT 2 130 #define DCM_SHIFT 3 131 #define RFSSEL_SHIFT 4 132 #define RCKPOL_SHIFT 5 133 #define RCKSEL_SHIFT 6 134 #define LBM_SHIFT 7 135 #define TXEN_SHIFT 8 136 #define TFFEN_SHIFT 9 137 #define TFSPOL_SHIFT 10 138 #define TFSSEL_SHIFT 11 139 #define TCKPOL_SHIFT 13 140 #define TCKSEL_SHIFT 14 141 #define TXDDL_SHIFT 15 142 #define SGEN_SHIFT 16 143 #define SCKPOL_SHIFT 17 144 #define SCKSEL_SHIFT 18 145 #define FGEN_SHIFT 20 146 #define SPICKM_SHIFT 21 147 #define TBSWAP_SHIFT 28 148 149 #define RCKPOL_MASK BIT(0) 150 #define TCKPOL_MASK BIT(0) 151 #define SPICKM_MASK (BIT(1) | BIT(0)) 152 #define MSP_RX_CLKPOL_BIT(n) ((n & RCKPOL_MASK) << RCKPOL_SHIFT) 153 #define MSP_TX_CLKPOL_BIT(n) ((n & TCKPOL_MASK) << TCKPOL_SHIFT) 154 155 #define P1ELEN_SHIFT 0 156 #define P1FLEN_SHIFT 3 157 #define DTYP_SHIFT 10 158 #define ENDN_SHIFT 12 159 #define DDLY_SHIFT 13 160 #define FSIG_SHIFT 15 161 #define P2ELEN_SHIFT 16 162 #define P2FLEN_SHIFT 19 163 #define P2SM_SHIFT 26 164 #define P2EN_SHIFT 27 165 #define FSYNC_SHIFT 15 166 167 #define P1ELEN_MASK 0x00000007 168 #define P2ELEN_MASK 0x00070000 169 #define P1FLEN_MASK 0x00000378 170 #define P2FLEN_MASK 0x03780000 171 #define DDLY_MASK 0x00003000 172 #define DTYP_MASK 0x00000600 173 #define P2SM_MASK 0x04000000 174 #define P2EN_MASK 0x08000000 175 #define ENDN_MASK 0x00001000 176 #define TFSPOL_MASK 0x00000400 177 #define TBSWAP_MASK 0x30000000 178 #define COMPANDING_MODE_MASK 0x00000c00 179 #define FSYNC_MASK 0x00008000 180 181 #define MSP_P1_ELEM_LEN_BITS(n) (n & P1ELEN_MASK) 182 #define MSP_P2_ELEM_LEN_BITS(n) (((n) << P2ELEN_SHIFT) & P2ELEN_MASK) 183 #define MSP_P1_FRAME_LEN_BITS(n) (((n) << P1FLEN_SHIFT) & P1FLEN_MASK) 184 #define MSP_P2_FRAME_LEN_BITS(n) (((n) << P2FLEN_SHIFT) & P2FLEN_MASK) 185 #define MSP_DATA_DELAY_BITS(n) (((n) << DDLY_SHIFT) & DDLY_MASK) 186 #define MSP_DATA_TYPE_BITS(n) (((n) << DTYP_SHIFT) & DTYP_MASK) 187 #define MSP_P2_START_MODE_BIT(n) ((n << P2SM_SHIFT) & P2SM_MASK) 188 #define MSP_P2_ENABLE_BIT(n) ((n << P2EN_SHIFT) & P2EN_MASK) 189 #define MSP_SET_ENDIANNES_BIT(n) ((n << ENDN_SHIFT) & ENDN_MASK) 190 #define MSP_FSYNC_POL(n) ((n << TFSPOL_SHIFT) & TFSPOL_MASK) 191 #define MSP_DATA_WORD_SWAP(n) ((n << TBSWAP_SHIFT) & TBSWAP_MASK) 192 #define MSP_SET_COMPANDING_MODE(n) ((n << DTYP_SHIFT) & \ 193 COMPANDING_MODE_MASK) 194 #define MSP_SET_FSYNC_IGNORE(n) ((n << FSYNC_SHIFT) & FSYNC_MASK) 195 196 /* Flag register */ 197 #define RX_BUSY BIT(0) 198 #define RX_FIFO_EMPTY BIT(1) 199 #define RX_FIFO_FULL BIT(2) 200 #define TX_BUSY BIT(3) 201 #define TX_FIFO_EMPTY BIT(4) 202 #define TX_FIFO_FULL BIT(5) 203 204 #define RBUSY_SHIFT 0 205 #define RFE_SHIFT 1 206 #define RFU_SHIFT 2 207 #define TBUSY_SHIFT 3 208 #define TFE_SHIFT 4 209 #define TFU_SHIFT 5 210 211 /* Multichannel control register */ 212 #define RMCEN_SHIFT 0 213 #define RMCSF_SHIFT 1 214 #define RCMPM_SHIFT 3 215 #define TMCEN_SHIFT 5 216 #define TNCSF_SHIFT 6 217 218 /* Sample rate generator register */ 219 #define SCKDIV_SHIFT 0 220 #define FRWID_SHIFT 10 221 #define FRPER_SHIFT 16 222 223 #define SCK_DIV_MASK 0x0000003FF 224 #define FRAME_WIDTH_BITS(n) (((n) << FRWID_SHIFT) & 0x0000FC00) 225 #define FRAME_PERIOD_BITS(n) (((n) << FRPER_SHIFT) & 0x1FFF0000) 226 227 /* DMA controller register */ 228 #define RX_DMA_ENABLE BIT(0) 229 #define TX_DMA_ENABLE BIT(1) 230 231 #define RDMAE_SHIFT 0 232 #define TDMAE_SHIFT 1 233 234 /* Interrupt Register */ 235 #define RX_SERVICE_INT BIT(0) 236 #define RX_OVERRUN_ERROR_INT BIT(1) 237 #define RX_FSYNC_ERR_INT BIT(2) 238 #define RX_FSYNC_INT BIT(3) 239 #define TX_SERVICE_INT BIT(4) 240 #define TX_UNDERRUN_ERR_INT BIT(5) 241 #define TX_FSYNC_ERR_INT BIT(6) 242 #define TX_FSYNC_INT BIT(7) 243 #define ALL_INT 0x000000ff 244 245 /* MSP test control register */ 246 #define MSP_ITCR_ITEN BIT(0) 247 #define MSP_ITCR_TESTFIFO BIT(1) 248 249 #define RMCEN_BIT 0 250 #define RMCSF_BIT 1 251 #define RCMPM_BIT 3 252 #define TMCEN_BIT 5 253 #define TNCSF_BIT 6 254 255 /* Single or dual phase mode */ 256 enum msp_phase_mode { 257 MSP_SINGLE_PHASE, 258 MSP_DUAL_PHASE 259 }; 260 261 /* Frame length */ 262 enum msp_frame_length { 263 MSP_FRAME_LEN_1 = 0, 264 MSP_FRAME_LEN_2 = 1, 265 MSP_FRAME_LEN_4 = 3, 266 MSP_FRAME_LEN_8 = 7, 267 MSP_FRAME_LEN_12 = 11, 268 MSP_FRAME_LEN_16 = 15, 269 MSP_FRAME_LEN_20 = 19, 270 MSP_FRAME_LEN_32 = 31, 271 MSP_FRAME_LEN_48 = 47, 272 MSP_FRAME_LEN_64 = 63 273 }; 274 275 /* Element length */ 276 enum msp_elem_length { 277 MSP_ELEM_LEN_8 = 0, 278 MSP_ELEM_LEN_10 = 1, 279 MSP_ELEM_LEN_12 = 2, 280 MSP_ELEM_LEN_14 = 3, 281 MSP_ELEM_LEN_16 = 4, 282 MSP_ELEM_LEN_20 = 5, 283 MSP_ELEM_LEN_24 = 6, 284 MSP_ELEM_LEN_32 = 7 285 }; 286 287 enum msp_data_xfer_width { 288 MSP_DATA_TRANSFER_WIDTH_BYTE, 289 MSP_DATA_TRANSFER_WIDTH_HALFWORD, 290 MSP_DATA_TRANSFER_WIDTH_WORD 291 }; 292 293 enum msp_frame_sync { 294 MSP_FSYNC_UNIGNORE = 0, 295 MSP_FSYNC_IGNORE = 1, 296 }; 297 298 enum msp_phase2_start_mode { 299 MSP_PHASE2_START_MODE_IMEDIATE, 300 MSP_PHASE2_START_MODE_FSYNC 301 }; 302 303 enum msp_btf { 304 MSP_BTF_MS_BIT_FIRST = 0, 305 MSP_BTF_LS_BIT_FIRST = 1 306 }; 307 308 enum msp_fsync_pol { 309 MSP_FSYNC_POL_ACT_HI = 0, 310 MSP_FSYNC_POL_ACT_LO = 1 311 }; 312 313 /* Data delay (in bit clock cycles) */ 314 enum msp_delay { 315 MSP_DELAY_0 = 0, 316 MSP_DELAY_1 = 1, 317 MSP_DELAY_2 = 2, 318 MSP_DELAY_3 = 3 319 }; 320 321 /* Configurations of clocks (transmit, receive or sample rate generator) */ 322 enum msp_edge { 323 MSP_FALLING_EDGE = 0, 324 MSP_RISING_EDGE = 1, 325 }; 326 327 enum msp_hws { 328 MSP_SWAP_NONE = 0, 329 MSP_SWAP_BYTE_PER_WORD = 1, 330 MSP_SWAP_BYTE_PER_HALF_WORD = 2, 331 MSP_SWAP_HALF_WORD_PER_WORD = 3 332 }; 333 334 enum msp_compress_mode { 335 MSP_COMPRESS_MODE_LINEAR = 0, 336 MSP_COMPRESS_MODE_MU_LAW = 2, 337 MSP_COMPRESS_MODE_A_LAW = 3 338 }; 339 340 enum msp_expand_mode { 341 MSP_EXPAND_MODE_LINEAR = 0, 342 MSP_EXPAND_MODE_LINEAR_SIGNED = 1, 343 MSP_EXPAND_MODE_MU_LAW = 2, 344 MSP_EXPAND_MODE_A_LAW = 3 345 }; 346 347 #define MSP_FRAME_PERIOD_IN_MONO_MODE 256 348 #define MSP_FRAME_PERIOD_IN_STEREO_MODE 32 349 #define MSP_FRAME_WIDTH_IN_STEREO_MODE 16 350 351 enum msp_protocol { 352 MSP_I2S_PROTOCOL, 353 MSP_PCM_PROTOCOL, 354 MSP_PCM_COMPAND_PROTOCOL, 355 MSP_INVALID_PROTOCOL 356 }; 357 358 /* 359 * No of registers to backup during 360 * suspend resume 361 */ 362 #define MAX_MSP_BACKUP_REGS 36 363 364 enum i2s_direction_t { 365 MSP_DIR_TX = 0x01, 366 MSP_DIR_RX = 0x02, 367 }; 368 369 enum msp_data_size { 370 MSP_DATA_BITS_DEFAULT = -1, 371 MSP_DATA_BITS_8 = 0x00, 372 MSP_DATA_BITS_10, 373 MSP_DATA_BITS_12, 374 MSP_DATA_BITS_14, 375 MSP_DATA_BITS_16, 376 MSP_DATA_BITS_20, 377 MSP_DATA_BITS_24, 378 MSP_DATA_BITS_32, 379 }; 380 381 enum msp_state { 382 MSP_STATE_IDLE = 0, 383 MSP_STATE_CONFIGURED = 1, 384 MSP_STATE_RUNNING = 2, 385 }; 386 387 enum msp_rx_comparison_enable_mode { 388 MSP_COMPARISON_DISABLED = 0, 389 MSP_COMPARISON_NONEQUAL_ENABLED = 2, 390 MSP_COMPARISON_EQUAL_ENABLED = 3 391 }; 392 393 struct msp_multichannel_config { 394 bool rx_multichannel_enable; 395 bool tx_multichannel_enable; 396 enum msp_rx_comparison_enable_mode rx_comparison_enable_mode; 397 u8 padding; 398 u32 comparison_value; 399 u32 comparison_mask; 400 u32 rx_channel_0_enable; 401 u32 rx_channel_1_enable; 402 u32 rx_channel_2_enable; 403 u32 rx_channel_3_enable; 404 u32 tx_channel_0_enable; 405 u32 tx_channel_1_enable; 406 u32 tx_channel_2_enable; 407 u32 tx_channel_3_enable; 408 }; 409 410 struct msp_protdesc { 411 u32 rx_phase_mode; 412 u32 tx_phase_mode; 413 u32 rx_phase2_start_mode; 414 u32 tx_phase2_start_mode; 415 u32 rx_byte_order; 416 u32 tx_byte_order; 417 u32 rx_frame_len_1; 418 u32 rx_frame_len_2; 419 u32 tx_frame_len_1; 420 u32 tx_frame_len_2; 421 u32 rx_elem_len_1; 422 u32 rx_elem_len_2; 423 u32 tx_elem_len_1; 424 u32 tx_elem_len_2; 425 u32 rx_data_delay; 426 u32 tx_data_delay; 427 u32 rx_clk_pol; 428 u32 tx_clk_pol; 429 u32 rx_fsync_pol; 430 u32 tx_fsync_pol; 431 u32 rx_half_word_swap; 432 u32 tx_half_word_swap; 433 u32 compression_mode; 434 u32 expansion_mode; 435 u32 frame_sync_ignore; 436 u32 frame_period; 437 u32 frame_width; 438 u32 clocks_per_frame; 439 }; 440 441 struct ux500_msp_config { 442 unsigned int f_inputclk; 443 unsigned int rx_clk_sel; 444 unsigned int tx_clk_sel; 445 unsigned int srg_clk_sel; 446 unsigned int rx_fsync_pol; 447 unsigned int tx_fsync_pol; 448 unsigned int rx_fsync_sel; 449 unsigned int tx_fsync_sel; 450 unsigned int rx_fifo_config; 451 unsigned int tx_fifo_config; 452 unsigned int loopback_enable; 453 unsigned int tx_data_enable; 454 unsigned int default_protdesc; 455 struct msp_protdesc protdesc; 456 int multichannel_configured; 457 struct msp_multichannel_config multichannel_config; 458 unsigned int direction; 459 unsigned int protocol; 460 unsigned int frame_freq; 461 enum msp_data_size data_size; 462 unsigned int def_elem_len; 463 unsigned int iodelay; 464 }; 465 466 struct ux500_msp_dma_params { 467 unsigned int data_size; 468 dma_addr_t tx_rx_addr; 469 struct stedma40_chan_cfg *dma_cfg; 470 }; 471 472 struct ux500_msp { 473 int id; 474 void __iomem *registers; 475 struct device *dev; 476 struct ux500_msp_dma_params playback_dma_data; 477 struct ux500_msp_dma_params capture_dma_data; 478 enum msp_state msp_state; 479 int def_elem_len; 480 unsigned int dir_busy; 481 int loopback_enable; 482 unsigned int f_bitclk; 483 }; 484 485 struct msp_i2s_platform_data; 486 int ux500_msp_i2s_init_msp(struct platform_device *pdev, 487 struct ux500_msp **msp_p, 488 struct msp_i2s_platform_data *platform_data); 489 void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev, 490 struct ux500_msp *msp); 491 int ux500_msp_i2s_open(struct ux500_msp *msp, struct ux500_msp_config *config); 492 int ux500_msp_i2s_close(struct ux500_msp *msp, 493 unsigned int dir); 494 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, 495 int direction); 496 497 #endif 498