1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car Gen3 ULCB board
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2016 Cogent Embedded, Inc.
7 */
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11
12/ {
13	model = "Renesas R-Car Gen3 ULCB board";
14
15	aliases {
16		i2c0 = &i2c0;
17		i2c1 = &i2c1;
18		i2c2 = &i2c2;
19		i2c3 = &i2c3;
20		i2c4 = &i2c4;
21		i2c5 = &i2c5;
22		i2c6 = &i2c6;
23		i2c7 = &i2c_dvfs;
24		serial0 = &scif2;
25		ethernet0 = &avb;
26		mmc0 = &sdhi2;
27		mmc1 = &sdhi0;
28	};
29
30	chosen {
31		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
32		stdout-path = "serial0:115200n8";
33	};
34
35	audio_clkout: audio-clkout {
36		/*
37		 * This is same as <&rcar_sound 0>
38		 * but needed to avoid cs2000/rcar_sound probe dead-lock
39		 */
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		clock-frequency = <12288000>;
43	};
44
45	hdmi0-out {
46		compatible = "hdmi-connector";
47		type = "a";
48
49		port {
50			hdmi0_con: endpoint {
51				remote-endpoint = <&rcar_dw_hdmi0_out>;
52			};
53		};
54	};
55
56	keyboard {
57		compatible = "gpio-keys";
58
59		key-1 {
60			linux,code = <KEY_1>;
61			label = "SW3";
62			wakeup-source;
63			debounce-interval = <20>;
64			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
65		};
66	};
67
68	leds {
69		compatible = "gpio-leds";
70
71		led5 {
72			gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
73		};
74		led6 {
75			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
76		};
77	};
78
79	reg_1p8v: regulator-1p8v {
80		compatible = "regulator-fixed";
81		regulator-name = "fixed-1.8V";
82		regulator-min-microvolt = <1800000>;
83		regulator-max-microvolt = <1800000>;
84		regulator-boot-on;
85		regulator-always-on;
86	};
87
88	reg_3p3v: regulator-3p3v {
89		compatible = "regulator-fixed";
90		regulator-name = "fixed-3.3V";
91		regulator-min-microvolt = <3300000>;
92		regulator-max-microvolt = <3300000>;
93		regulator-boot-on;
94		regulator-always-on;
95	};
96
97	vcc_sdhi0: regulator-vcc-sdhi0 {
98		compatible = "regulator-fixed";
99
100		regulator-name = "SDHI0 Vcc";
101		regulator-min-microvolt = <3300000>;
102		regulator-max-microvolt = <3300000>;
103
104		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
105		enable-active-high;
106	};
107
108	vccq_sdhi0: regulator-vccq-sdhi0 {
109		compatible = "regulator-gpio";
110
111		regulator-name = "SDHI0 VccQ";
112		regulator-min-microvolt = <1800000>;
113		regulator-max-microvolt = <3300000>;
114
115		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
116		gpios-states = <1>;
117		states = <3300000 1>, <1800000 0>;
118	};
119
120	x12_clk: x12 {
121		compatible = "fixed-clock";
122		#clock-cells = <0>;
123		clock-frequency = <24576000>;
124	};
125
126	x23_clk: x23-clock {
127		compatible = "fixed-clock";
128		#clock-cells = <0>;
129		clock-frequency = <25000000>;
130	};
131};
132
133&a57_0 {
134	cpu-supply = <&dvfs>;
135};
136
137&audio_clk_a {
138	clock-frequency = <22579200>;
139};
140
141&avb {
142	pinctrl-0 = <&avb_pins>;
143	pinctrl-names = "default";
144	phy-handle = <&phy0>;
145	tx-internal-delay-ps = <2000>;
146	status = "okay";
147
148	phy0: ethernet-phy@0 {
149		compatible = "ethernet-phy-id0022.1622",
150			     "ethernet-phy-ieee802.3-c22";
151		rxc-skew-ps = <1500>;
152		reg = <0>;
153		interrupt-parent = <&gpio2>;
154		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
155		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
156	};
157};
158
159&du {
160	status = "okay";
161};
162
163&ehci1 {
164	status = "okay";
165};
166
167&extal_clk {
168	clock-frequency = <16666666>;
169};
170
171&extalr_clk {
172	clock-frequency = <32768>;
173};
174
175&hdmi0 {
176	status = "okay";
177
178	ports {
179		port@1 {
180			reg = <1>;
181			rcar_dw_hdmi0_out: endpoint {
182				remote-endpoint = <&hdmi0_con>;
183			};
184		};
185		port@2 {
186			reg = <2>;
187		};
188	};
189};
190
191&i2c2 {
192	pinctrl-0 = <&i2c2_pins>;
193	pinctrl-names = "default";
194
195	status = "okay";
196
197	clock-frequency = <100000>;
198
199	ak4613: codec@10 {
200		compatible = "asahi-kasei,ak4613";
201		reg = <0x10>;
202		clocks = <&rcar_sound 3>;
203
204		asahi-kasei,in1-single-end;
205		asahi-kasei,in2-single-end;
206		asahi-kasei,out1-single-end;
207		asahi-kasei,out2-single-end;
208		asahi-kasei,out3-single-end;
209		asahi-kasei,out4-single-end;
210		asahi-kasei,out5-single-end;
211		asahi-kasei,out6-single-end;
212	};
213
214	cs2000: clk-multiplier@4f {
215		#clock-cells = <0>;
216		compatible = "cirrus,cs2000-cp";
217		reg = <0x4f>;
218		clocks = <&audio_clkout>, <&x12_clk>;
219		clock-names = "clk_in", "ref_clk";
220
221		assigned-clocks = <&cs2000>;
222		assigned-clock-rates = <24576000>; /* 1/1 divide */
223	};
224};
225
226&i2c4 {
227	status = "okay";
228
229	clock-frequency = <400000>;
230
231	versaclock5: clock-generator@6a {
232		compatible = "idt,5p49v5925";
233		reg = <0x6a>;
234		#clock-cells = <1>;
235		clocks = <&x23_clk>;
236		clock-names = "xin";
237	};
238};
239
240&i2c_dvfs {
241	status = "okay";
242
243	clock-frequency = <400000>;
244
245	pmic: pmic@30 {
246		pinctrl-0 = <&irq0_pins>;
247		pinctrl-names = "default";
248
249		compatible = "rohm,bd9571mwv";
250		reg = <0x30>;
251		interrupt-parent = <&intc_ex>;
252		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
253		interrupt-controller;
254		#interrupt-cells = <2>;
255		gpio-controller;
256		#gpio-cells = <2>;
257		rohm,ddr-backup-power = <0xf>;
258		rohm,rstbmode-pulse;
259
260		regulators {
261			dvfs: dvfs {
262				regulator-name = "dvfs";
263				regulator-min-microvolt = <750000>;
264				regulator-max-microvolt = <1030000>;
265				regulator-boot-on;
266				regulator-always-on;
267			};
268		};
269	};
270
271	eeprom@50 {
272		compatible = "rohm,br24t01", "atmel,24c01";
273		reg = <0x50>;
274		pagesize = <8>;
275	};
276};
277
278&ohci1 {
279	status = "okay";
280};
281
282&pfc {
283	pinctrl-0 = <&scif_clk_pins>;
284	pinctrl-names = "default";
285
286	avb_pins: avb {
287		mux {
288			groups = "avb_link", "avb_mdio", "avb_mii";
289			function = "avb";
290		};
291
292		pins_mdio {
293			groups = "avb_mdio";
294			drive-strength = <24>;
295		};
296
297		pins_mii_tx {
298			pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
299			       "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
300			drive-strength = <12>;
301		};
302	};
303
304	i2c2_pins: i2c2 {
305		groups = "i2c2_a";
306		function = "i2c2";
307	};
308
309	irq0_pins: irq0 {
310		groups = "intc_ex_irq0";
311		function = "intc_ex";
312	};
313
314	scif2_pins: scif2 {
315		groups = "scif2_data_a";
316		function = "scif2";
317	};
318
319	scif_clk_pins: scif_clk {
320		groups = "scif_clk_a";
321		function = "scif_clk";
322	};
323
324	sdhi0_pins: sd0 {
325		groups = "sdhi0_data4", "sdhi0_ctrl";
326		function = "sdhi0";
327		power-source = <3300>;
328	};
329
330	sdhi0_pins_uhs: sd0_uhs {
331		groups = "sdhi0_data4", "sdhi0_ctrl";
332		function = "sdhi0";
333		power-source = <1800>;
334	};
335
336	sdhi2_pins: sd2 {
337		groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
338		function = "sdhi2";
339		power-source = <1800>;
340	};
341
342	sound_pins: sound {
343		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
344		function = "ssi";
345	};
346
347	sound_clk_pins: sound-clk {
348		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
349			 "audio_clkout_a", "audio_clkout3_a";
350		function = "audio_clk";
351	};
352
353	usb1_pins: usb1 {
354		groups = "usb1";
355		function = "usb1";
356	};
357};
358
359&rcar_sound {
360	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
361	pinctrl-names = "default";
362
363	/* audio_clkout0/1/2/3 */
364	#clock-cells = <1>;
365	clock-frequency = <12288000 11289600>;
366
367	status = "okay";
368
369	/* update <audio_clk_b> to <cs2000> */
370	clocks = <&cpg CPG_MOD 1005>,
371		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
372		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
373		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
374		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
375		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
376		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
377		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
378		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
379		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
380		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
381		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
382		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
383		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
384		 <&audio_clk_a>, <&cs2000>,
385		 <&audio_clk_c>,
386		 <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
387};
388
389&rpc {
390	/* Left disabled.  To be enabled by firmware when unlocked. */
391
392	flash@0 {
393		compatible = "cypress,hyperflash", "cfi-flash";
394		reg = <0>;
395
396		partitions {
397			compatible = "fixed-partitions";
398			#address-cells = <1>;
399			#size-cells = <1>;
400
401			bootparam@0 {
402				reg = <0x00000000 0x040000>;
403				read-only;
404			};
405			bl2@40000 {
406				reg = <0x00040000 0x140000>;
407				read-only;
408			};
409			cert_header_sa6@180000 {
410				reg = <0x00180000 0x040000>;
411				read-only;
412			};
413			bl31@1c0000 {
414				reg = <0x001c0000 0x040000>;
415				read-only;
416			};
417			tee@200000 {
418				reg = <0x00200000 0x440000>;
419				read-only;
420			};
421			uboot@640000 {
422				reg = <0x00640000 0x100000>;
423				read-only;
424			};
425			dtb@740000 {
426				reg = <0x00740000 0x080000>;
427			};
428			kernel@7c0000 {
429				reg = <0x007c0000 0x1400000>;
430			};
431			user@1bc0000 {
432				reg = <0x01bc0000 0x2440000>;
433			};
434		};
435	};
436};
437
438&rwdt {
439	timeout-sec = <60>;
440	status = "okay";
441};
442
443&scif2 {
444	pinctrl-0 = <&scif2_pins>;
445	pinctrl-names = "default";
446
447	status = "okay";
448};
449
450&scif_clk {
451	clock-frequency = <14745600>;
452};
453
454&sdhi0 {
455	pinctrl-0 = <&sdhi0_pins>;
456	pinctrl-1 = <&sdhi0_pins_uhs>;
457	pinctrl-names = "default", "state_uhs";
458
459	vmmc-supply = <&vcc_sdhi0>;
460	vqmmc-supply = <&vccq_sdhi0>;
461	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
462	bus-width = <4>;
463	sd-uhs-sdr50;
464	sd-uhs-sdr104;
465	status = "okay";
466};
467
468&sdhi2 {
469	/* used for on-board 8bit eMMC */
470	pinctrl-0 = <&sdhi2_pins>;
471	pinctrl-1 = <&sdhi2_pins>;
472	pinctrl-names = "default", "state_uhs";
473
474	vmmc-supply = <&reg_3p3v>;
475	vqmmc-supply = <&reg_1p8v>;
476	bus-width = <8>;
477	mmc-hs200-1_8v;
478	mmc-hs400-1_8v;
479	no-sd;
480	no-sdio;
481	non-removable;
482	full-pwr-cycle-in-suspend;
483	status = "okay";
484};
485
486&ssi1 {
487	shared-pin;
488};
489
490&usb2_phy1 {
491	pinctrl-0 = <&usb1_pins>;
492	pinctrl-names = "default";
493
494	status = "okay";
495};
496
497
498/*
499 * For sound-test.
500 *
501 * We can switch Audio Card for testing
502 *
503 * #include "ulcb-simple-audio-card.dtsi"
504 * #include "ulcb-simple-audio-card-mix+split.dtsi"
505 * #include "ulcb-audio-graph-card.dtsi"
506 * #include "ulcb-audio-graph-card-mix+split.dtsi"
507 * #include "ulcb-audio-graph-card2-mix+split.dtsi"
508 */
509#include "ulcb-audio-graph-card2.dtsi"
510