1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _USR_IDXD_H_ 4 #define _USR_IDXD_H_ 5 6 #ifdef __KERNEL__ 7 #include <linux/types.h> 8 #else 9 #include <stdint.h> 10 #endif 11 12 /* Driver command error status */ 13 enum idxd_scmd_stat { 14 IDXD_SCMD_DEV_ENABLED = 0x80000010, 15 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020, 16 IDXD_SCMD_WQ_ENABLED = 0x80000021, 17 IDXD_SCMD_DEV_DMA_ERR = 0x80020000, 18 IDXD_SCMD_WQ_NO_GRP = 0x80030000, 19 IDXD_SCMD_WQ_NO_NAME = 0x80040000, 20 IDXD_SCMD_WQ_NO_SVM = 0x80050000, 21 IDXD_SCMD_WQ_NO_THRESH = 0x80060000, 22 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000, 23 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000, 24 IDXD_SCMD_PERCPU_ERR = 0x80090000, 25 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000, 26 IDXD_SCMD_CDEV_ERR = 0x800b0000, 27 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000, 28 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000, 29 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, 30 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, 31 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, 32 }; 33 34 #define IDXD_SCMD_SOFTERR_MASK 0x80000000 35 #define IDXD_SCMD_SOFTERR_SHIFT 16 36 37 /* Descriptor flags */ 38 #define IDXD_OP_FLAG_FENCE 0x0001 39 #define IDXD_OP_FLAG_BOF 0x0002 40 #define IDXD_OP_FLAG_CRAV 0x0004 41 #define IDXD_OP_FLAG_RCR 0x0008 42 #define IDXD_OP_FLAG_RCI 0x0010 43 #define IDXD_OP_FLAG_CRSTS 0x0020 44 #define IDXD_OP_FLAG_CR 0x0080 45 #define IDXD_OP_FLAG_CC 0x0100 46 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200 47 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400 48 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800 49 #define IDXD_OP_FLAG_CR_TCS 0x1000 50 #define IDXD_OP_FLAG_STORD 0x2000 51 #define IDXD_OP_FLAG_DRDBK 0x4000 52 #define IDXD_OP_FLAG_DSTS 0x8000 53 54 /* IAX */ 55 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 56 #define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000 57 #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000 58 #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000 59 #define IDXD_OP_FLAG_SRC2_STS 0x100000 60 #define IDXD_OP_FLAG_CRC_RFC3720 0x200000 61 62 /* Opcode */ 63 enum dsa_opcode { 64 DSA_OPCODE_NOOP = 0, 65 DSA_OPCODE_BATCH, 66 DSA_OPCODE_DRAIN, 67 DSA_OPCODE_MEMMOVE, 68 DSA_OPCODE_MEMFILL, 69 DSA_OPCODE_COMPARE, 70 DSA_OPCODE_COMPVAL, 71 DSA_OPCODE_CR_DELTA, 72 DSA_OPCODE_AP_DELTA, 73 DSA_OPCODE_DUALCAST, 74 DSA_OPCODE_CRCGEN = 0x10, 75 DSA_OPCODE_COPY_CRC, 76 DSA_OPCODE_DIF_CHECK, 77 DSA_OPCODE_DIF_INS, 78 DSA_OPCODE_DIF_STRP, 79 DSA_OPCODE_DIF_UPDT, 80 DSA_OPCODE_CFLUSH = 0x20, 81 }; 82 83 enum iax_opcode { 84 IAX_OPCODE_NOOP = 0, 85 IAX_OPCODE_DRAIN = 2, 86 IAX_OPCODE_MEMMOVE, 87 IAX_OPCODE_DECOMPRESS = 0x42, 88 IAX_OPCODE_COMPRESS, 89 IAX_OPCODE_CRC64, 90 IAX_OPCODE_ZERO_DECOMP_32 = 0x48, 91 IAX_OPCODE_ZERO_DECOMP_16, 92 IAX_OPCODE_DECOMP_32 = 0x4c, 93 IAX_OPCODE_DECOMP_16, 94 IAX_OPCODE_SCAN = 0x50, 95 IAX_OPCODE_SET_MEMBER, 96 IAX_OPCODE_EXTRACT, 97 IAX_OPCODE_SELECT, 98 IAX_OPCODE_RLE_BURST, 99 IAX_OPCDE_FIND_UNIQUE, 100 IAX_OPCODE_EXPAND, 101 }; 102 103 /* Completion record status */ 104 enum dsa_completion_status { 105 DSA_COMP_NONE = 0, 106 DSA_COMP_SUCCESS, 107 DSA_COMP_SUCCESS_PRED, 108 DSA_COMP_PAGE_FAULT_NOBOF, 109 DSA_COMP_PAGE_FAULT_IR, 110 DSA_COMP_BATCH_FAIL, 111 DSA_COMP_BATCH_PAGE_FAULT, 112 DSA_COMP_DR_OFFSET_NOINC, 113 DSA_COMP_DR_OFFSET_ERANGE, 114 DSA_COMP_DIF_ERR, 115 DSA_COMP_BAD_OPCODE = 0x10, 116 DSA_COMP_INVALID_FLAGS, 117 DSA_COMP_NOZERO_RESERVE, 118 DSA_COMP_XFER_ERANGE, 119 DSA_COMP_DESC_CNT_ERANGE, 120 DSA_COMP_DR_ERANGE, 121 DSA_COMP_OVERLAP_BUFFERS, 122 DSA_COMP_DCAST_ERR, 123 DSA_COMP_DESCLIST_ALIGN, 124 DSA_COMP_INT_HANDLE_INVAL, 125 DSA_COMP_CRA_XLAT, 126 DSA_COMP_CRA_ALIGN, 127 DSA_COMP_ADDR_ALIGN, 128 DSA_COMP_PRIV_BAD, 129 DSA_COMP_TRAFFIC_CLASS_CONF, 130 DSA_COMP_PFAULT_RDBA, 131 DSA_COMP_HW_ERR1, 132 DSA_COMP_HW_ERR_DRB, 133 DSA_COMP_TRANSLATION_FAIL, 134 }; 135 136 enum iax_completion_status { 137 IAX_COMP_NONE = 0, 138 IAX_COMP_SUCCESS, 139 IAX_COMP_PAGE_FAULT_IR = 0x04, 140 IAX_COMP_ANALYTICS_ERROR = 0x0a, 141 IAX_COMP_OUTBUF_OVERFLOW, 142 IAX_COMP_BAD_OPCODE = 0x10, 143 IAX_COMP_INVALID_FLAGS, 144 IAX_COMP_NOZERO_RESERVE, 145 IAX_COMP_INVALID_SIZE, 146 IAX_COMP_OVERLAP_BUFFERS = 0x16, 147 IAX_COMP_INT_HANDLE_INVAL = 0x19, 148 IAX_COMP_CRA_XLAT, 149 IAX_COMP_CRA_ALIGN, 150 IAX_COMP_ADDR_ALIGN, 151 IAX_COMP_PRIV_BAD, 152 IAX_COMP_TRAFFIC_CLASS_CONF, 153 IAX_COMP_PFAULT_RDBA, 154 IAX_COMP_HW_ERR1, 155 IAX_COMP_HW_ERR_DRB, 156 IAX_COMP_TRANSLATION_FAIL, 157 IAX_COMP_PRS_TIMEOUT, 158 IAX_COMP_WATCHDOG, 159 IAX_COMP_INVALID_COMP_FLAG = 0x30, 160 IAX_COMP_INVALID_FILTER_FLAG, 161 IAX_COMP_INVALID_INPUT_SIZE, 162 IAX_COMP_INVALID_NUM_ELEMS, 163 IAX_COMP_INVALID_SRC1_WIDTH, 164 IAX_COMP_INVALID_INVERT_OUT, 165 }; 166 167 #define DSA_COMP_STATUS_MASK 0x7f 168 #define DSA_COMP_STATUS_WRITE 0x80 169 170 struct dsa_hw_desc { 171 uint32_t pasid:20; 172 uint32_t rsvd:11; 173 uint32_t priv:1; 174 uint32_t flags:24; 175 uint32_t opcode:8; 176 uint64_t completion_addr; 177 union { 178 uint64_t src_addr; 179 uint64_t rdback_addr; 180 uint64_t pattern; 181 uint64_t desc_list_addr; 182 }; 183 union { 184 uint64_t dst_addr; 185 uint64_t rdback_addr2; 186 uint64_t src2_addr; 187 uint64_t comp_pattern; 188 }; 189 union { 190 uint32_t xfer_size; 191 uint32_t desc_count; 192 }; 193 uint16_t int_handle; 194 uint16_t rsvd1; 195 union { 196 uint8_t expected_res; 197 /* create delta record */ 198 struct { 199 uint64_t delta_addr; 200 uint32_t max_delta_size; 201 uint32_t delt_rsvd; 202 uint8_t expected_res_mask; 203 }; 204 uint32_t delta_rec_size; 205 uint64_t dest2; 206 /* CRC */ 207 struct { 208 uint32_t crc_seed; 209 uint32_t crc_rsvd; 210 uint64_t seed_addr; 211 }; 212 /* DIF check or strip */ 213 struct { 214 uint8_t src_dif_flags; 215 uint8_t dif_chk_res; 216 uint8_t dif_chk_flags; 217 uint8_t dif_chk_res2[5]; 218 uint32_t chk_ref_tag_seed; 219 uint16_t chk_app_tag_mask; 220 uint16_t chk_app_tag_seed; 221 }; 222 /* DIF insert */ 223 struct { 224 uint8_t dif_ins_res; 225 uint8_t dest_dif_flag; 226 uint8_t dif_ins_flags; 227 uint8_t dif_ins_res2[13]; 228 uint32_t ins_ref_tag_seed; 229 uint16_t ins_app_tag_mask; 230 uint16_t ins_app_tag_seed; 231 }; 232 /* DIF update */ 233 struct { 234 uint8_t src_upd_flags; 235 uint8_t upd_dest_flags; 236 uint8_t dif_upd_flags; 237 uint8_t dif_upd_res[5]; 238 uint32_t src_ref_tag_seed; 239 uint16_t src_app_tag_mask; 240 uint16_t src_app_tag_seed; 241 uint32_t dest_ref_tag_seed; 242 uint16_t dest_app_tag_mask; 243 uint16_t dest_app_tag_seed; 244 }; 245 246 uint8_t op_specific[24]; 247 }; 248 } __attribute__((packed)); 249 250 struct iax_hw_desc { 251 uint32_t pasid:20; 252 uint32_t rsvd:11; 253 uint32_t priv:1; 254 uint32_t flags:24; 255 uint32_t opcode:8; 256 uint64_t completion_addr; 257 uint64_t src1_addr; 258 uint64_t dst_addr; 259 uint32_t src1_size; 260 uint16_t int_handle; 261 union { 262 uint16_t compr_flags; 263 uint16_t decompr_flags; 264 }; 265 uint64_t src2_addr; 266 uint32_t max_dst_size; 267 uint32_t src2_size; 268 uint32_t filter_flags; 269 uint32_t num_inputs; 270 } __attribute__((packed)); 271 272 struct dsa_raw_desc { 273 uint64_t field[8]; 274 } __attribute__((packed)); 275 276 /* 277 * The status field will be modified by hardware, therefore it should be 278 * volatile and prevent the compiler from optimize the read. 279 */ 280 struct dsa_completion_record { 281 volatile uint8_t status; 282 union { 283 uint8_t result; 284 uint8_t dif_status; 285 }; 286 uint16_t rsvd; 287 uint32_t bytes_completed; 288 uint64_t fault_addr; 289 union { 290 /* common record */ 291 struct { 292 uint32_t invalid_flags:24; 293 uint32_t rsvd2:8; 294 }; 295 296 uint32_t delta_rec_size; 297 uint32_t crc_val; 298 299 /* DIF check & strip */ 300 struct { 301 uint32_t dif_chk_ref_tag; 302 uint16_t dif_chk_app_tag_mask; 303 uint16_t dif_chk_app_tag; 304 }; 305 306 /* DIF insert */ 307 struct { 308 uint64_t dif_ins_res; 309 uint32_t dif_ins_ref_tag; 310 uint16_t dif_ins_app_tag_mask; 311 uint16_t dif_ins_app_tag; 312 }; 313 314 /* DIF update */ 315 struct { 316 uint32_t dif_upd_src_ref_tag; 317 uint16_t dif_upd_src_app_tag_mask; 318 uint16_t dif_upd_src_app_tag; 319 uint32_t dif_upd_dest_ref_tag; 320 uint16_t dif_upd_dest_app_tag_mask; 321 uint16_t dif_upd_dest_app_tag; 322 }; 323 324 uint8_t op_specific[16]; 325 }; 326 } __attribute__((packed)); 327 328 struct dsa_raw_completion_record { 329 uint64_t field[4]; 330 } __attribute__((packed)); 331 332 struct iax_completion_record { 333 volatile uint8_t status; 334 uint8_t error_code; 335 uint16_t rsvd; 336 uint32_t bytes_completed; 337 uint64_t fault_addr; 338 uint32_t invalid_flags; 339 uint32_t rsvd2; 340 uint32_t output_size; 341 uint8_t output_bits; 342 uint8_t rsvd3; 343 uint16_t xor_csum; 344 uint32_t crc; 345 uint32_t min; 346 uint32_t max; 347 uint32_t sum; 348 uint64_t rsvd4[2]; 349 } __attribute__((packed)); 350 351 struct iax_raw_completion_record { 352 uint64_t field[8]; 353 } __attribute__((packed)); 354 355 #endif 356