1 /*
2 * Suspend support specific for i386.
3 *
4 * Distribute under GPLv2
5 *
6 * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
7 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
8 *
9 * AK currently useless for 24 because the core ACPI code doesn't support S3.
10 * and most of the infrastructure is missing.
11 */
12
13 #include <linux/config.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/spinlock.h>
19 #include <linux/poll.h>
20 #include <linux/delay.h>
21 #include <linux/sysrq.h>
22 #include <linux/proc_fs.h>
23 #include <linux/irq.h>
24 #include <linux/pm.h>
25 #include <asm/uaccess.h>
26 #include <asm/acpi.h>
27 #include <asm/io.h>
28 #include <asm/proto.h>
29 #include <asm/i387.h>
30 #include <asm/desc.h>
31
32 void fix_processor_context(void);
33
34 /* Image of the saved processor state. If you touch this, fix acpi_wakeup.S. */
35 struct saved_context {
36 u16 ds, es, fs, gs, ss;
37 unsigned long gs_base, gs_kernel_base, fs_base;
38 unsigned long cr0, cr2, cr3, cr4;
39 u16 gdt_pad;
40 u16 gdt_limit;
41 unsigned long gdt_base;
42 u16 idt_pad;
43 u16 idt_limit;
44 unsigned long idt_base;
45 u16 ldt;
46 u16 tss;
47 unsigned long tr;
48 unsigned long safety;
49 unsigned long return_address;
50 unsigned long eflags;
51 } __attribute__((packed));
52
53 struct saved_context saved_context;
54
55 unsigned long saved_context_eax, saved_context_ebx, saved_context_ecx, saved_context_edx;
56 unsigned long saved_context_esp, saved_context_ebp, saved_context_esi, saved_context_edi;
57 unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_context_r11;
58 unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15;
59 unsigned long saved_context_eflags;
60
save_processor_state(void)61 void save_processor_state (void)
62 {
63 kernel_fpu_begin();
64
65 /*
66 * descriptor tables
67 */
68 asm volatile ("sgdt %0" : "=m" (saved_context.gdt_limit));
69 asm volatile ("sidt %0" : "=m" (saved_context.idt_limit));
70 asm volatile ("sldt %0" : "=m" (saved_context.ldt));
71 asm volatile ("str %0" : "=m" (saved_context.tr));
72
73 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
74 /* EFER should be constant for kernel version, no need to handle it. */
75 /*
76 * segment registers
77 */
78 asm volatile ("movw %%ds, %0" : "=m" (saved_context.ds));
79 asm volatile ("movw %%es, %0" : "=m" (saved_context.es));
80 asm volatile ("movw %%fs, %0" : "=m" (saved_context.fs));
81 asm volatile ("movw %%gs, %0" : "=m" (saved_context.gs));
82 asm volatile ("movw %%ss, %0" : "=m" (saved_context.ss));
83
84 rdmsrl(MSR_FS_BASE, saved_context.fs_base);
85 rdmsrl(MSR_GS_BASE, saved_context.gs_base);
86 rdmsrl(MSR_KERNEL_GS_BASE, saved_context.gs_kernel_base);
87
88 /*
89 * control registers
90 */
91 asm volatile ("movq %%cr0, %0" : "=r" (saved_context.cr0));
92 asm volatile ("movq %%cr2, %0" : "=r" (saved_context.cr2));
93 asm volatile ("movq %%cr3, %0" : "=r" (saved_context.cr3));
94 asm volatile ("movq %%cr4, %0" : "=r" (saved_context.cr4));
95 }
96
97 static void
do_fpu_end(void)98 do_fpu_end(void)
99 {
100 /* restore FPU regs if necessary */
101 kernel_fpu_end();
102 }
103
restore_processor_state(void)104 void restore_processor_state(void)
105 {
106 /*
107 * control registers
108 */
109 asm volatile ("movq %0, %%cr4" :: "r" (saved_context.cr4));
110 asm volatile ("movq %0, %%cr3" :: "r" (saved_context.cr3));
111 asm volatile ("movq %0, %%cr2" :: "r" (saved_context.cr2));
112 asm volatile ("movq %0, %%cr0" :: "r" (saved_context.cr0));
113
114 /*
115 * segment registers
116 */
117 asm volatile ("movw %0, %%ds" :: "r" (saved_context.ds));
118 asm volatile ("movw %0, %%es" :: "r" (saved_context.es));
119 asm volatile ("movw %0, %%fs" :: "r" (saved_context.fs));
120 load_gs_index(saved_context.gs);
121 asm volatile ("movw %0, %%ss" :: "r" (saved_context.ss));
122
123 wrmsrl(MSR_FS_BASE, saved_context.fs_base);
124 wrmsrl(MSR_GS_BASE, saved_context.gs_base);
125 wrmsrl(MSR_KERNEL_GS_BASE, saved_context.gs_kernel_base);
126
127 /*
128 * now restore the descriptor tables to their proper values
129 * ltr is done i fix_processor_context().
130 */
131 asm volatile ("lgdt %0" :: "m" (saved_context.gdt_limit));
132 asm volatile ("lidt %0" :: "m" (saved_context.idt_limit));
133 asm volatile ("lldt %0" :: "m" (saved_context.ldt));
134
135 fix_processor_context();
136
137 do_fpu_end();
138 }
139
140 #define loaddebug(thread,register) \
141 set_debug((thread)->debugreg[register], register)
142
fix_processor_context(void)143 void fix_processor_context(void)
144 {
145 int cpu = smp_processor_id();
146 struct tss_struct * t = init_tss + cpu;
147
148 set_tss_desc(cpu,t);
149
150 /* clear busy TSS */
151 gdt_cpu_table[cpu].tss.type = 9;
152
153 syscall_init(); /* This sets MSR_*STAR and related */
154 load_TR(cpu); /* This does ltr */
155 load_LDT(current->active_mm); /* This does lldt */
156
157 /*
158 * Now maybe reload the debug registers
159 */
160 if (current->thread.debugreg[7]){
161 loaddebug(¤t->thread, 0);
162 loaddebug(¤t->thread, 1);
163 loaddebug(¤t->thread, 2);
164 loaddebug(¤t->thread, 3);
165 /* no 4 and 5 */
166 loaddebug(¤t->thread, 6);
167 loaddebug(¤t->thread, 7);
168 }
169
170 }
171
172
173