1 /* drivers/atm/suni.h - PMC PM5346 SUNI (PHY) declarations */ 2 3 /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */ 4 5 6 #ifndef DRIVER_ATM_SUNI_H 7 #define DRIVER_ATM_SUNI_H 8 9 #include <linux/atmdev.h> 10 #include <linux/atmioc.h> 11 12 13 /* SUNI registers */ 14 15 #define SUNI_MRI 0x00 /* Master Reset and Identity / Load 16 Meter */ 17 #define SUNI_MC 0x01 /* Master Configuration */ 18 #define SUNI_MIS 0x02 /* Master Interrupt Status */ 19 /* no 0x03 */ 20 #define SUNI_MCM 0x04 /* Master Clock Monitor */ 21 #define SUNI_MCT 0x05 /* Master Control */ 22 #define SUNI_CSCS 0x06 /* Clock Synthesis Control and Status */ 23 #define SUNI_CRCS 0x07 /* Clock Recovery Control and Status */ 24 /* 0x08-0x0F reserved */ 25 #define SUNI_RSOP_CIE 0x10 /* RSOP Control/Interrupt Enable */ 26 #define SUNI_RSOP_SIS 0x11 /* RSOP Status/Interrupt Status */ 27 #define SUNI_RSOP_SBL 0x12 /* RSOP Section BIP-8 LSB */ 28 #define SUNI_RSOP_SBM 0x13 /* RSOP Section BIP-8 MSB */ 29 #define SUNI_TSOP_CTRL 0x14 /* TSOP Control */ 30 #define SUNI_TSOP_DIAG 0x15 /* TSOP Diagnostic */ 31 /* 0x16-0x17 reserved */ 32 #define SUNI_RLOP_CS 0x18 /* RLOP Control/Status */ 33 #define SUNI_RLOP_IES 0x19 /* RLOP Interrupt Enable/Status */ 34 #define SUNI_RLOP_LBL 0x1A /* RLOP Line BIP-8/24 LSB */ 35 #define SUNI_RLOP_LB 0x1B /* RLOP Line BIP-8/24 */ 36 #define SUNI_RLOP_LBM 0x1C /* RLOP Line BIP-8/24 MSB */ 37 #define SUNI_RLOP_LFL 0x1D /* RLOP Line FEBE LSB */ 38 #define SUNI_RLOP_LF 0x1E /* RLOP Line FEBE */ 39 #define SUNI_RLOP_LFM 0x1F /* RLOP Line FEBE MSB */ 40 #define SUNI_TLOP_CTRL 0x20 /* TLOP Control */ 41 #define SUNI_TLOP_DIAG 0x21 /* TLOP Diagnostic */ 42 /* 0x22-0x2F reserved */ 43 #define SUNI_RPOP_SC 0x30 /* RPOP Status/Control */ 44 #define SUNI_RPOP_IS 0x31 /* RPOP Interrupt Status */ 45 /* 0x32 reserved */ 46 #define SUNI_RPOP_IE 0x33 /* RPOP Interrupt Enable */ 47 /* 0x34-0x36 reserved */ 48 #define SUNI_RPOP_PSL 0x37 /* RPOP Path Signal Label */ 49 #define SUNI_RPOP_PBL 0x38 /* RPOP Path BIP-8 LSB */ 50 #define SUNI_RPOP_PBM 0x39 /* RPOP Path BIP-8 MSB */ 51 #define SUNI_RPOP_PFL 0x3A /* RPOP Path FEBE LSB */ 52 #define SUNI_RPOP_PFM 0x3B /* RPOP Path FEBE MSB */ 53 /* 0x3C reserved */ 54 #define SUNI_RPOP_PBC 0x3D /* RPOP Path BIP-8 Configuration */ 55 /* 0x3E-0x3F reserved */ 56 #define SUNI_TPOP_CD 0x40 /* TPOP Control/Diagnostic */ 57 #define SUNI_TPOP_PC 0x41 /* TPOP Pointer Control */ 58 /* 0x42-0x44 reserved */ 59 #define SUNI_TPOP_APL 0x45 /* TPOP Arbitrary Pointer LSB */ 60 #define SUNI_TPOP_APM 0x46 /* TPOP Arbitrary Pointer MSB */ 61 /* 0x47 reserved */ 62 #define SUNI_TPOP_PSL 0x48 /* TPOP Path Signal Label */ 63 #define SUNI_TPOP_PS 0x49 /* TPOP Path Status */ 64 /* 0x4A-0x4F reserved */ 65 #define SUNI_RACP_CS 0x50 /* RACP Control/Status */ 66 #define SUNI_RACP_IES 0x51 /* RACP Interrupt Enable/Status */ 67 #define SUNI_RACP_MHP 0x52 /* RACP Match Header Pattern */ 68 #define SUNI_RACP_MHM 0x53 /* RACP Match Header Mask */ 69 #define SUNI_RACP_CHEC 0x54 /* RACP Correctable HCS Error Count */ 70 #define SUNI_RACP_UHEC 0x55 /* RACP Uncorrectable HCS Err Count */ 71 #define SUNI_RACP_RCCL 0x56 /* RACP Receive Cell Counter LSB */ 72 #define SUNI_RACP_RCC 0x57 /* RACP Receive Cell Counter */ 73 #define SUNI_RACP_RCCM 0x58 /* RACP Receive Cell Counter MSB */ 74 #define SUNI_RACP_CFG 0x59 /* RACP Configuration */ 75 /* 0x5A-0x5F reserved */ 76 #define SUNI_TACP_CS 0x60 /* TACP Control/Status */ 77 #define SUNI_TACP_IUCHP 0x61 /* TACP Idle/Unassigned Cell Hdr Pat */ 78 #define SUNI_TACP_IUCPOP 0x62 /* TACP Idle/Unassigned Cell Payload 79 Octet Pattern */ 80 #define SUNI_TACP_FIFO 0x63 /* TACP FIFO Configuration */ 81 #define SUNI_TACP_TCCL 0x64 /* TACP Transmit Cell Counter LSB */ 82 #define SUNI_TACP_TCC 0x65 /* TACP Transmit Cell Counter */ 83 #define SUNI_TACP_TCCM 0x66 /* TACP Transmit Cell Counter MSB */ 84 #define SUNI_TACP_CFG 0x67 /* TACP Configuration */ 85 /* 0x68-0x7F reserved */ 86 #define SUNI_MT 0x80 /* Master Test */ 87 /* 0x81-0xFF reserved */ 88 89 /* SUNI register values */ 90 91 92 /* MRI is reg 0 */ 93 #define SUNI_MRI_ID 0x0f /* R, SUNI revision number */ 94 #define SUNI_MRI_ID_SHIFT 0 95 #define SUNI_MRI_TYPE 0x70 /* R, SUNI type (lite is 011) */ 96 #define SUNI_MRI_TYPE_SHIFT 4 97 #define SUNI_MRI_RESET 0x80 /* RW, reset & power down chip 98 0: normal operation 99 1: reset & low power */ 100 /* MCT is reg 5 */ 101 #define SUNI_MCT_LOOPT 0x01 /* RW, timing source, 0: from 102 TRCLK+/- */ 103 #define SUNI_MCT_DLE 0x02 /* RW, diagnostic loopback */ 104 #define SUNI_MCT_LLE 0x04 /* RW, line loopback */ 105 #define SUNI_MCT_FIXPTR 0x20 /* RW, disable transmit payload pointer 106 adjustments 107 0: payload ptr controlled by TPOP 108 ptr control reg 109 1: payload pointer fixed at 522 */ 110 #define SUNI_MCT_LCDV 0x40 /* R, loss of cell delineation */ 111 #define SUNI_MCT_LCDE 0x80 /* RW, loss of cell delineation 112 interrupt (1: on) */ 113 /* RSOP_CIE is reg 0x10 */ 114 #define SUNI_RSOP_CIE_OOFE 0x01 /* RW, enable interrupt on frame alarm 115 state change */ 116 #define SUNI_RSOP_CIE_LOFE 0x02 /* RW, enable interrupt on loss of 117 frame state change */ 118 #define SUNI_RSOP_CIE_LOSE 0x04 /* RW, enable interrupt on loss of 119 signal state change */ 120 #define SUNI_RSOP_CIE_BIPEE 0x08 /* RW, enable interrupt on section 121 BIP-8 error (B1) */ 122 #define SUNI_RSOP_CIE_FOOF 0x20 /* W, force RSOP out of frame at next 123 boundary */ 124 #define SUNI_RSOP_CIE_DDS 0x40 /* RW, disable scrambling */ 125 126 /* RSOP_SIS is reg 0x11 */ 127 #define SUNI_RSOP_SIS_OOFV 0x01 /* R, out of frame */ 128 #define SUNI_RSOP_SIS_LOFV 0x02 /* R, loss of frame */ 129 #define SUNI_RSOP_SIS_LOSV 0x04 /* R, loss of signal */ 130 #define SUNI_RSOP_SIS_OOFI 0x08 /* R, out of frame interrupt */ 131 #define SUNI_RSOP_SIS_LOFI 0x10 /* R, loss of frame interrupt */ 132 #define SUNI_RSOP_SIS_LOSI 0x20 /* R, loss of signal interrupt */ 133 #define SUNI_RSOP_SIS_BIPEI 0x40 /* R, section BIP-8 interrupt */ 134 135 /* TSOP_CTRL is reg 0x14 */ 136 #define SUNI_TSOP_CTRL_LAIS 0x01 /* insert alarm indication signal */ 137 #define SUNI_TSOP_CTRL_DS 0x40 /* disable scrambling */ 138 139 /* TSOP_DIAG is reg 0x15 */ 140 #define SUNI_TSOP_DIAG_DFP 0x01 /* insert single bit error cont. */ 141 #define SUNI_TSOP_DIAG_DBIP8 0x02 /* insert section BIP err (cont) */ 142 #define SUNI_TSOP_DIAG_DLOS 0x04 /* set line to zero (loss of signal) */ 143 144 /* TLOP_DIAG is reg 0x21 */ 145 #define SUNI_TLOP_DIAG_DBIP 0x01 /* insert line BIP err (continuously) */ 146 147 /* TPOP_DIAG is reg 0x40 */ 148 #define SUNI_TPOP_DIAG_PAIS 0x01 /* insert STS path alarm ind (cont) */ 149 #define SUNI_TPOP_DIAG_DB3 0x02 /* insert path BIP err (continuously) */ 150 151 /* TPOP_APM is reg 0x46 */ 152 #define SUNI_TPOP_APM_APTR 0x03 /* RW, arbitrary pointer, upper 2 153 bits */ 154 #define SUNI_TPOP_APM_APTR_SHIFT 0 155 #define SUNI_TPOP_APM_S 0x0c /* RW, "unused" bits of payload 156 pointer */ 157 #define SUNI_TPOP_APM_S_SHIFT 2 158 #define SUNI_TPOP_APM_NDF 0xf0 /* RW, NDF bits */ 159 #define SUNI_TPOP_APM_NDF_SHIFT 4 160 161 #define SUNI_TPOP_S_SONET 0 /* set S bits to 00 */ 162 #define SUNI_TPOP_S_SDH 2 /* set S bits to 10 */ 163 164 /* RACP_IES is reg 0x51 */ 165 #define SUNI_RACP_IES_FOVRI 0x02 /* R, FIFO overrun */ 166 #define SUNI_RACP_IES_UHCSI 0x04 /* R, uncorrectable HCS error */ 167 #define SUNI_RACP_IES_CHCSI 0x08 /* R, correctable HCS error */ 168 #define SUNI_RACP_IES_OOCDI 0x10 /* R, change of cell delineation 169 state */ 170 #define SUNI_RACP_IES_FIFOE 0x20 /* RW, enable FIFO overrun interrupt */ 171 #define SUNI_RACP_IES_HCSE 0x40 /* RW, enable HCS error interrupt */ 172 #define SUNI_RACP_IES_OOCDE 0x80 /* RW, enable cell delineation state 173 change interrupt */ 174 175 /* TACP_CS is reg 0x60 */ 176 #define SUNI_TACP_CS_FIFORST 0x01 /* RW, reset transmit FIFO (sticky) */ 177 #define SUNI_TACP_CS_DSCR 0x02 /* RW, disable payload scrambling */ 178 #define SUNI_TACP_CS_HCAADD 0x04 /* RW, add coset polynomial to HCS */ 179 #define SUNI_TACP_CS_DHCS 0x10 /* RW, insert HCS errors */ 180 #define SUNI_TACP_CS_FOVRI 0x20 /* R, FIFO overrun */ 181 #define SUNI_TACP_CS_TSOCI 0x40 /* R, TSOC input high */ 182 #define SUNI_TACP_CS_FIFOE 0x80 /* RW, enable FIFO overrun interrupt */ 183 184 /* TACP_IUCHP is reg 0x61 */ 185 #define SUNI_TACP_IUCHP_CLP 0x01 /* RW, 8th bit of 4th octet of i/u 186 pattern */ 187 #define SUNI_TACP_IUCHP_PTI 0x0e /* RW, 5th-7th bits of 4th octet of i/u 188 pattern */ 189 #define SUNI_TACP_IUCHP_PTI_SHIFT 1 190 #define SUNI_TACP_IUCHP_GFC 0xf0 /* RW, 1st-4th bits of 1st octet of i/u 191 pattern */ 192 #define SUNI_TACP_IUCHP_GFC_SHIFT 4 193 194 /* MT is reg 0x80 */ 195 #define SUNI_MT_HIZIO 0x01 /* RW, all but data bus & MP interface 196 tri-state */ 197 #define SUNI_MT_HIZDATA 0x02 /* W, also tri-state data bus */ 198 #define SUNI_MT_IOTST 0x04 /* RW, enable test mode */ 199 #define SUNI_MT_DBCTRL 0x08 /* W, control data bus by CSB pin */ 200 #define SUNI_MT_PMCTST 0x10 /* W, PMC test mode */ 201 #define SUNI_MT_DS27_53 0x80 /* RW, select between 8- or 16- bit */ 202 203 204 #define SUNI_IDLE_PATTERN 0x6a /* idle pattern */ 205 206 207 #ifdef __KERNEL__ 208 int suni_init(struct atm_dev *dev); 209 #endif 210 211 #endif 212