1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) Protonic Holland
4 * Author: David Jander <david@protonic.nl>
5 */
6/dts-v1/;
7
8#include "stm32mp151.dtsi"
9#include "stm32mp15-pinctrl.dtsi"
10#include "stm32mp15xxad-pinctrl.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/leds/common.h>
14
15/ {
16	aliases {
17		ethernet0 = &ethernet0;
18		mdio-gpio0 = &mdio0;
19		serial0 = &uart4;
20	};
21
22	led-controller-0 {
23		compatible = "gpio-leds";
24
25		led-0 {
26			color = <LED_COLOR_ID_RED>;
27			function = LED_FUNCTION_INDICATOR;
28			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
29		};
30
31		led-1 {
32			color = <LED_COLOR_ID_GREEN>;
33			function = LED_FUNCTION_INDICATOR;
34			gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
35			linux,default-trigger = "heartbeat";
36		};
37	};
38
39
40	/* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce
41	 * stmmac MDC clock without reducing system bus rate, we need to use
42	 * gpio based MDIO bus.
43	 */
44	mdio0: mdio {
45		compatible = "virtual,mdio-gpio";
46		#address-cells = <1>;
47		#size-cells = <0>;
48		gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
49			 &gpioa 2 GPIO_ACTIVE_HIGH>;
50	};
51
52	reg_3v3: regulator-3v3 {
53		compatible = "regulator-fixed";
54		regulator-name = "3v3";
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57	};
58};
59
60&dts {
61	status = "okay";
62};
63
64&ethernet0 {
65	pinctrl-0 = <&ethernet0_rmii_pins_a>;
66	pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
67	pinctrl-names = "default", "sleep";
68	phy-mode = "rmii";
69	status = "okay";
70};
71
72&ethernet0_rmii_pins_a {
73	pins1 {
74		pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */
75			 <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */
76			 <STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */
77	};
78	pins2 {
79		pinmux = <STM32_PINMUX('C', 4, AF11)>,  /* ETH1_RMII_RXD0 */
80			 <STM32_PINMUX('C', 5, AF11)>,  /* ETH1_RMII_RXD1 */
81			 <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK input */
82			 <STM32_PINMUX('A', 7, AF11)>;  /* ETH1_RMII_CRS_DV */
83	};
84};
85
86&ethernet0_rmii_sleep_pins_a {
87	pins1 {
88		pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* ETH1_RMII_TXD0 */
89			 <STM32_PINMUX('B', 13, ANALOG)>, /* ETH1_RMII_TXD1 */
90			 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
91			 <STM32_PINMUX('C', 4, ANALOG)>,  /* ETH1_RMII_RXD0 */
92			 <STM32_PINMUX('C', 5, ANALOG)>,  /* ETH1_RMII_RXD1 */
93			 <STM32_PINMUX('A', 1, ANALOG)>,  /* ETH1_RMII_REF_CLK */
94			 <STM32_PINMUX('A', 7, ANALOG)>;  /* ETH1_RMII_CRS_DV */
95	};
96};
97
98&iwdg2 {
99	status = "okay";
100};
101
102&qspi {
103	pinctrl-names = "default", "sleep";
104	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
105	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
106	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
107	#address-cells = <1>;
108	#size-cells = <0>;
109	status = "okay";
110
111	flash@0 {
112		compatible = "spi-nand";
113		reg = <0>;
114		spi-rx-bus-width = <4>;
115		spi-max-frequency = <104000000>;
116		#address-cells = <1>;
117		#size-cells = <1>;
118	};
119};
120
121&qspi_bk1_pins_a {
122	pins1 {
123		bias-pull-up;
124		drive-push-pull;
125		slew-rate = <1>;
126	};
127};
128
129&rng1 {
130	status = "okay";
131};
132
133&sdmmc1 {
134	pinctrl-names = "default", "opendrain", "sleep";
135	pinctrl-0 = <&sdmmc1_b4_pins_a>;
136	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
137	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
138	broken-cd;
139	st,neg-edge;
140	bus-width = <4>;
141	vmmc-supply = <&reg_3v3>;
142	vqmmc-supply = <&reg_3v3>;
143	status = "okay";
144};
145
146&sdmmc1_b4_od_pins_a {
147	pins1 {
148		bias-pull-up;
149	};
150	pins2 {
151		bias-pull-up;
152	};
153};
154
155&sdmmc1_b4_pins_a {
156	pins1 {
157		bias-pull-up;
158	};
159	pins2 {
160		bias-pull-up;
161	};
162};
163
164&uart4 {
165	pinctrl-names = "default", "sleep", "idle";
166	pinctrl-0 = <&uart4_pins_a>;
167	pinctrl-1 = <&uart4_sleep_pins_a>;
168	pinctrl-2 = <&uart4_idle_pins_a>;
169	/delete-property/dmas;
170	/delete-property/dma-names;
171	status = "okay";
172};
173
174&uart4_idle_pins_a {
175	pins1 {
176		pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* UART4_TX */
177	};
178	pins2 {
179		pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
180		bias-pull-up;
181	};
182};
183
184&uart4_pins_a {
185	pins1 {
186		pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
187		bias-disable;
188		drive-push-pull;
189		slew-rate = <0>;
190	};
191	pins2 {
192		pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
193		bias-pull-up;
194	};
195};
196
197&uart4_sleep_pins_a {
198	pins {
199		pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* UART4_TX */
200			<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
201	};
202};
203
204&usbh_ehci {
205	phys = <&usbphyc_port0>;
206	phy-names = "usb";
207	status = "okay";
208};
209
210&usbotg_hs {
211	dr_mode = "host";
212	pinctrl-0 = <&usbotg_hs_pins_a>;
213	pinctrl-names = "default";
214	phys = <&usbphyc_port1 0>;
215	phy-names = "usb2-phy";
216	status = "okay";
217};
218
219&usbphyc {
220	status = "okay";
221};
222
223&usbphyc_port0 {
224	phy-supply = <&reg_3v3>;
225};
226
227&usbphyc_port1 {
228	phy-supply = <&reg_3v3>;
229};
230