1 /* 2 * SMU_7_0_0 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef SMU_7_0_0_D_H 25 #define SMU_7_0_0_D_H 26 27 #define mmGCK_SMC_IND_INDEX 0x80 28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80 29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82 30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84 31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86 32 #define mmGCK_SMC_IND_DATA 0x81 33 #define mmGCK0_GCK_SMC_IND_DATA 0x81 34 #define mmGCK1_GCK_SMC_IND_DATA 0x83 35 #define mmGCK2_GCK_SMC_IND_DATA 0x85 36 #define mmGCK3_GCK_SMC_IND_DATA 0x87 37 #define ixCG_DCLK_CNTL 0xc050009c 38 #define ixCG_DCLK_STATUS 0xc05000a0 39 #define ixCG_VCLK_CNTL 0xc05000a4 40 #define ixCG_VCLK_STATUS 0xc05000a8 41 #define ixCG_ECLK_CNTL 0xc05000ac 42 #define ixCG_ECLK_STATUS 0xc05000b0 43 #define ixCG_ACLK_CNTL 0xc05000dc 44 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 47 #define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 48 #define ixCG_SPLL_FUNC_CNTL_4 0xc050014c 49 #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 50 #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 51 #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 52 #define ixSPLL_CNTL_MODE 0xc0500160 53 #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 54 #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 55 #define ixMPLL_BYPASSCLK_SEL 0xc050019c 56 #define ixCG_CLKPIN_CNTL 0xc05001a0 57 #define ixCG_CLKPIN_CNTL_2 0xc05001a4 58 #define ixTHM_CLK_CNTL 0xc05001a8 59 #define ixMISC_CLK_CTRL 0xc05001ac 60 #define ixGCK_PLL_TEST_CNTL 0xc05001c0 61 #define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 62 #define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 63 #define mmSMC_IND_INDEX 0x80 64 #define mmSMC0_SMC_IND_INDEX 0x80 65 #define mmSMC1_SMC_IND_INDEX 0x82 66 #define mmSMC2_SMC_IND_INDEX 0x84 67 #define mmSMC3_SMC_IND_INDEX 0x86 68 #define mmSMC_IND_DATA 0x81 69 #define mmSMC0_SMC_IND_DATA 0x81 70 #define mmSMC1_SMC_IND_DATA 0x83 71 #define mmSMC2_SMC_IND_DATA 0x85 72 #define mmSMC3_SMC_IND_DATA 0x87 73 #define mmSMC_IND_INDEX_0 0x80 74 #define mmSMC_IND_DATA_0 0x81 75 #define mmSMC_IND_INDEX_1 0x82 76 #define mmSMC_IND_DATA_1 0x83 77 #define mmSMC_IND_INDEX_2 0x84 78 #define mmSMC_IND_DATA_2 0x85 79 #define mmSMC_IND_INDEX_3 0x86 80 #define mmSMC_IND_DATA_3 0x87 81 #define mmSMC_IND_INDEX_4 0x88 82 #define mmSMC_IND_DATA_4 0x89 83 #define mmSMC_IND_INDEX_5 0x8a 84 #define mmSMC_IND_DATA_5 0x8b 85 #define mmSMC_IND_INDEX_6 0x8c 86 #define mmSMC_IND_DATA_6 0x8d 87 #define mmSMC_IND_INDEX_7 0x8e 88 #define mmSMC_IND_DATA_7 0x8f 89 #define mmSMC_IND_ACCESS_CNTL 0x90 90 #define mmSMC_MESSAGE_0 0x94 91 #define mmSMC_RESP_0 0x95 92 #define mmSMC_MESSAGE_1 0x96 93 #define mmSMC_RESP_1 0x97 94 #define mmSMC_MESSAGE_2 0x98 95 #define mmSMC_RESP_2 0x99 96 #define mmSMC_MESSAGE_3 0x9a 97 #define mmSMC_RESP_3 0x9b 98 #define mmSMC_MESSAGE_4 0x9c 99 #define mmSMC_RESP_4 0x9d 100 #define mmSMC_MESSAGE_5 0x9e 101 #define mmSMC_RESP_5 0x9f 102 #define mmSMC_MESSAGE_6 0xa0 103 #define mmSMC_RESP_6 0xa1 104 #define mmSMC_MESSAGE_7 0xa2 105 #define mmSMC_RESP_7 0xa3 106 #define mmSMC_MSG_ARG_0 0xa4 107 #define mmSMC_MSG_ARG_1 0xa5 108 #define mmSMC_MSG_ARG_2 0xa6 109 #define mmSMC_MSG_ARG_3 0xa7 110 #define mmSMC_MSG_ARG_4 0xa8 111 #define mmSMC_MSG_ARG_5 0xa9 112 #define mmSMC_MSG_ARG_6 0xaa 113 #define mmSMC_MSG_ARG_7 0xab 114 #define mmSMC_MESSAGE_8 0xb5 115 #define mmSMC_RESP_8 0xb6 116 #define mmSMC_MESSAGE_9 0xb7 117 #define mmSMC_RESP_9 0xb8 118 #define mmSMC_MESSAGE_10 0xb9 119 #define mmSMC_RESP_10 0xba 120 #define mmSMC_MESSAGE_11 0xbb 121 #define mmSMC_RESP_11 0xbc 122 #define mmSMC_MSG_ARG_8 0xbd 123 #define mmSMC_MSG_ARG_9 0xbe 124 #define mmSMC_MSG_ARG_10 0xbf 125 #define mmSMC_MSG_ARG_11 0x91 126 #define ixSMC_SYSCON_RESET_CNTL 0x80000000 127 #define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 128 #define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 129 #define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c 130 #define ixSMC_SYSCON_MISC_CNTL 0x80000010 131 #define ixSMC_SYSCON_MSG_ARG_0 0x80000068 132 #define ixSMC_PC_C 0x80000370 133 #define ixSMC_SCRATCH9 0x80000424 134 #define mmCG_FPS_CNT 0x1a4 135 #define mmSMU_SMC_IND_INDEX 0x80 136 #define mmSMU0_SMU_SMC_IND_INDEX 0x80 137 #define mmSMU1_SMU_SMC_IND_INDEX 0x82 138 #define mmSMU2_SMU_SMC_IND_INDEX 0x84 139 #define mmSMU3_SMU_SMC_IND_INDEX 0x86 140 #define mmSMU_SMC_IND_DATA 0x81 141 #define mmSMU0_SMU_SMC_IND_DATA 0x81 142 #define mmSMU1_SMU_SMC_IND_DATA 0x83 143 #define mmSMU2_SMU_SMC_IND_DATA 0x85 144 #define mmSMU3_SMU_SMC_IND_DATA 0x87 145 #define ixRCU_UC_EVENTS 0xc0000004 146 #define ixRCU_MISC_CTRL 0xc0000010 147 #define ixCC_RCU_FUSES 0xc00c0000 148 #define ixCC_SMU_MISC_FUSES 0xc00c0004 149 #define ixCC_SCLK_VID_FUSES 0xc00c0008 150 #define ixCC_GIO_IOCCFG_FUSES 0xc00c000c 151 #define ixCC_GIO_IOC_FUSES 0xc00c0010 152 #define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c 153 #define ixCC_TST_ID_STRAPS 0xc00c0020 154 #define ixCC_FCTRL_FUSES 0xc00c0024 155 #define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 156 #define ixSMU_STATUS 0xe0003088 157 #define ixSMU_FIRMWARE 0xe00030a4 158 #define ixSMU_INPUT_DATA 0xe00030b8 159 #define ixSMU_EFUSE_0 0xc0100000 160 #define ixDPM_TABLE_1 0x3f000 161 #define ixDPM_TABLE_2 0x3f004 162 #define ixDPM_TABLE_3 0x3f008 163 #define ixDPM_TABLE_4 0x3f00c 164 #define ixDPM_TABLE_5 0x3f010 165 #define ixDPM_TABLE_6 0x3f014 166 #define ixDPM_TABLE_7 0x3f018 167 #define ixDPM_TABLE_8 0x3f01c 168 #define ixDPM_TABLE_9 0x3f020 169 #define ixDPM_TABLE_10 0x3f024 170 #define ixDPM_TABLE_11 0x3f028 171 #define ixDPM_TABLE_12 0x3f02c 172 #define ixDPM_TABLE_13 0x3f030 173 #define ixDPM_TABLE_14 0x3f034 174 #define ixDPM_TABLE_15 0x3f038 175 #define ixDPM_TABLE_16 0x3f03c 176 #define ixDPM_TABLE_17 0x3f040 177 #define ixDPM_TABLE_18 0x3f044 178 #define ixDPM_TABLE_19 0x3f048 179 #define ixDPM_TABLE_20 0x3f04c 180 #define ixDPM_TABLE_21 0x3f050 181 #define ixDPM_TABLE_22 0x3f054 182 #define ixDPM_TABLE_23 0x3f058 183 #define ixDPM_TABLE_24 0x3f05c 184 #define ixDPM_TABLE_25 0x3f060 185 #define ixDPM_TABLE_26 0x3f064 186 #define ixDPM_TABLE_27 0x3f068 187 #define ixDPM_TABLE_28 0x3f06c 188 #define ixDPM_TABLE_29 0x3f070 189 #define ixDPM_TABLE_30 0x3f074 190 #define ixDPM_TABLE_31 0x3f078 191 #define ixDPM_TABLE_32 0x3f07c 192 #define ixDPM_TABLE_33 0x3f080 193 #define ixDPM_TABLE_34 0x3f084 194 #define ixDPM_TABLE_35 0x3f088 195 #define ixDPM_TABLE_36 0x3f08c 196 #define ixDPM_TABLE_37 0x3f090 197 #define ixDPM_TABLE_38 0x3f094 198 #define ixDPM_TABLE_39 0x3f098 199 #define ixDPM_TABLE_40 0x3f09c 200 #define ixDPM_TABLE_41 0x3f0a0 201 #define ixDPM_TABLE_42 0x3f0a4 202 #define ixDPM_TABLE_43 0x3f0a8 203 #define ixDPM_TABLE_44 0x3f0ac 204 #define ixDPM_TABLE_45 0x3f0b0 205 #define ixDPM_TABLE_46 0x3f0b4 206 #define ixDPM_TABLE_47 0x3f0b8 207 #define ixDPM_TABLE_48 0x3f0bc 208 #define ixDPM_TABLE_49 0x3f0c0 209 #define ixDPM_TABLE_50 0x3f0c4 210 #define ixDPM_TABLE_51 0x3f0c8 211 #define ixDPM_TABLE_52 0x3f0cc 212 #define ixDPM_TABLE_53 0x3f0d0 213 #define ixDPM_TABLE_54 0x3f0d4 214 #define ixDPM_TABLE_55 0x3f0d8 215 #define ixDPM_TABLE_56 0x3f0dc 216 #define ixDPM_TABLE_57 0x3f0e0 217 #define ixDPM_TABLE_58 0x3f0e4 218 #define ixDPM_TABLE_59 0x3f0e8 219 #define ixDPM_TABLE_60 0x3f0ec 220 #define ixDPM_TABLE_61 0x3f0f0 221 #define ixDPM_TABLE_62 0x3f0f4 222 #define ixDPM_TABLE_63 0x3f0f8 223 #define ixDPM_TABLE_64 0x3f0fc 224 #define ixDPM_TABLE_65 0x3f100 225 #define ixDPM_TABLE_66 0x3f104 226 #define ixDPM_TABLE_67 0x3f108 227 #define ixDPM_TABLE_68 0x3f10c 228 #define ixDPM_TABLE_69 0x3f110 229 #define ixDPM_TABLE_70 0x3f114 230 #define ixDPM_TABLE_71 0x3f118 231 #define ixDPM_TABLE_72 0x3f11c 232 #define ixDPM_TABLE_73 0x3f120 233 #define ixDPM_TABLE_74 0x3f124 234 #define ixDPM_TABLE_75 0x3f128 235 #define ixDPM_TABLE_76 0x3f12c 236 #define ixDPM_TABLE_77 0x3f130 237 #define ixDPM_TABLE_78 0x3f134 238 #define ixDPM_TABLE_79 0x3f138 239 #define ixDPM_TABLE_80 0x3f13c 240 #define ixDPM_TABLE_81 0x3f140 241 #define ixDPM_TABLE_82 0x3f144 242 #define ixDPM_TABLE_83 0x3f148 243 #define ixDPM_TABLE_84 0x3f14c 244 #define ixDPM_TABLE_85 0x3f150 245 #define ixDPM_TABLE_86 0x3f154 246 #define ixDPM_TABLE_87 0x3f158 247 #define ixDPM_TABLE_88 0x3f15c 248 #define ixDPM_TABLE_89 0x3f160 249 #define ixDPM_TABLE_90 0x3f164 250 #define ixDPM_TABLE_91 0x3f168 251 #define ixDPM_TABLE_92 0x3f16c 252 #define ixDPM_TABLE_93 0x3f170 253 #define ixDPM_TABLE_94 0x3f174 254 #define ixDPM_TABLE_95 0x3f178 255 #define ixDPM_TABLE_96 0x3f17c 256 #define ixDPM_TABLE_97 0x3f180 257 #define ixDPM_TABLE_98 0x3f184 258 #define ixDPM_TABLE_99 0x3f188 259 #define ixDPM_TABLE_100 0x3f18c 260 #define ixDPM_TABLE_101 0x3f190 261 #define ixDPM_TABLE_102 0x3f194 262 #define ixDPM_TABLE_103 0x3f198 263 #define ixDPM_TABLE_104 0x3f19c 264 #define ixDPM_TABLE_105 0x3f1a0 265 #define ixDPM_TABLE_106 0x3f1a4 266 #define ixDPM_TABLE_107 0x3f1a8 267 #define ixDPM_TABLE_108 0x3f1ac 268 #define ixDPM_TABLE_109 0x3f1b0 269 #define ixDPM_TABLE_110 0x3f1b4 270 #define ixDPM_TABLE_111 0x3f1b8 271 #define ixDPM_TABLE_112 0x3f1bc 272 #define ixDPM_TABLE_113 0x3f1c0 273 #define ixDPM_TABLE_114 0x3f1c4 274 #define ixDPM_TABLE_115 0x3f1c8 275 #define ixDPM_TABLE_116 0x3f1cc 276 #define ixDPM_TABLE_117 0x3f1d0 277 #define ixDPM_TABLE_118 0x3f1d4 278 #define ixDPM_TABLE_119 0x3f1d8 279 #define ixDPM_TABLE_120 0x3f1dc 280 #define ixDPM_TABLE_121 0x3f1e0 281 #define ixDPM_TABLE_122 0x3f1e4 282 #define ixDPM_TABLE_123 0x3f1e8 283 #define ixDPM_TABLE_124 0x3f1ec 284 #define ixDPM_TABLE_125 0x3f1f0 285 #define ixDPM_TABLE_126 0x3f1f4 286 #define ixDPM_TABLE_127 0x3f1f8 287 #define ixDPM_TABLE_128 0x3f1fc 288 #define ixDPM_TABLE_129 0x3f200 289 #define ixDPM_TABLE_130 0x3f204 290 #define ixDPM_TABLE_131 0x3f208 291 #define ixDPM_TABLE_132 0x3f20c 292 #define ixDPM_TABLE_133 0x3f210 293 #define ixDPM_TABLE_134 0x3f214 294 #define ixDPM_TABLE_135 0x3f218 295 #define ixDPM_TABLE_136 0x3f21c 296 #define ixDPM_TABLE_137 0x3f220 297 #define ixDPM_TABLE_138 0x3f224 298 #define ixDPM_TABLE_139 0x3f228 299 #define ixDPM_TABLE_140 0x3f22c 300 #define ixDPM_TABLE_141 0x3f230 301 #define ixDPM_TABLE_142 0x3f234 302 #define ixDPM_TABLE_143 0x3f238 303 #define ixDPM_TABLE_144 0x3f23c 304 #define ixDPM_TABLE_145 0x3f240 305 #define ixDPM_TABLE_146 0x3f244 306 #define ixDPM_TABLE_147 0x3f248 307 #define ixDPM_TABLE_148 0x3f24c 308 #define ixDPM_TABLE_149 0x3f250 309 #define ixDPM_TABLE_150 0x3f254 310 #define ixDPM_TABLE_151 0x3f258 311 #define ixDPM_TABLE_152 0x3f25c 312 #define ixDPM_TABLE_153 0x3f260 313 #define ixDPM_TABLE_154 0x3f264 314 #define ixDPM_TABLE_155 0x3f268 315 #define ixDPM_TABLE_156 0x3f26c 316 #define ixDPM_TABLE_157 0x3f270 317 #define ixDPM_TABLE_158 0x3f274 318 #define ixDPM_TABLE_159 0x3f278 319 #define ixDPM_TABLE_160 0x3f27c 320 #define ixDPM_TABLE_161 0x3f280 321 #define ixDPM_TABLE_162 0x3f284 322 #define ixDPM_TABLE_163 0x3f288 323 #define ixDPM_TABLE_164 0x3f28c 324 #define ixDPM_TABLE_165 0x3f290 325 #define ixDPM_TABLE_166 0x3f294 326 #define ixDPM_TABLE_167 0x3f298 327 #define ixDPM_TABLE_168 0x3f29c 328 #define ixDPM_TABLE_169 0x3f2a0 329 #define ixDPM_TABLE_170 0x3f2a4 330 #define ixDPM_TABLE_171 0x3f2a8 331 #define ixDPM_TABLE_172 0x3f2ac 332 #define ixDPM_TABLE_173 0x3f2b0 333 #define ixDPM_TABLE_174 0x3f2b4 334 #define ixDPM_TABLE_175 0x3f2b8 335 #define ixDPM_TABLE_176 0x3f2bc 336 #define ixDPM_TABLE_177 0x3f2c0 337 #define ixDPM_TABLE_178 0x3f2c4 338 #define ixDPM_TABLE_179 0x3f2c8 339 #define ixDPM_TABLE_180 0x3f2cc 340 #define ixDPM_TABLE_181 0x3f2d0 341 #define ixDPM_TABLE_182 0x3f2d4 342 #define ixDPM_TABLE_183 0x3f2d8 343 #define ixDPM_TABLE_184 0x3f2dc 344 #define ixDPM_TABLE_185 0x3f2e0 345 #define ixDPM_TABLE_186 0x3f2e4 346 #define ixDPM_TABLE_187 0x3f2e8 347 #define ixDPM_TABLE_188 0x3f2ec 348 #define ixDPM_TABLE_189 0x3f2f0 349 #define ixDPM_TABLE_190 0x3f2f4 350 #define ixDPM_TABLE_191 0x3f2f8 351 #define ixSOFT_REGISTERS_TABLE_1 0x3f900 352 #define ixSOFT_REGISTERS_TABLE_2 0x3f904 353 #define ixSOFT_REGISTERS_TABLE_3 0x3f908 354 #define ixSOFT_REGISTERS_TABLE_4 0x3f90c 355 #define ixSOFT_REGISTERS_TABLE_5 0x3f910 356 #define ixSOFT_REGISTERS_TABLE_6 0x3f914 357 #define ixSOFT_REGISTERS_TABLE_7 0x3f918 358 #define ixSOFT_REGISTERS_TABLE_8 0x3f91c 359 #define ixSOFT_REGISTERS_TABLE_9 0x3f920 360 #define ixSOFT_REGISTERS_TABLE_10 0x3f924 361 #define ixSOFT_REGISTERS_TABLE_11 0x3f928 362 #define ixSOFT_REGISTERS_TABLE_12 0x3f92c 363 #define ixSOFT_REGISTERS_TABLE_13 0x3f930 364 #define ixSOFT_REGISTERS_TABLE_14 0x3f934 365 #define ixSOFT_REGISTERS_TABLE_15 0x3f938 366 #define ixSOFT_REGISTERS_TABLE_16 0x3f93c 367 #define ixSOFT_REGISTERS_TABLE_17 0x3f940 368 #define ixSOFT_REGISTERS_TABLE_18 0x3f944 369 #define ixSOFT_REGISTERS_TABLE_19 0x3f948 370 #define ixSOFT_REGISTERS_TABLE_20 0x3f94c 371 #define ixSOFT_REGISTERS_TABLE_21 0x3f950 372 #define ixSMU_LCLK_DPM_STATE_0_CNTL_0 0x3fd00 373 #define ixSMU_LCLK_DPM_STATE_1_CNTL_0 0x3fd14 374 #define ixSMU_LCLK_DPM_STATE_2_CNTL_0 0x3fd28 375 #define ixSMU_LCLK_DPM_STATE_3_CNTL_0 0x3fd3c 376 #define ixSMU_LCLK_DPM_STATE_4_CNTL_0 0x3fd50 377 #define ixSMU_LCLK_DPM_STATE_5_CNTL_0 0x3fd64 378 #define ixSMU_LCLK_DPM_STATE_6_CNTL_0 0x3fd78 379 #define ixSMU_LCLK_DPM_STATE_7_CNTL_0 0x3fd8c 380 #define ixSMU_LCLK_DPM_STATE_0_CNTL_1 0x3fd04 381 #define ixSMU_LCLK_DPM_STATE_1_CNTL_1 0x3fd18 382 #define ixSMU_LCLK_DPM_STATE_2_CNTL_1 0x3fd2c 383 #define ixSMU_LCLK_DPM_STATE_3_CNTL_1 0x3fd40 384 #define ixSMU_LCLK_DPM_STATE_4_CNTL_1 0x3fd54 385 #define ixSMU_LCLK_DPM_STATE_5_CNTL_1 0x3fd68 386 #define ixSMU_LCLK_DPM_STATE_6_CNTL_1 0x3fd7c 387 #define ixSMU_LCLK_DPM_STATE_7_CNTL_1 0x3fd90 388 #define ixSMU_LCLK_DPM_STATE_0_CNTL_2 0x3fd08 389 #define ixSMU_LCLK_DPM_STATE_1_CNTL_2 0x3fd1c 390 #define ixSMU_LCLK_DPM_STATE_2_CNTL_2 0x3fd30 391 #define ixSMU_LCLK_DPM_STATE_3_CNTL_2 0x3fd44 392 #define ixSMU_LCLK_DPM_STATE_4_CNTL_2 0x3fd58 393 #define ixSMU_LCLK_DPM_STATE_5_CNTL_2 0x3fd6c 394 #define ixSMU_LCLK_DPM_STATE_6_CNTL_2 0x3fd80 395 #define ixSMU_LCLK_DPM_STATE_7_CNTL_2 0x3fd94 396 #define ixSMU_LCLK_DPM_STATE_0_CNTL_3 0x3fd0c 397 #define ixSMU_LCLK_DPM_STATE_1_CNTL_3 0x3fd20 398 #define ixSMU_LCLK_DPM_STATE_2_CNTL_3 0x3fd34 399 #define ixSMU_LCLK_DPM_STATE_3_CNTL_3 0x3fd48 400 #define ixSMU_LCLK_DPM_STATE_4_CNTL_3 0x3fd5c 401 #define ixSMU_LCLK_DPM_STATE_5_CNTL_3 0x3fd70 402 #define ixSMU_LCLK_DPM_STATE_6_CNTL_3 0x3fd84 403 #define ixSMU_LCLK_DPM_STATE_7_CNTL_3 0x3fd98 404 #define ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD 0x3fd10 405 #define ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD 0x3fd24 406 #define ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD 0x3fd38 407 #define ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD 0x3fd4c 408 #define ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD 0x3fd60 409 #define ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD 0x3fd74 410 #define ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD 0x3fd88 411 #define ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD 0x3fd9c 412 #define ixGIO_PID_CONTROLLER_CNTL_0 0x3fda0 413 #define ixGIO_PID_CONTROLLER_CNTL_1 0x3fda4 414 #define ixGIO_PID_CONTROLLER_CNTL_2 0x3fda8 415 #define ixGIO_PID_CONTROLLER_CNTL_3 0x3fdac 416 #define ixGIO_PID_CONTROLLER_CNTL_4 0x3fdb0 417 #define ixGIO_PID_CONTROLLER_CNTL_5 0x3fdb4 418 #define ixGIO_PID_CONTROLLER_CNTL_6 0x3fdb8 419 #define ixGIO_PID_CONTROLLER_CNTL_7 0x3fdbc 420 #define ixGIO_PID_CONTROLLER_CNTL_8 0x3fdc0 421 #define ixSMU_LCLK_DPM_LEVEL_COUNT 0x3fdc4 422 #define ixSMU_LCLK_DPM_CNTL 0x3fdc8 423 #define ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE 0x3fdcc 424 #define ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL 0x3fdd0 425 #define ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS 0x3fdd4 426 #define ixPM_FUSES_1 0x3fa80 427 #define ixPM_FUSES_2 0x3fa84 428 #define ixPM_FUSES_3 0x3fa88 429 #define ixPM_FUSES_4 0x3fa8c 430 #define ixPM_FUSES_5 0x3fa90 431 #define ixPM_FUSES_6 0x3fa94 432 #define ixPM_FUSES_7 0x3fa98 433 #define ixPM_FUSES_8 0x3fa9c 434 #define ixPM_FUSES_9 0x3faa0 435 #define ixPM_FUSES_10 0x3faa4 436 #define ixPM_FUSES_11 0x3faa8 437 #define ixPM_FUSES_12 0x3faac 438 #define ixPM_FUSES_13 0x3fab0 439 #define ixPM_FUSES_14 0x3fab4 440 #define ixPM_FUSES_15 0x3fab8 441 #define ixPM_FUSES_16 0x3fabc 442 #define ixPM_FUSES_17 0x3fac0 443 #define ixPM_FUSES_18 0x3fac4 444 #define ixPM_FUSES_19 0x3fac8 445 #define ixPM_FUSES_20 0x3facc 446 #define ixPM_FUSES_21 0x3fad0 447 #define ixPM_FUSES_22 0x3fad4 448 #define ixPM_FUSES_23 0x3fad8 449 #define ixPM_FUSES_24 0x3fadc 450 #define ixPM_FUSES_25 0x3fae0 451 #define ixPM_FUSES_26 0x3fae4 452 #define ixPM_FUSES_27 0x3fae8 453 #define ixPM_FUSES_28 0x3faec 454 #define ixPM_FUSES_29 0x3faf0 455 #define ixPM_FUSES_30 0x3faf4 456 #define ixPM_FUSES_31 0x3faf8 457 #define ixPM_FUSES_32 0x3fafc 458 #define ixPM_FUSES_33 0x3fb00 459 #define ixPM_FUSES_34 0x3fb04 460 #define ixPM_FUSES_35 0x3fb08 461 #define ixPM_FUSES_36 0x3fb0c 462 #define ixPM_FUSES_37 0x3fb10 463 #define ixPM_FUSES_38 0x3fb14 464 #define ixPM_FUSES_39 0x3fb18 465 #define ixPM_FUSES_40 0x3fb1c 466 #define ixPM_FUSES_41 0x3fb20 467 #define ixPM_FUSES_42 0x3fb24 468 #define ixPM_FUSES_43 0x3fb28 469 #define ixPM_FUSES_44 0x3fb2c 470 #define ixPM_FUSES_45 0x3fb30 471 #define ixPM_FUSES_46 0x3fb34 472 #define ixPM_FUSES_47 0x3fb38 473 #define ixPM_FUSES_48 0x3fb3c 474 #define ixPM_FUSES_49 0x3fb40 475 #define ixPM_FUSES_50 0x3fb44 476 #define ixPM_FUSES_51 0x3fb48 477 #define ixPM_FUSES_52 0x3fb4c 478 #define ixPM_FUSES_53 0x3fb50 479 #define ixPM_FUSES_54 0x3fb54 480 #define ixPM_FUSES_55 0x3fb58 481 #define ixPM_FUSES_56 0x3fb5c 482 #define ixPM_FUSES_57 0x3fb60 483 #define ixPM_FUSES_58 0x3fb64 484 #define ixPM_FUSES_59 0x3fb68 485 #define ixPM_FUSES_60 0x3fb6c 486 #define ixPM_FUSES_61 0x3fb70 487 #define ixPM_FUSES_62 0x3fb74 488 #define ixPM_FUSES_63 0x3fb78 489 #define ixPM_FUSES_64 0x3fb7c 490 #define ixPM_FUSES_65 0x3fb80 491 #define ixFIRMWARE_FLAGS 0x3f800 492 #define ixTEMPERATURE_READ_ADDR 0x3f808 493 #define ixCURRENT_GNB_TEMP 0x3f810 494 #define ixCURRENT_GLOBAL_TEMP 0x3f814 495 #define ixFEATURE_STATUS 0x3f818 496 #define ixPCIE_PLL_RECONF 0x3f81c 497 #define ixPM_INTERVAL_CNTL_0 0x3f820 498 #define ixPM_INTERVAL_CNTL_1 0x3f824 499 #define ixPM_INTERVAL_CNTL_2 0x3f82c 500 #define ixVPC_INTERVAL_CNTL 0x3f830 501 #define ixDISP_PHY_TDP_LIMIT 0x3f834 502 #define ixFCH_PWR_CREDIT 0x3f838 503 #define ixPKGPWR_MV_AVG 0x3f83c 504 #define ixPACKAGE_POWER 0x3f840 505 #define ixPKG_PWR_CNTL 0x3f844 506 #define ixPKG_PWR_STATUS 0x3f848 507 #define ixDISP_PHY_CONFIG 0x3f84c 508 #define ixGPU_TDP_LIMIT 0x3f850 509 #define ixEXT_API_IN_DATA_0_0 0x3f858 510 #define ixEXT_API_IN_DATA_0_1 0x3f85c 511 #define ixEXT_API_IN_DATA_0_2 0x3f860 512 #define ixEXT_API_IN_DATA_0_3 0x3f864 513 #define ixEXT_API_OUT_DATA_0_0 0x3f868 514 #define ixEXT_API_OUT_DATA_0_1 0x3f86c 515 #define ixEXT_API_OUT_DATA_0_2 0x3f870 516 #define ixEXT_API_OUT_DATA_0_3 0x3f874 517 #define ixBAPM_PARAMETERS 0x3f984 518 #define ixBAPM_PARAMETERS_2 0x3f988 519 #define ixBAPM_PARAMETERS_3 0x3f98c 520 #define ixBAPM_PARAMETERS_4 0x3f990 521 #define ixSMU_SVI_TELEMETRY 0x3f994 522 #define ixBAPM_STATUS 0x3f998 523 #define ixSMU_HTC_STATUS 0x3f99c 524 #define ixSMU_VPC_STATUS 0x3f9a0 525 #define ixENTITY_TEMPERATURES_1 0x3f9a4 526 #define ixENTITY_TEMPERATURES_2 0x3f9a8 527 #define ixENTITY_TEMPERATURES_3 0x3f9ac 528 #define ixCU_POWER 0x3f9b0 529 #define ixGPU_POWER 0x3f9b4 530 #define ixNTE_POWER 0x3f9b8 531 #define ixTDC_STATUS 0x3f9d0 532 #define ixTDC_MV_AVERAGE 0x3f9d4 533 #define ixPM_CONFIG 0x3f9d8 534 #define ixTE0_TEMPERATURE_READ_ADDR 0x3f9dc 535 #define ixTE1_TEMPERATURE_READ_ADDR 0x3f9e0 536 #define ixTE2_TEMPERATURE_READ_ADDR 0x3f9e4 537 #define ixNB_DPM_CONFIG_1 0x3f9e8 538 #define ixNB_DPM_CONFIG_2 0x3f9ec 539 #define ixNB_DPM_CONFIG_3 0x3f9f0 540 #define ixSMU_IDD_OVERRIDE 0x3f9fc 541 #define ixAVS_CONFIG 0x3fa00 542 #define ixTDC_VRM_LIMIT 0x3fa04 543 #define ixCU0_PSM_CONFIG 0x3fa08 544 #define ixCU1_PSM_CONFIG 0x3fa0c 545 #define ixSPMI_CONFIG 0x3fa10 546 #define ixSPMI_SMC_CHAIN_ADDR 0x3fa14 547 #define ixSPMI_STATUS 0x3fa30 548 #define ixAVSNB_CONFIG 0x3fa34 549 #define ixHTC_CONFIG 0x3fa38 550 #define ixAVS_CU0_TEMPERATURE_SENSOR 0x3fa3c 551 #define ixAVS_CU1_TEMPERATURE_SENSOR 0x3fa40 552 #define ixAVS_GNB_TEMPERATURE_SENSOR 0x3fa44 553 #define ixAVS_UNB_TEMPERATURE_SENSOR 0x3fa48 554 #define ixSMU_MONITOR_PORT80_MMIO_ADDR 0x3fa4c 555 #define ixSMU_MONITOR_PORT80_MEMBASE_HI 0x3fa50 556 #define ixSMU_MONITOR_PORT80_MEMBASE_LO 0x3fa54 557 #define ixSMU_MONITOR_PORT80_MEMSETUP 0x3fa58 558 #define ixSMU_MONITOR_PORT80_CTRL 0x3fa5c 559 #define ixSMU_TCEN_ALIVE 0x3fa60 560 #define ixPDM_STATUS 0x3fa64 561 #define ixPDM_CNTL_1 0x3fa68 562 #define ixPDM_CNTL_2 0x3fa6c 563 #define ixPDM_CNTL_3 0x3fa70 564 #define ixSMU_PM_STATUS_0 0x3fe00 565 #define ixSMU_PM_STATUS_1 0x3fe04 566 #define ixSMU_PM_STATUS_2 0x3fe08 567 #define ixSMU_PM_STATUS_3 0x3fe0c 568 #define ixSMU_PM_STATUS_4 0x3fe10 569 #define ixSMU_PM_STATUS_5 0x3fe14 570 #define ixSMU_PM_STATUS_6 0x3fe18 571 #define ixSMU_PM_STATUS_7 0x3fe1c 572 #define ixSMU_PM_STATUS_8 0x3fe20 573 #define ixSMU_PM_STATUS_9 0x3fe24 574 #define ixSMU_PM_STATUS_10 0x3fe28 575 #define ixSMU_PM_STATUS_11 0x3fe2c 576 #define ixSMU_PM_STATUS_12 0x3fe30 577 #define ixSMU_PM_STATUS_13 0x3fe34 578 #define ixSMU_PM_STATUS_14 0x3fe38 579 #define ixSMU_PM_STATUS_15 0x3fe3c 580 #define ixSMU_PM_STATUS_16 0x3fe40 581 #define ixSMU_PM_STATUS_17 0x3fe44 582 #define ixSMU_PM_STATUS_18 0x3fe48 583 #define ixSMU_PM_STATUS_19 0x3fe4c 584 #define ixSMU_PM_STATUS_20 0x3fe50 585 #define ixSMU_PM_STATUS_21 0x3fe54 586 #define ixSMU_PM_STATUS_22 0x3fe58 587 #define ixSMU_PM_STATUS_23 0x3fe5c 588 #define ixSMU_PM_STATUS_24 0x3fe60 589 #define ixSMU_PM_STATUS_25 0x3fe64 590 #define ixSMU_PM_STATUS_26 0x3fe68 591 #define ixSMU_PM_STATUS_27 0x3fe6c 592 #define ixSMU_PM_STATUS_28 0x3fe70 593 #define ixSMU_PM_STATUS_29 0x3fe74 594 #define ixSMU_PM_STATUS_30 0x3fe78 595 #define ixSMU_PM_STATUS_31 0x3fe7c 596 #define ixSMU_PM_STATUS_32 0x3fe80 597 #define ixSMU_PM_STATUS_33 0x3fe84 598 #define ixSMU_PM_STATUS_34 0x3fe88 599 #define ixSMU_PM_STATUS_35 0x3fe8c 600 #define ixSMU_PM_STATUS_36 0x3fe90 601 #define ixSMU_PM_STATUS_37 0x3fe94 602 #define ixSMU_PM_STATUS_38 0x3fe98 603 #define ixSMU_PM_STATUS_39 0x3fe9c 604 #define ixSMU_PM_STATUS_40 0x3fea0 605 #define ixSMU_PM_STATUS_41 0x3fea4 606 #define ixSMU_PM_STATUS_42 0x3fea8 607 #define ixSMU_PM_STATUS_43 0x3feac 608 #define ixSMU_PM_STATUS_44 0x3feb0 609 #define ixSMU_PM_STATUS_45 0x3feb4 610 #define ixSMU_PM_STATUS_46 0x3feb8 611 #define ixSMU_PM_STATUS_47 0x3febc 612 #define ixSMU_PM_STATUS_48 0x3fec0 613 #define ixSMU_PM_STATUS_49 0x3fec4 614 #define ixSMU_PM_STATUS_50 0x3fec8 615 #define ixSMU_PM_STATUS_51 0x3fecc 616 #define ixSMU_PM_STATUS_52 0x3fed0 617 #define ixSMU_PM_STATUS_53 0x3fed4 618 #define ixSMU_PM_STATUS_54 0x3fed8 619 #define ixSMU_PM_STATUS_55 0x3fedc 620 #define ixSMU_PM_STATUS_56 0x3fee0 621 #define ixSMU_PM_STATUS_57 0x3fee4 622 #define ixSMU_PM_STATUS_58 0x3fee8 623 #define ixSMU_PM_STATUS_59 0x3feec 624 #define ixSMU_PM_STATUS_60 0x3fef0 625 #define ixSMU_PM_STATUS_61 0x3fef4 626 #define ixSMU_PM_STATUS_62 0x3fef8 627 #define ixSMU_PM_STATUS_63 0x3fefc 628 #define ixSMU_PM_STATUS_64 0x3ff00 629 #define ixSMU_PM_STATUS_65 0x3ff04 630 #define ixSMU_PM_STATUS_66 0x3ff08 631 #define ixSMU_PM_STATUS_67 0x3ff0c 632 #define ixSMU_PM_STATUS_68 0x3ff10 633 #define ixSMU_PM_STATUS_69 0x3ff14 634 #define ixSMU_PM_STATUS_70 0x3ff18 635 #define ixSMU_PM_STATUS_71 0x3ff1c 636 #define ixSMU_PM_STATUS_72 0x3ff20 637 #define ixSMU_PM_STATUS_73 0x3ff24 638 #define ixSMU_PM_STATUS_74 0x3ff28 639 #define ixSMU_PM_STATUS_75 0x3ff2c 640 #define ixSMU_PM_STATUS_76 0x3ff30 641 #define ixSMU_PM_STATUS_77 0x3ff34 642 #define ixSMU_PM_STATUS_78 0x3ff38 643 #define ixSMU_PM_STATUS_79 0x3ff3c 644 #define ixSMU_PM_STATUS_80 0x3ff40 645 #define ixSMU_PM_STATUS_81 0x3ff44 646 #define ixSMU_PM_STATUS_82 0x3ff48 647 #define ixSMU_PM_STATUS_83 0x3ff4c 648 #define ixSMU_PM_STATUS_84 0x3ff50 649 #define ixSMU_PM_STATUS_85 0x3ff54 650 #define ixSMU_PM_STATUS_86 0x3ff58 651 #define ixSMU_PM_STATUS_87 0x3ff5c 652 #define ixSMU_PM_STATUS_88 0x3ff60 653 #define ixSMU_PM_STATUS_89 0x3ff64 654 #define ixSMU_PM_STATUS_90 0x3ff68 655 #define ixSMU_PM_STATUS_91 0x3ff6c 656 #define ixSMU_PM_STATUS_92 0x3ff70 657 #define ixSMU_PM_STATUS_93 0x3ff74 658 #define ixSMU_PM_STATUS_94 0x3ff78 659 #define ixSMU_PM_STATUS_95 0x3ff7c 660 #define ixSMU_PM_STATUS_96 0x3ff80 661 #define ixSMU_PM_STATUS_97 0x3ff84 662 #define ixSMU_PM_STATUS_98 0x3ff88 663 #define ixSMU_PM_STATUS_99 0x3ff8c 664 #define ixSMU_PM_STATUS_100 0x3ff90 665 #define ixSMU_PM_STATUS_101 0x3ff94 666 #define ixSMU_PM_STATUS_102 0x3ff98 667 #define ixSMU_PM_STATUS_103 0x3ff9c 668 #define ixSMU_PM_STATUS_104 0x3ffa0 669 #define ixSMU_PM_STATUS_105 0x3ffa4 670 #define ixSMU_PM_STATUS_106 0x3ffa8 671 #define ixSMU_PM_STATUS_107 0x3ffac 672 #define ixSMU_PM_STATUS_108 0x3ffb0 673 #define ixSMU_PM_STATUS_109 0x3ffb4 674 #define ixSMU_PM_STATUS_110 0x3ffb8 675 #define ixSMU_PM_STATUS_111 0x3ffbc 676 #define ixSMU_PM_STATUS_112 0x3ffc0 677 #define ixSMU_PM_STATUS_113 0x3ffc4 678 #define ixSMU_PM_STATUS_114 0x3ffc8 679 #define ixSMU_PM_STATUS_115 0x3ffcc 680 #define ixSMU_PM_STATUS_116 0x3ffd0 681 #define ixSMU_PM_STATUS_117 0x3ffd4 682 #define ixSMU_PM_STATUS_118 0x3ffd8 683 #define ixSMU_PM_STATUS_119 0x3ffdc 684 #define ixSMU_PM_STATUS_120 0x3ffe0 685 #define ixSMU_PM_STATUS_121 0x3ffe4 686 #define ixSMU_PM_STATUS_122 0x3ffe8 687 #define ixSMU_PM_STATUS_123 0x3ffec 688 #define ixSMU_PM_STATUS_124 0x3fff0 689 #define ixSMU_PM_STATUS_125 0x3fff4 690 #define ixSMU_PM_STATUS_126 0x3fff8 691 #define ixSMU_PM_STATUS_127 0x3fffc 692 #define ixCG_THERMAL_INT_ENA 0xc2100024 693 #define ixCG_THERMAL_INT_CTRL 0xc2100028 694 #define ixCG_THERMAL_INT_STATUS 0xc210002c 695 #define ixGENERAL_PWRMGT 0xc0200000 696 #define ixCNB_PWRMGT_CNTL 0xc0200004 697 #define ixSCLK_PWRMGT_CNTL 0xc0200008 698 #define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 699 #define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 700 #define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac 701 #define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 702 #define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 703 #define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 704 #define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc 705 #define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 706 #define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 707 #define ixPLL_TEST_CNTL 0xc020003c 708 #define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 709 #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 710 #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 711 #define ixCG_ACPI_CNTL 0xc0200064 712 #define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 713 #define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 714 #define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c 715 #define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 716 #define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c 717 #define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 718 #define ixSMU_VOLTAGE_STATUS 0xc0200094 719 #define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 720 #define ixCG_ULV_PARAMETER 0xc020015c 721 #define ixSCLK_MIN_DIV 0xc0200308 722 #define ixLCAC_SX0_CNTL 0xc0400d00 723 #define ixLCAC_SX0_OVR_SEL 0xc0400d04 724 #define ixLCAC_SX0_OVR_VAL 0xc0400d08 725 #define ixLCAC_MC0_CNTL 0xc0400d30 726 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 727 #define ixLCAC_MC0_OVR_VAL 0xc0400d38 728 #define ixLCAC_MC1_CNTL 0xc0400d3c 729 #define ixLCAC_MC1_OVR_SEL 0xc0400d40 730 #define ixLCAC_MC1_OVR_VAL 0xc0400d44 731 #define ixLCAC_MC2_CNTL 0xc0400d48 732 #define ixLCAC_MC2_OVR_SEL 0xc0400d4c 733 #define ixLCAC_MC2_OVR_VAL 0xc0400d50 734 #define ixLCAC_MC3_CNTL 0xc0400d54 735 #define ixLCAC_MC3_OVR_SEL 0xc0400d58 736 #define ixLCAC_MC3_OVR_VAL 0xc0400d5c 737 #define ixLCAC_CPL_CNTL 0xc0400d80 738 #define ixLCAC_CPL_OVR_SEL 0xc0400d84 739 #define ixLCAC_CPL_OVR_VAL 0xc0400d88 740 741 #endif /* SMU_7_0_0_D_H */ 742