1 /*********************************************************************
2 *
3 * Filename: smc-ircc.c
4 * Version: 0.4
5 * Description: Driver for the SMC Infrared Communications Controller
6 * Status: Experimental.
7 * Author: Thomas Davis (tadavis@jps.net)
8 * Created at:
9 * Modified at: Tue Feb 22 10:05:06 2000
10 * Modified by: Dag Brattli <dag@brattli.net>
11 * Modified at: Tue Jun 26 2001
12 * Modified by: Stefani Seibold <stefani@seibold.net>
13 * Modified at: Thur Apr 18 2002
14 * Modified by: Jeff Snyder <je4d@pobox.com>
15 *
16 * Copyright (c) 2001 Stefani Seibold
17 * Copyright (c) 1999-2001 Dag Brattli
18 * Copyright (c) 1998-1999 Thomas Davis,
19 * All Rights Reserved.
20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * MA 02111-1307 USA
35 *
36 * SIO's: all SIO documentet by SMC (June, 2001)
37 * Applicable Models : Fujitsu Lifebook 635t, Sony PCG-505TX,
38 * Dell Inspiron 8000
39 *
40 ********************************************************************/
41
42 #include <linux/module.h>
43 #include <linux/kernel.h>
44 #include <linux/types.h>
45 #include <linux/skbuff.h>
46 #include <linux/netdevice.h>
47 #include <linux/ioport.h>
48 #include <linux/delay.h>
49 #include <linux/slab.h>
50 #include <linux/init.h>
51 #include <linux/rtnetlink.h>
52 #include <linux/serial_reg.h>
53
54 #include <asm/io.h>
55 #include <asm/dma.h>
56 #include <asm/byteorder.h>
57
58 #include <linux/pm.h>
59
60 #include <net/irda/wrapper.h>
61 #include <net/irda/irda.h>
62 #include <net/irda/irmod.h>
63 #include <net/irda/irlap_frame.h>
64 #include <net/irda/irda_device.h>
65 #include <net/irda/smc-ircc.h>
66 #include <net/irda/irport.h>
67
68 struct smc_chip {
69 char *name;
70 u16 flags;
71 u8 devid;
72 u8 rev;
73 };
74 typedef struct smc_chip smc_chip_t;
75
76 static const char *driver_name = "smc-ircc";
77
78 #define DIM(x) (sizeof(x)/(sizeof(*(x))))
79
80 #define CHIP_IO_EXTENT 8
81
82 static struct ircc_cb *dev_self[] = { NULL, NULL};
83
84 /* Some prototypes */
85 static int ircc_open(unsigned int iobase, unsigned int board_addr);
86 static int ircc_dma_receive(struct ircc_cb *self, int iobase);
87 static void ircc_dma_receive_complete(struct ircc_cb *self, int iobase);
88 static int ircc_hard_xmit(struct sk_buff *skb, struct net_device *dev);
89 static void ircc_dma_xmit(struct ircc_cb *self, int iobase, int bofs);
90 static void ircc_change_speed(void *priv, u32 speed);
91 static void ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
92 static int ircc_net_open(struct net_device *dev);
93 static int ircc_net_close(struct net_device *dev);
94 static int ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
95
96 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
97 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
98 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
99 #define SIR 0 /* SuperIO Chip has only slow IRDA */
100 #define FIR 4 /* SuperIO Chip has fast IRDA */
101 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
102
103 /* These are the currently known SMC SuperIO chipsets */
104 static smc_chip_t __initdata fdc_chips_flat[]=
105 {
106 /* Base address 0x3f0 or 0x370 */
107 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip can not detected */
108 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
109 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
110 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
111 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
112 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
113 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
114 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
115 { NULL }
116 };
117
118 static smc_chip_t __initdata fdc_chips_paged[]=
119 {
120 /* Base address 0x3f0 or 0x370 */
121 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
122 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
123 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
124 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
125 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
126 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
127 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
128 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
129 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
130 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
131 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
132 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
133 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
134 { NULL }
135 };
136
137 static smc_chip_t __initdata lpc_chips_flat[]=
138 {
139 /* Base address 0x2E or 0x4E */
140 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
141 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
142 { NULL }
143 };
144
145 static smc_chip_t __initdata lpc_chips_paged[]=
146 {
147 /* Base address 0x2E or 0x4E */
148 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
149 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
150 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
151 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
152 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
153 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
154 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
155 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
156 { NULL }
157 };
158
159 static int ircc_irq=255;
160 static int ircc_dma=255;
161 static int ircc_fir=0;
162 static int ircc_sir=0;
163 static int ircc_cfg=0;
164
165 static unsigned short dev_count=0;
166
register_bank(int iobase,int bank)167 static inline void register_bank(int iobase, int bank)
168 {
169 outb(((inb(iobase+IRCC_MASTER) & 0xf0) | (bank & 0x07)),
170 iobase+IRCC_MASTER);
171 }
172
smc_access(unsigned short cfg_base,unsigned char reg)173 static int __init smc_access(unsigned short cfg_base,unsigned char reg)
174 {
175 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
176
177 outb(reg, cfg_base);
178
179 if (inb(cfg_base)!=reg)
180 return -1;
181
182 return 0;
183 }
184
smc_probe(unsigned short cfg_base,u8 reg,const smc_chip_t * chip,char * type)185 static const smc_chip_t * __init smc_probe(unsigned short cfg_base,u8 reg,const smc_chip_t *chip,char *type)
186 {
187 u8 devid,xdevid,rev;
188
189 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
190
191 /* Leave configuration */
192
193 outb(0xaa, cfg_base);
194
195 if (inb(cfg_base)==0xaa) /* not a smc superio chip */
196 return NULL;
197
198 outb(reg, cfg_base);
199
200 xdevid=inb(cfg_base+1);
201
202 /* Enter configuration */
203
204 outb(0x55, cfg_base);
205
206 if (smc_access(cfg_base,0x55)) /* send second key and check */
207 return NULL;
208
209 /* probe device ID */
210
211 if (smc_access(cfg_base,reg))
212 return NULL;
213
214 devid=inb(cfg_base+1);
215
216 if (devid==0) /* typical value for unused port */
217 return NULL;
218
219 if (devid==0xff) /* typical value for unused port */
220 return NULL;
221
222 /* probe revision ID */
223
224 if (smc_access(cfg_base,reg+1))
225 return NULL;
226
227 rev=inb(cfg_base+1);
228
229 if (rev>=128) /* i think this will make no sense */
230 return NULL;
231
232 if (devid==xdevid) /* protection against false positives */
233 return NULL;
234
235 /* Check for expected device ID; are there others? */
236
237 while(chip->devid!=devid) {
238
239 chip++;
240
241 if (chip->name==NULL)
242 return NULL;
243 }
244 if (chip->rev>rev)
245 return NULL;
246
247 MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",devid,rev,cfg_base,type,chip->name);
248
249 if (chip->flags&NoIRDA)
250 MESSAGE("chipset does not support IRDA\n");
251
252 return chip;
253 }
254
255 /*
256 * Function smc_superio_flat (chip, base, type)
257 *
258 * Try get configuration of a smc SuperIO chip with flat register model
259 *
260 */
smc_superio_flat(const smc_chip_t * chips,unsigned short cfg_base,char * type)261 static int __init smc_superio_flat(const smc_chip_t *chips, unsigned short cfg_base, char *type)
262 {
263 unsigned short fir_io;
264 unsigned short sir_io;
265 u8 mode;
266 int ret = -ENODEV;
267
268 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
269
270 if (smc_probe(cfg_base,0xD,chips,type)==NULL)
271 return ret;
272
273 outb(0x0c, cfg_base);
274
275 mode = inb(cfg_base+1);
276 mode = (mode & 0x38) >> 3;
277
278 /* Value for IR port */
279 if (mode && mode < 4) {
280 /* SIR iobase */
281 outb(0x25, cfg_base);
282 sir_io = inb(cfg_base+1) << 2;
283
284 /* FIR iobase */
285 outb(0x2b, cfg_base);
286 fir_io = inb(cfg_base+1) << 3;
287
288 if (fir_io) {
289 if (ircc_open(fir_io, sir_io) == 0)
290 ret=0;
291 }
292 }
293
294 /* Exit configuration */
295 outb(0xaa, cfg_base);
296
297 return ret;
298 }
299
300 /*
301 * Function smc_superio_paged (chip, base, type)
302 *
303 * Try get configuration of a smc SuperIO chip with paged register model
304 *
305 */
smc_superio_paged(const smc_chip_t * chips,unsigned short cfg_base,char * type)306 static int __init smc_superio_paged(const smc_chip_t *chips, unsigned short cfg_base, char *type)
307 {
308 unsigned short fir_io;
309 unsigned short sir_io;
310 int ret = -ENODEV;
311
312 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
313
314 if (smc_probe(cfg_base,0x20,chips,type)==NULL)
315 return ret;
316
317 /* Select logical device (UART2) */
318 outb(0x07, cfg_base);
319 outb(0x05, cfg_base + 1);
320
321 /* SIR iobase */
322 outb(0x60, cfg_base);
323 sir_io = inb(cfg_base + 1) << 8;
324 outb(0x61, cfg_base);
325 sir_io |= inb(cfg_base + 1);
326
327 /* Read FIR base */
328 outb(0x62, cfg_base);
329 fir_io = inb(cfg_base + 1) << 8;
330 outb(0x63, cfg_base);
331 fir_io |= inb(cfg_base + 1);
332 outb(0x2b, cfg_base); /* ??? */
333
334 if (fir_io) {
335 if (ircc_open(fir_io, sir_io) == 0)
336 ret=0;
337 }
338
339 /* Exit configuration */
340 outb(0xaa, cfg_base);
341
342 return ret;
343 }
344
smc_superio_fdc(unsigned short cfg_base)345 static int __init smc_superio_fdc(unsigned short cfg_base)
346 {
347 if (check_region(cfg_base, 2) < 0) {
348 IRDA_DEBUG(0, "%s: can't get cfg_base of 0x%03x\n",
349 __FUNCTION__, cfg_base);
350 return -1;
351 }
352
353 if (!smc_superio_flat(fdc_chips_flat,cfg_base,"FDC")||!smc_superio_paged(fdc_chips_paged,cfg_base,"FDC"))
354 return 0;
355
356 return -1;
357 }
358
smc_superio_lpc(unsigned short cfg_base)359 static int __init smc_superio_lpc(unsigned short cfg_base)
360 {
361 #if 0
362 if (check_region(cfg_base, 2) < 0) {
363 IRDA_DEBUG(0, "%s: can't get cfg_base of 0x%03x\n",
364 __FUNCTION__, cfg_base);
365 return -1;
366 }
367 #endif
368
369 if (!smc_superio_flat(lpc_chips_flat,cfg_base,"LPC")||!smc_superio_paged(lpc_chips_paged,cfg_base,"LPC"))
370 return 0;
371
372 return -1;
373 }
374
375 /*
376 * Function ircc_init ()
377 *
378 * Initialize chip. Just try to find out how many chips we are dealing with
379 * and where they are
380 */
ircc_init(void)381 int __init ircc_init(void)
382 {
383 int ret=-ENODEV;
384
385 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
386
387 dev_count=0;
388
389 if ((ircc_fir>0)&&(ircc_sir>0)) {
390 MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
391 MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
392
393 if (ircc_open(ircc_fir, ircc_sir) == 0)
394 return 0;
395
396 return -ENODEV;
397 }
398
399 /* try user provided configuration register base address */
400 if (ircc_cfg>0) {
401 MESSAGE(" Overriding configuration address 0x%04x\n", ircc_cfg);
402 if (!smc_superio_fdc(ircc_cfg))
403 ret=0;
404 }
405
406 /* Trys to open for all the SMC chipsets we know about */
407
408 IRDA_DEBUG(0, "%s Try to open all known SMC chipsets\n", __FUNCTION__);
409
410 if (!smc_superio_fdc(0x3f0))
411 ret=0;
412 if (!smc_superio_fdc(0x370))
413 ret=0;
414 if (!smc_superio_fdc(0xe0))
415 ret=0;
416 if (!smc_superio_lpc(0x2e))
417 ret=0;
418 if (!smc_superio_lpc(0x4e))
419 ret=0;
420
421 return ret;
422 }
423
424 /*
425 * Function ircc_open (iobase, irq)
426 *
427 * Try to open driver instance
428 *
429 */
ircc_open(unsigned int fir_base,unsigned int sir_base)430 static int __init ircc_open(unsigned int fir_base, unsigned int sir_base)
431 {
432 struct ircc_cb *self;
433 struct irport_cb *irport;
434 unsigned char low, high, chip, config, dma, irq, version;
435
436
437 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
438
439 if (check_region(fir_base, CHIP_IO_EXTENT) < 0) {
440 IRDA_DEBUG(0, "%s: can't get fir_base of 0x%03x\n",
441 __FUNCTION__, fir_base);
442 return -ENODEV;
443 }
444 #if POSSIBLE_USED_BY_SERIAL_DRIVER
445 if (check_region(sir_base, CHIP_IO_EXTENT) < 0) {
446 IRDA_DEBUG(0, "%s: can't get sir_base of 0x%03x\n",
447 __FUNCTION__, sir_base);
448 return -ENODEV;
449 }
450 #endif
451
452 register_bank(fir_base, 3);
453
454 high = inb(fir_base+IRCC_ID_HIGH);
455 low = inb(fir_base+IRCC_ID_LOW);
456 chip = inb(fir_base+IRCC_CHIP_ID);
457 version = inb(fir_base+IRCC_VERSION);
458 config = inb(fir_base+IRCC_INTERFACE);
459
460 irq = config >> 4 & 0x0f;
461 dma = config & 0x0f;
462
463 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
464 IRDA_DEBUG(0, "%s(), addr 0x%04x - no device found!\n",
465 __FUNCTION__, fir_base);
466 return -ENODEV;
467 }
468 MESSAGE("SMC IrDA Controller found\n IrCC version %d.%d, "
469 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
470 chip & 0x0f, version, fir_base, sir_base, dma, irq);
471
472 if (dev_count>DIM(dev_self)) {
473 IRDA_DEBUG(0, "%s(), to many devices!\n", __FUNCTION__);
474 return -ENOMEM;
475 }
476
477 /*
478 * Allocate new instance of the driver
479 */
480 self = kmalloc(sizeof(struct ircc_cb), GFP_KERNEL);
481 if (self == NULL) {
482 ERROR("%s, Can't allocate memory for control block!\n",
483 driver_name);
484 return -ENOMEM;
485 }
486 memset(self, 0, sizeof(struct ircc_cb));
487 spin_lock_init(&self->lock);
488
489 /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
490 self->rx_buff.truesize = 4000;
491 self->tx_buff.truesize = 4000;
492
493 self->rx_buff.head = (u8 *) kmalloc(self->rx_buff.truesize,
494 GFP_KERNEL|GFP_DMA);
495 if (self->rx_buff.head == NULL) {
496 ERROR("%s, Can't allocate memory for receive buffer!\n",
497 driver_name);
498 kfree(self);
499 return -ENOMEM;
500 }
501
502 self->tx_buff.head = (u8 *) kmalloc(self->tx_buff.truesize,
503 GFP_KERNEL|GFP_DMA);
504 if (self->tx_buff.head == NULL) {
505 ERROR("%s, Can't allocate memory for transmit buffer!\n",
506 driver_name);
507 kfree(self->rx_buff.head);
508 kfree(self);
509 return -ENOMEM;
510 }
511
512 irport = irport_open(dev_count, sir_base, irq);
513 if (!irport) {
514 kfree(self->tx_buff.head);
515 kfree(self->rx_buff.head);
516 kfree(self);
517 return -ENODEV;
518 }
519
520 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
521 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
522
523 /* Need to store self somewhere */
524 dev_self[dev_count++] = self;
525
526 /* Steal the network device from irport */
527 self->netdev = irport->netdev;
528 self->irport = irport;
529
530 irport->priv = self;
531
532 /* Initialize IO */
533 self->io = &irport->io;
534 self->io->fir_base = fir_base;
535 self->io->sir_base = sir_base; /* Used by irport */
536 self->io->fir_ext = CHIP_IO_EXTENT;
537 self->io->sir_ext = 8; /* Used by irport */
538
539 if (ircc_irq < 255) {
540 if (ircc_irq!=irq)
541 MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
542 driver_name, irq, ircc_irq);
543 self->io->irq = ircc_irq;
544 }
545 else
546 self->io->irq = irq;
547 if (ircc_dma < 255) {
548 if (ircc_dma!=dma)
549 MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
550 driver_name, dma, ircc_dma);
551 self->io->dma = ircc_dma;
552 }
553 else
554 self->io->dma = dma;
555
556 request_region(self->io->fir_base, CHIP_IO_EXTENT, driver_name);
557
558 /* Initialize QoS for this device */
559 irda_init_max_qos_capabilies(&irport->qos);
560
561 /* The only value we must override it the baudrate */
562 irport->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
563 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
564
565 irport->qos.min_turn_time.bits = 0x07;
566 irport->qos.window_size.bits = 0x01;
567 irda_qos_bits_to_value(&irport->qos);
568
569 irport->flags = IFF_FIR|IFF_MIR|IFF_SIR|IFF_DMA|IFF_PIO;
570
571
572 self->rx_buff.in_frame = FALSE;
573 self->rx_buff.state = OUTSIDE_FRAME;
574 self->tx_buff.data = self->tx_buff.head;
575 self->rx_buff.data = self->rx_buff.head;
576
577 /* Override the speed change function, since we must control it now */
578 irport->change_speed = &ircc_change_speed;
579 irport->interrupt = &ircc_interrupt;
580 self->netdev->open = &ircc_net_open;
581 self->netdev->stop = &ircc_net_close;
582
583 irport_start(self->irport);
584
585 self->pmdev = pm_register(PM_SYS_DEV, PM_SYS_IRDA, ircc_pmproc);
586 if (self->pmdev)
587 self->pmdev->data = self;
588
589 /* Power on device */
590
591 outb(0x00, fir_base+IRCC_MASTER);
592
593 return 0;
594 }
595
596 /*
597 * Function ircc_change_speed (self, baud)
598 *
599 * Change the speed of the device
600 *
601 */
ircc_change_speed(void * priv,u32 speed)602 static void ircc_change_speed(void *priv, u32 speed)
603 {
604 int iobase, ir_mode, ctrl, fast;
605 struct ircc_cb *self = (struct ircc_cb *) priv;
606 struct net_device *dev;
607
608 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
609
610 ASSERT(self != NULL, return;);
611
612 dev = self->netdev;
613 iobase = self->io->fir_base;
614
615 /* Update accounting for new speed */
616 self->io->speed = speed;
617
618 outb(IRCC_MASTER_RESET, iobase+IRCC_MASTER);
619 outb(0x00, iobase+IRCC_MASTER);
620
621 switch (speed) {
622 default:
623 IRDA_DEBUG(0, "%s(), unknown baud rate of %d\n",
624 __FUNCTION__, speed);
625 /* FALLTHROUGH */
626 case 9600:
627 case 19200:
628 case 38400:
629 case 57600:
630 case 115200:
631 ir_mode = IRCC_CFGA_IRDA_SIR_A;
632 ctrl = 0;
633 fast = 0;
634 break;
635 case 576000:
636 ir_mode = IRCC_CFGA_IRDA_HDLC;
637 ctrl = IRCC_CRC;
638 fast = 0;
639 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
640 break;
641 case 1152000:
642 ir_mode = IRCC_CFGA_IRDA_HDLC;
643 ctrl = IRCC_1152 | IRCC_CRC;
644 fast = 0;
645 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", __FUNCTION__);
646 break;
647 case 4000000:
648 ir_mode = IRCC_CFGA_IRDA_4PPM;
649 ctrl = IRCC_CRC;
650 fast = IRCC_LCR_A_FAST;
651 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", __FUNCTION__);
652 break;
653 }
654
655 register_bank(iobase, 0);
656 outb(0, iobase+IRCC_IER);
657 outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER);
658
659 /* Make special FIR init if necessary */
660 if (speed > 115200) {
661 irport_stop(self->irport);
662
663 /* Install FIR transmit handler */
664 dev->hard_start_xmit = &ircc_hard_xmit;
665
666 /*
667 * Don't know why we have to do this, but FIR interrupts
668 * stops working if we remove it.
669 */
670 /* outb(UART_MCR_OUT2, self->io->sir_base + UART_MCR); */
671
672 /* Be ready for incoming frames */
673 ircc_dma_receive(self, iobase);
674 } else {
675 /* Install SIR transmit handler */
676 dev->hard_start_xmit = &irport_hard_xmit;
677 irport_start(self->irport);
678
679 IRDA_DEBUG(0, "%s(), using irport to change speed to %d\n", __FUNCTION__, speed);
680 irport_change_speed(self->irport, speed);
681 }
682
683 register_bank(iobase, 1);
684 outb(((inb(iobase+IRCC_SCE_CFGA) & 0x87) | ir_mode),
685 iobase+IRCC_SCE_CFGA);
686
687 #ifdef SMC_669 /* Uses pin 88/89 for Rx/Tx */
688 outb(((inb(iobase+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
689 iobase+IRCC_SCE_CFGB);
690 #else
691 outb(((inb(iobase+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
692 iobase+IRCC_SCE_CFGB);
693 #endif
694 (void) inb(iobase+IRCC_FIFO_THRESHOLD);
695 outb(64, iobase+IRCC_FIFO_THRESHOLD);
696
697 register_bank(iobase, 4);
698 outb((inb(iobase+IRCC_CONTROL) & 0x30) | ctrl, iobase+IRCC_CONTROL);
699
700 register_bank(iobase, 0);
701 outb(fast, iobase+IRCC_LCR_A);
702
703 netif_start_queue(dev);
704 }
705
706 /*
707 * Function ircc_hard_xmit (skb, dev)
708 *
709 * Transmit the frame!
710 *
711 */
ircc_hard_xmit(struct sk_buff * skb,struct net_device * dev)712 static int ircc_hard_xmit(struct sk_buff *skb, struct net_device *dev)
713 {
714 struct irport_cb *irport;
715 struct ircc_cb *self;
716 unsigned long flags;
717 s32 speed;
718 int iobase;
719 int mtt;
720
721 irport = (struct irport_cb *) dev->priv;
722 self = (struct ircc_cb *) irport->priv;
723 ASSERT(self != NULL, return 0;);
724
725 iobase = self->io->fir_base;
726
727 netif_stop_queue(dev);
728
729 /* Check if we need to change the speed after this frame */
730 speed = irda_get_next_speed(skb);
731 if ((speed != self->io->speed) && (speed != -1)) {
732 /* Check for empty frame */
733 if (!skb->len) {
734 ircc_change_speed(self, speed);
735 dev_kfree_skb(skb);
736 return 0;
737 } else
738 self->new_speed = speed;
739 }
740
741 spin_lock_irqsave(&self->lock, flags);
742
743 memcpy(self->tx_buff.head, skb->data, skb->len);
744
745 self->tx_buff.len = skb->len;
746 self->tx_buff.data = self->tx_buff.head;
747
748 mtt = irda_get_mtt(skb);
749 if (mtt) {
750 int bofs;
751
752 /*
753 * Compute how many BOFs (STA or PA's) we need to waste the
754 * min turn time given the speed of the link.
755 */
756 bofs = mtt * (self->io->speed / 1000) / 8000;
757 if (bofs > 4095)
758 bofs = 4095;
759
760 ircc_dma_xmit(self, iobase, bofs);
761 } else {
762 /* Transmit frame */
763 ircc_dma_xmit(self, iobase, 0);
764 }
765 spin_unlock_irqrestore(&self->lock, flags);
766 dev_kfree_skb(skb);
767
768 return 0;
769 }
770
771 /*
772 * Function ircc_dma_xmit (self, iobase)
773 *
774 * Transmit data using DMA
775 *
776 */
ircc_dma_xmit(struct ircc_cb * self,int iobase,int bofs)777 static void ircc_dma_xmit(struct ircc_cb *self, int iobase, int bofs)
778 {
779 u8 ctrl;
780
781 IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
782 #if 0
783 /* Disable Rx */
784 register_bank(iobase, 0);
785 outb(0x00, iobase+IRCC_LCR_B);
786 #endif
787 register_bank(iobase, 1);
788 outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
789 iobase+IRCC_SCE_CFGB);
790
791 self->io->direction = IO_XMIT;
792
793 /* Set BOF additional count for generating the min turn time */
794 register_bank(iobase, 4);
795 outb(bofs & 0xff, iobase+IRCC_BOF_COUNT_LO);
796 ctrl = inb(iobase+IRCC_CONTROL) & 0xf0;
797 outb(ctrl | ((bofs >> 8) & 0x0f), iobase+IRCC_BOF_COUNT_HI);
798
799 /* Set max Tx frame size */
800 outb(self->tx_buff.len >> 8, iobase+IRCC_TX_SIZE_HI);
801 outb(self->tx_buff.len & 0xff, iobase+IRCC_TX_SIZE_LO);
802
803 /* Setup DMA controller (must be done after enabling chip DMA) */
804 setup_dma(self->io->dma, self->tx_buff.data, self->tx_buff.len,
805 DMA_TX_MODE);
806
807 outb(UART_MCR_OUT2, self->io->sir_base + UART_MCR);
808 /* Enable burst mode chip Tx DMA */
809 register_bank(iobase, 1);
810 outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
811 IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB);
812
813 /* Enable interrupt */
814 outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER);
815 register_bank(iobase, 0);
816 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER);
817
818 /* Enable transmit */
819 outb(IRCC_LCR_B_SCE_TRANSMIT|IRCC_LCR_B_SIP_ENABLE, iobase+IRCC_LCR_B);
820 }
821
822 /*
823 * Function ircc_dma_xmit_complete (self)
824 *
825 * The transfer of a frame in finished. This function will only be called
826 * by the interrupt handler
827 *
828 */
ircc_dma_xmit_complete(struct ircc_cb * self,int iobase)829 static void ircc_dma_xmit_complete(struct ircc_cb *self, int iobase)
830 {
831 IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
832 #if 0
833 /* Disable Tx */
834 register_bank(iobase, 0);
835 outb(0x00, iobase+IRCC_LCR_B);
836 #endif
837 register_bank(self->io->fir_base, 1);
838 outb(inb(self->io->fir_base+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
839 self->io->fir_base+IRCC_SCE_CFGB);
840
841 /* Check for underrrun! */
842 register_bank(iobase, 0);
843 if (inb(iobase+IRCC_LSR) & IRCC_LSR_UNDERRUN) {
844 self->irport->stats.tx_errors++;
845 self->irport->stats.tx_fifo_errors++;
846
847 /* Reset error condition */
848 register_bank(iobase, 0);
849 outb(IRCC_MASTER_ERROR_RESET, iobase+IRCC_MASTER);
850 outb(0x00, iobase+IRCC_MASTER);
851 } else {
852 self->irport->stats.tx_packets++;
853 self->irport->stats.tx_bytes += self->tx_buff.len;
854 }
855
856 /* Check if it's time to change the speed */
857 if (self->new_speed) {
858 ircc_change_speed(self, self->new_speed);
859 self->new_speed = 0;
860 }
861
862 netif_wake_queue(self->netdev);
863 }
864
865 /*
866 * Function ircc_dma_receive (self)
867 *
868 * Get ready for receiving a frame. The device will initiate a DMA
869 * if it starts to receive a frame.
870 *
871 */
ircc_dma_receive(struct ircc_cb * self,int iobase)872 static int ircc_dma_receive(struct ircc_cb *self, int iobase)
873 {
874 #if 0
875 /* Turn off chip DMA */
876 register_bank(iobase, 1);
877 outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
878 iobase+IRCC_SCE_CFGB);
879 #endif
880 setup_dma(self->io->dma, self->rx_buff.data, self->rx_buff.truesize,
881 DMA_RX_MODE);
882
883 /* Set max Rx frame size */
884 register_bank(iobase, 4);
885 outb((2050 >> 8) & 0x0f, iobase+IRCC_RX_SIZE_HI);
886 outb(2050 & 0xff, iobase+IRCC_RX_SIZE_LO);
887
888 self->io->direction = IO_RECV;
889 self->rx_buff.data = self->rx_buff.head;
890
891 /* Setup DMA controller */
892
893 /* Enable receiver */
894 register_bank(iobase, 0);
895 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
896 iobase+IRCC_LCR_B);
897
898 /* Enable burst mode chip Rx DMA */
899 register_bank(iobase, 1);
900 outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
901 IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB);
902
903 return 0;
904 }
905
906 /*
907 * Function ircc_dma_receive_complete (self)
908 *
909 * Finished with receiving frames
910 *
911 */
ircc_dma_receive_complete(struct ircc_cb * self,int iobase)912 static void ircc_dma_receive_complete(struct ircc_cb *self, int iobase)
913 {
914 struct sk_buff *skb;
915 int len, msgcnt;
916
917 IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
918 #if 0
919 /* Disable Rx */
920 register_bank(iobase, 0);
921 outb(0x00, iobase+IRCC_LCR_B);
922 #endif
923 register_bank(iobase, 0);
924 msgcnt = inb(iobase+IRCC_LCR_B) & 0x08;
925
926 IRDA_DEBUG(2, "%s: dma count = %d\n",
927 __FUNCTION__, get_dma_residue(self->io->dma));
928
929 len = self->rx_buff.truesize - get_dma_residue(self->io->dma);
930
931 /* Remove CRC */
932 if (self->io->speed < 4000000)
933 len -= 2;
934 else
935 len -= 4;
936
937 if ((len < 2) || (len > 2050)) {
938 WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
939 return;
940 }
941 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
942
943 skb = dev_alloc_skb(len+1);
944 if (!skb) {
945 WARNING("%s(), memory squeeze, dropping frame.\n", __FUNCTION__);
946 return;
947 }
948 /* Make sure IP header gets aligned */
949 skb_reserve(skb, 1);
950
951 memcpy(skb_put(skb, len), self->rx_buff.data, len);
952 self->irport->stats.rx_packets++;
953 self->irport->stats.rx_bytes += len;
954
955 skb->dev = self->netdev;
956 skb->mac.raw = skb->data;
957 skb->protocol = htons(ETH_P_IRDA);
958 netif_rx(skb);
959 }
960
961 /*
962 * Function ircc_interrupt (irq, dev_id, regs)
963 *
964 * An interrupt from the chip has arrived. Time to do some work
965 *
966 */
ircc_interrupt(int irq,void * dev_id,struct pt_regs * regs)967 static void ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
968 {
969 struct net_device *dev = (struct net_device *) dev_id;
970 struct irport_cb *irport;
971 struct ircc_cb *self;
972 int iobase, iir;
973
974 if (dev == NULL) {
975 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
976 driver_name, irq);
977 return;
978 }
979 irport = (struct irport_cb *) dev->priv;
980 ASSERT(irport != NULL, return;);
981 self = (struct ircc_cb *) irport->priv;
982 ASSERT(self != NULL, return;);
983
984 /* Check if we should use the SIR interrupt handler */
985 if (self->io->speed < 576000) {
986 irport_interrupt(irq, dev_id, regs);
987 return;
988 }
989 iobase = self->io->fir_base;
990
991 spin_lock(&self->lock);
992
993 register_bank(iobase, 0);
994 iir = inb(iobase+IRCC_IIR);
995
996 /* Disable interrupts */
997 outb(0, iobase+IRCC_IER);
998
999 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1000
1001 if (iir & IRCC_IIR_EOM) {
1002 if (self->io->direction == IO_RECV)
1003 ircc_dma_receive_complete(self, iobase);
1004 else
1005 ircc_dma_xmit_complete(self, iobase);
1006
1007 ircc_dma_receive(self, iobase);
1008 }
1009
1010 /* Enable interrupts again */
1011 register_bank(iobase, 0);
1012 outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, iobase+IRCC_IER);
1013
1014 spin_unlock(&self->lock);
1015 }
1016
1017 #if 0 /* unused */
1018 /*
1019 * Function ircc_is_receiving (self)
1020 *
1021 * Return TRUE is we are currently receiving a frame
1022 *
1023 */
1024 static int ircc_is_receiving(struct ircc_cb *self)
1025 {
1026 int status = FALSE;
1027 /* int iobase; */
1028
1029 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
1030
1031 ASSERT(self != NULL, return FALSE;);
1032
1033 IRDA_DEBUG(0, "%s: dma count = %d\n",
1034 __FUNCTION__, get_dma_residue(self->io->dma));
1035
1036 status = (self->rx_buff.state != OUTSIDE_FRAME);
1037
1038 return status;
1039 }
1040 #endif /* unused */
1041
1042 /*
1043 * Function ircc_net_open (dev)
1044 *
1045 * Start the device
1046 *
1047 */
ircc_net_open(struct net_device * dev)1048 static int ircc_net_open(struct net_device *dev)
1049 {
1050 struct irport_cb *irport;
1051 struct ircc_cb *self;
1052 int iobase;
1053
1054 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
1055
1056 ASSERT(dev != NULL, return -1;);
1057 irport = (struct irport_cb *) dev->priv;
1058 self = (struct ircc_cb *) irport->priv;
1059
1060 ASSERT(self != NULL, return 0;);
1061
1062 iobase = self->io->fir_base;
1063
1064 irport_net_open(dev); /* irport allocates the irq */
1065
1066 /*
1067 * Always allocate the DMA channel after the IRQ,
1068 * and clean up on failure.
1069 */
1070 if (request_dma(self->io->dma, dev->name)) {
1071 irport_net_close(dev);
1072
1073 WARNING("%s(), unable to allocate DMA=%d\n", __FUNCTION__, self->io->dma);
1074 return -EAGAIN;
1075 }
1076
1077 MOD_INC_USE_COUNT;
1078
1079 return 0;
1080 }
1081
1082 /*
1083 * Function ircc_net_close (dev)
1084 *
1085 * Stop the device
1086 *
1087 */
ircc_net_close(struct net_device * dev)1088 static int ircc_net_close(struct net_device *dev)
1089 {
1090 struct irport_cb *irport;
1091 struct ircc_cb *self;
1092 int iobase;
1093
1094 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
1095
1096 ASSERT(dev != NULL, return -1;);
1097 irport = (struct irport_cb *) dev->priv;
1098 self = (struct ircc_cb *) irport->priv;
1099
1100 ASSERT(self != NULL, return 0;);
1101
1102 iobase = self->io->fir_base;
1103
1104 irport_net_close(dev);
1105
1106 disable_dma(self->io->dma);
1107
1108 free_dma(self->io->dma);
1109
1110 MOD_DEC_USE_COUNT;
1111
1112 return 0;
1113 }
1114
ircc_suspend(struct ircc_cb * self)1115 static void ircc_suspend(struct ircc_cb *self)
1116 {
1117 MESSAGE("%s, Suspending\n", driver_name);
1118
1119 if (self->io->suspended)
1120 return;
1121
1122 ircc_net_close(self->netdev);
1123
1124 self->io->suspended = 1;
1125 }
1126
ircc_wakeup(struct ircc_cb * self)1127 static void ircc_wakeup(struct ircc_cb *self)
1128 {
1129 unsigned long flags;
1130
1131 if (!self->io->suspended)
1132 return;
1133
1134 save_flags(flags);
1135 cli();
1136
1137 ircc_net_open(self->netdev);
1138
1139 restore_flags(flags);
1140 MESSAGE("%s, Waking up\n", driver_name);
1141 }
1142
ircc_pmproc(struct pm_dev * dev,pm_request_t rqst,void * data)1143 static int ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data)
1144 {
1145 struct ircc_cb *self = (struct ircc_cb*) dev->data;
1146 if (self) {
1147 switch (rqst) {
1148 case PM_SUSPEND:
1149 ircc_suspend(self);
1150 break;
1151 case PM_RESUME:
1152 ircc_wakeup(self);
1153 break;
1154 }
1155 }
1156 return 0;
1157 }
1158
1159 #ifdef MODULE
1160
1161 /*
1162 * Function ircc_close (self)
1163 *
1164 * Close driver instance
1165 *
1166 */
1167 #ifdef MODULE
ircc_close(struct ircc_cb * self)1168 static int __exit ircc_close(struct ircc_cb *self)
1169 {
1170 int iobase;
1171
1172 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
1173
1174 ASSERT(self != NULL, return -1;);
1175
1176 iobase = self->irport->io.fir_base;
1177
1178 irport_close(self->irport);
1179
1180 /* Stop interrupts */
1181 register_bank(iobase, 0);
1182 outb(0, iobase+IRCC_IER);
1183 outb(IRCC_MASTER_RESET, iobase+IRCC_MASTER);
1184 outb(0x00, iobase+IRCC_MASTER);
1185 #if 0
1186 /* Reset to SIR mode */
1187 register_bank(iobase, 1);
1188 outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase+IRCC_SCE_CFGA);
1189 outb(IRCC_CFGB_IR, iobase+IRCC_SCE_CFGB);
1190 #endif
1191 /* Release the PORT that this driver is using */
1192 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__, iobase);
1193
1194 release_region(iobase, CHIP_IO_EXTENT);
1195
1196 if (self->tx_buff.head)
1197 kfree(self->tx_buff.head);
1198
1199 if (self->rx_buff.head)
1200 kfree(self->rx_buff.head);
1201
1202 kfree(self);
1203
1204 return 0;
1205 }
1206 #endif /* MODULE */
1207
smc_init(void)1208 static int __init smc_init(void)
1209 {
1210 return ircc_init();
1211 }
1212
smc_cleanup(void)1213 static void __exit smc_cleanup(void)
1214 {
1215 int i;
1216
1217 IRDA_DEBUG(0, "%s()\n", __FUNCTION__);
1218
1219 for (i=0; i < 2; i++) {
1220 if (dev_self[i])
1221 ircc_close(dev_self[i]);
1222 }
1223 }
1224
1225 module_init(smc_init);
1226 module_exit(smc_cleanup);
1227
1228 MODULE_AUTHOR("Thomas Davis <tadavis@jps.net>");
1229 MODULE_DESCRIPTION("SMC IrCC controller driver");
1230 MODULE_LICENSE("GPL");
1231
1232 MODULE_PARM(ircc_dma, "1i");
1233 MODULE_PARM_DESC(ircc_dma, "DMA channel");
1234 MODULE_PARM(ircc_irq, "1i");
1235 MODULE_PARM_DESC(ircc_irq, "IRQ line");
1236 MODULE_PARM(ircc_fir, "1-4i");
1237 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
1238 MODULE_PARM(ircc_sir, "1-4i");
1239 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
1240 MODULE_PARM(ircc_cfg, "1-4i");
1241 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
1242
1243 #endif /* MODULE */
1244