1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm8250.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/soc/qcom,apr.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/sound/qcom,q6afe.h> 20#include <dt-bindings/thermal/thermal.h> 21#include <dt-bindings/clock/qcom,camcc-sm8250.h> 22#include <dt-bindings/clock/qcom,videocc-sm8250.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 i2c16 = &i2c16; 48 i2c17 = &i2c17; 49 i2c18 = &i2c18; 50 i2c19 = &i2c19; 51 spi0 = &spi0; 52 spi1 = &spi1; 53 spi2 = &spi2; 54 spi3 = &spi3; 55 spi4 = &spi4; 56 spi5 = &spi5; 57 spi6 = &spi6; 58 spi7 = &spi7; 59 spi8 = &spi8; 60 spi9 = &spi9; 61 spi10 = &spi10; 62 spi11 = &spi11; 63 spi12 = &spi12; 64 spi13 = &spi13; 65 spi14 = &spi14; 66 spi15 = &spi15; 67 spi16 = &spi16; 68 spi17 = &spi17; 69 spi18 = &spi18; 70 spi19 = &spi19; 71 }; 72 73 chosen { }; 74 75 clocks { 76 xo_board: xo-board { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <38400000>; 80 clock-output-names = "xo_board"; 81 }; 82 83 sleep_clk: sleep-clk { 84 compatible = "fixed-clock"; 85 clock-frequency = <32768>; 86 #clock-cells = <0>; 87 }; 88 }; 89 90 cpus { 91 #address-cells = <2>; 92 #size-cells = <0>; 93 94 CPU0: cpu@0 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo485"; 97 reg = <0x0 0x0>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <448>; 100 dynamic-power-coefficient = <205>; 101 next-level-cache = <&L2_0>; 102 power-domains = <&CPU_PD0>; 103 power-domain-names = "psci"; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 operating-points-v2 = <&cpu0_opp_table>; 106 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 107 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 108 #cooling-cells = <2>; 109 L2_0: l2-cache { 110 compatible = "cache"; 111 next-level-cache = <&L3_0>; 112 L3_0: l3-cache { 113 compatible = "cache"; 114 }; 115 }; 116 }; 117 118 CPU1: cpu@100 { 119 device_type = "cpu"; 120 compatible = "qcom,kryo485"; 121 reg = <0x0 0x100>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <448>; 124 dynamic-power-coefficient = <205>; 125 next-level-cache = <&L2_100>; 126 power-domains = <&CPU_PD1>; 127 power-domain-names = "psci"; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 operating-points-v2 = <&cpu0_opp_table>; 130 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 131 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 132 #cooling-cells = <2>; 133 L2_100: l2-cache { 134 compatible = "cache"; 135 next-level-cache = <&L3_0>; 136 }; 137 }; 138 139 CPU2: cpu@200 { 140 device_type = "cpu"; 141 compatible = "qcom,kryo485"; 142 reg = <0x0 0x200>; 143 enable-method = "psci"; 144 capacity-dmips-mhz = <448>; 145 dynamic-power-coefficient = <205>; 146 next-level-cache = <&L2_200>; 147 power-domains = <&CPU_PD2>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 operating-points-v2 = <&cpu0_opp_table>; 151 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 152 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 153 #cooling-cells = <2>; 154 L2_200: l2-cache { 155 compatible = "cache"; 156 next-level-cache = <&L3_0>; 157 }; 158 }; 159 160 CPU3: cpu@300 { 161 device_type = "cpu"; 162 compatible = "qcom,kryo485"; 163 reg = <0x0 0x300>; 164 enable-method = "psci"; 165 capacity-dmips-mhz = <448>; 166 dynamic-power-coefficient = <205>; 167 next-level-cache = <&L2_300>; 168 power-domains = <&CPU_PD3>; 169 power-domain-names = "psci"; 170 qcom,freq-domain = <&cpufreq_hw 0>; 171 operating-points-v2 = <&cpu0_opp_table>; 172 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 173 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 174 #cooling-cells = <2>; 175 L2_300: l2-cache { 176 compatible = "cache"; 177 next-level-cache = <&L3_0>; 178 }; 179 }; 180 181 CPU4: cpu@400 { 182 device_type = "cpu"; 183 compatible = "qcom,kryo485"; 184 reg = <0x0 0x400>; 185 enable-method = "psci"; 186 capacity-dmips-mhz = <1024>; 187 dynamic-power-coefficient = <379>; 188 next-level-cache = <&L2_400>; 189 power-domains = <&CPU_PD4>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 operating-points-v2 = <&cpu4_opp_table>; 193 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 194 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 195 #cooling-cells = <2>; 196 L2_400: l2-cache { 197 compatible = "cache"; 198 next-level-cache = <&L3_0>; 199 }; 200 }; 201 202 CPU5: cpu@500 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo485"; 205 reg = <0x0 0x500>; 206 enable-method = "psci"; 207 capacity-dmips-mhz = <1024>; 208 dynamic-power-coefficient = <379>; 209 next-level-cache = <&L2_500>; 210 power-domains = <&CPU_PD5>; 211 power-domain-names = "psci"; 212 qcom,freq-domain = <&cpufreq_hw 1>; 213 operating-points-v2 = <&cpu4_opp_table>; 214 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 215 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 216 #cooling-cells = <2>; 217 L2_500: l2-cache { 218 compatible = "cache"; 219 next-level-cache = <&L3_0>; 220 }; 221 222 }; 223 224 CPU6: cpu@600 { 225 device_type = "cpu"; 226 compatible = "qcom,kryo485"; 227 reg = <0x0 0x600>; 228 enable-method = "psci"; 229 capacity-dmips-mhz = <1024>; 230 dynamic-power-coefficient = <379>; 231 next-level-cache = <&L2_600>; 232 power-domains = <&CPU_PD6>; 233 power-domain-names = "psci"; 234 qcom,freq-domain = <&cpufreq_hw 1>; 235 operating-points-v2 = <&cpu4_opp_table>; 236 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 237 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 238 #cooling-cells = <2>; 239 L2_600: l2-cache { 240 compatible = "cache"; 241 next-level-cache = <&L3_0>; 242 }; 243 }; 244 245 CPU7: cpu@700 { 246 device_type = "cpu"; 247 compatible = "qcom,kryo485"; 248 reg = <0x0 0x700>; 249 enable-method = "psci"; 250 capacity-dmips-mhz = <1024>; 251 dynamic-power-coefficient = <444>; 252 next-level-cache = <&L2_700>; 253 power-domains = <&CPU_PD7>; 254 power-domain-names = "psci"; 255 qcom,freq-domain = <&cpufreq_hw 2>; 256 operating-points-v2 = <&cpu7_opp_table>; 257 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 258 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 259 #cooling-cells = <2>; 260 L2_700: l2-cache { 261 compatible = "cache"; 262 next-level-cache = <&L3_0>; 263 }; 264 }; 265 266 cpu-map { 267 cluster0 { 268 core0 { 269 cpu = <&CPU0>; 270 }; 271 272 core1 { 273 cpu = <&CPU1>; 274 }; 275 276 core2 { 277 cpu = <&CPU2>; 278 }; 279 280 core3 { 281 cpu = <&CPU3>; 282 }; 283 284 core4 { 285 cpu = <&CPU4>; 286 }; 287 288 core5 { 289 cpu = <&CPU5>; 290 }; 291 292 core6 { 293 cpu = <&CPU6>; 294 }; 295 296 core7 { 297 cpu = <&CPU7>; 298 }; 299 }; 300 }; 301 302 idle-states { 303 entry-method = "psci"; 304 305 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 306 compatible = "arm,idle-state"; 307 idle-state-name = "silver-rail-power-collapse"; 308 arm,psci-suspend-param = <0x40000004>; 309 entry-latency-us = <360>; 310 exit-latency-us = <531>; 311 min-residency-us = <3934>; 312 local-timer-stop; 313 }; 314 315 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 316 compatible = "arm,idle-state"; 317 idle-state-name = "gold-rail-power-collapse"; 318 arm,psci-suspend-param = <0x40000004>; 319 entry-latency-us = <702>; 320 exit-latency-us = <1061>; 321 min-residency-us = <4488>; 322 local-timer-stop; 323 }; 324 }; 325 326 domain-idle-states { 327 CLUSTER_SLEEP_0: cluster-sleep-0 { 328 compatible = "domain-idle-state"; 329 idle-state-name = "cluster-llcc-off"; 330 arm,psci-suspend-param = <0x4100c244>; 331 entry-latency-us = <3264>; 332 exit-latency-us = <6562>; 333 min-residency-us = <9987>; 334 local-timer-stop; 335 }; 336 }; 337 }; 338 339 cpu0_opp_table: cpu0_opp_table { 340 compatible = "operating-points-v2"; 341 opp-shared; 342 343 cpu0_opp1: opp-300000000 { 344 opp-hz = /bits/ 64 <300000000>; 345 opp-peak-kBps = <800000 9600000>; 346 }; 347 348 cpu0_opp2: opp-403200000 { 349 opp-hz = /bits/ 64 <403200000>; 350 opp-peak-kBps = <800000 9600000>; 351 }; 352 353 cpu0_opp3: opp-518400000 { 354 opp-hz = /bits/ 64 <518400000>; 355 opp-peak-kBps = <800000 16588800>; 356 }; 357 358 cpu0_opp4: opp-614400000 { 359 opp-hz = /bits/ 64 <614400000>; 360 opp-peak-kBps = <800000 16588800>; 361 }; 362 363 cpu0_opp5: opp-691200000 { 364 opp-hz = /bits/ 64 <691200000>; 365 opp-peak-kBps = <800000 19660800>; 366 }; 367 368 cpu0_opp6: opp-787200000 { 369 opp-hz = /bits/ 64 <787200000>; 370 opp-peak-kBps = <1804000 19660800>; 371 }; 372 373 cpu0_opp7: opp-883200000 { 374 opp-hz = /bits/ 64 <883200000>; 375 opp-peak-kBps = <1804000 23347200>; 376 }; 377 378 cpu0_opp8: opp-979200000 { 379 opp-hz = /bits/ 64 <979200000>; 380 opp-peak-kBps = <1804000 26419200>; 381 }; 382 383 cpu0_opp9: opp-1075200000 { 384 opp-hz = /bits/ 64 <1075200000>; 385 opp-peak-kBps = <1804000 29491200>; 386 }; 387 388 cpu0_opp10: opp-1171200000 { 389 opp-hz = /bits/ 64 <1171200000>; 390 opp-peak-kBps = <1804000 32563200>; 391 }; 392 393 cpu0_opp11: opp-1248000000 { 394 opp-hz = /bits/ 64 <1248000000>; 395 opp-peak-kBps = <1804000 36249600>; 396 }; 397 398 cpu0_opp12: opp-1344000000 { 399 opp-hz = /bits/ 64 <1344000000>; 400 opp-peak-kBps = <2188000 36249600>; 401 }; 402 403 cpu0_opp13: opp-1420800000 { 404 opp-hz = /bits/ 64 <1420800000>; 405 opp-peak-kBps = <2188000 39321600>; 406 }; 407 408 cpu0_opp14: opp-1516800000 { 409 opp-hz = /bits/ 64 <1516800000>; 410 opp-peak-kBps = <3072000 42393600>; 411 }; 412 413 cpu0_opp15: opp-1612800000 { 414 opp-hz = /bits/ 64 <1612800000>; 415 opp-peak-kBps = <3072000 42393600>; 416 }; 417 418 cpu0_opp16: opp-1708800000 { 419 opp-hz = /bits/ 64 <1708800000>; 420 opp-peak-kBps = <4068000 42393600>; 421 }; 422 423 cpu0_opp17: opp-1804800000 { 424 opp-hz = /bits/ 64 <1804800000>; 425 opp-peak-kBps = <4068000 42393600>; 426 }; 427 }; 428 429 cpu4_opp_table: cpu4_opp_table { 430 compatible = "operating-points-v2"; 431 opp-shared; 432 433 cpu4_opp1: opp-710400000 { 434 opp-hz = /bits/ 64 <710400000>; 435 opp-peak-kBps = <1804000 19660800>; 436 }; 437 438 cpu4_opp2: opp-825600000 { 439 opp-hz = /bits/ 64 <825600000>; 440 opp-peak-kBps = <2188000 23347200>; 441 }; 442 443 cpu4_opp3: opp-940800000 { 444 opp-hz = /bits/ 64 <940800000>; 445 opp-peak-kBps = <2188000 26419200>; 446 }; 447 448 cpu4_opp4: opp-1056000000 { 449 opp-hz = /bits/ 64 <1056000000>; 450 opp-peak-kBps = <3072000 26419200>; 451 }; 452 453 cpu4_opp5: opp-1171200000 { 454 opp-hz = /bits/ 64 <1171200000>; 455 opp-peak-kBps = <3072000 29491200>; 456 }; 457 458 cpu4_opp6: opp-1286400000 { 459 opp-hz = /bits/ 64 <1286400000>; 460 opp-peak-kBps = <4068000 29491200>; 461 }; 462 463 cpu4_opp7: opp-1382400000 { 464 opp-hz = /bits/ 64 <1382400000>; 465 opp-peak-kBps = <4068000 32563200>; 466 }; 467 468 cpu4_opp8: opp-1478400000 { 469 opp-hz = /bits/ 64 <1478400000>; 470 opp-peak-kBps = <4068000 32563200>; 471 }; 472 473 cpu4_opp9: opp-1574400000 { 474 opp-hz = /bits/ 64 <1574400000>; 475 opp-peak-kBps = <5412000 39321600>; 476 }; 477 478 cpu4_opp10: opp-1670400000 { 479 opp-hz = /bits/ 64 <1670400000>; 480 opp-peak-kBps = <5412000 42393600>; 481 }; 482 483 cpu4_opp11: opp-1766400000 { 484 opp-hz = /bits/ 64 <1766400000>; 485 opp-peak-kBps = <5412000 45465600>; 486 }; 487 488 cpu4_opp12: opp-1862400000 { 489 opp-hz = /bits/ 64 <1862400000>; 490 opp-peak-kBps = <6220000 45465600>; 491 }; 492 493 cpu4_opp13: opp-1958400000 { 494 opp-hz = /bits/ 64 <1958400000>; 495 opp-peak-kBps = <6220000 48537600>; 496 }; 497 498 cpu4_opp14: opp-2054400000 { 499 opp-hz = /bits/ 64 <2054400000>; 500 opp-peak-kBps = <7216000 48537600>; 501 }; 502 503 cpu4_opp15: opp-2150400000 { 504 opp-hz = /bits/ 64 <2150400000>; 505 opp-peak-kBps = <7216000 51609600>; 506 }; 507 508 cpu4_opp16: opp-2246400000 { 509 opp-hz = /bits/ 64 <2246400000>; 510 opp-peak-kBps = <7216000 51609600>; 511 }; 512 513 cpu4_opp17: opp-2342400000 { 514 opp-hz = /bits/ 64 <2342400000>; 515 opp-peak-kBps = <8368000 51609600>; 516 }; 517 518 cpu4_opp18: opp-2419200000 { 519 opp-hz = /bits/ 64 <2419200000>; 520 opp-peak-kBps = <8368000 51609600>; 521 }; 522 }; 523 524 cpu7_opp_table: cpu7_opp_table { 525 compatible = "operating-points-v2"; 526 opp-shared; 527 528 cpu7_opp1: opp-844800000 { 529 opp-hz = /bits/ 64 <844800000>; 530 opp-peak-kBps = <2188000 19660800>; 531 }; 532 533 cpu7_opp2: opp-960000000 { 534 opp-hz = /bits/ 64 <960000000>; 535 opp-peak-kBps = <2188000 26419200>; 536 }; 537 538 cpu7_opp3: opp-1075200000 { 539 opp-hz = /bits/ 64 <1075200000>; 540 opp-peak-kBps = <3072000 26419200>; 541 }; 542 543 cpu7_opp4: opp-1190400000 { 544 opp-hz = /bits/ 64 <1190400000>; 545 opp-peak-kBps = <3072000 29491200>; 546 }; 547 548 cpu7_opp5: opp-1305600000 { 549 opp-hz = /bits/ 64 <1305600000>; 550 opp-peak-kBps = <4068000 32563200>; 551 }; 552 553 cpu7_opp6: opp-1401600000 { 554 opp-hz = /bits/ 64 <1401600000>; 555 opp-peak-kBps = <4068000 32563200>; 556 }; 557 558 cpu7_opp7: opp-1516800000 { 559 opp-hz = /bits/ 64 <1516800000>; 560 opp-peak-kBps = <4068000 36249600>; 561 }; 562 563 cpu7_opp8: opp-1632000000 { 564 opp-hz = /bits/ 64 <1632000000>; 565 opp-peak-kBps = <5412000 39321600>; 566 }; 567 568 cpu7_opp9: opp-1747200000 { 569 opp-hz = /bits/ 64 <1708800000>; 570 opp-peak-kBps = <5412000 42393600>; 571 }; 572 573 cpu7_opp10: opp-1862400000 { 574 opp-hz = /bits/ 64 <1862400000>; 575 opp-peak-kBps = <6220000 45465600>; 576 }; 577 578 cpu7_opp11: opp-1977600000 { 579 opp-hz = /bits/ 64 <1977600000>; 580 opp-peak-kBps = <6220000 48537600>; 581 }; 582 583 cpu7_opp12: opp-2073600000 { 584 opp-hz = /bits/ 64 <2073600000>; 585 opp-peak-kBps = <7216000 48537600>; 586 }; 587 588 cpu7_opp13: opp-2169600000 { 589 opp-hz = /bits/ 64 <2169600000>; 590 opp-peak-kBps = <7216000 51609600>; 591 }; 592 593 cpu7_opp14: opp-2265600000 { 594 opp-hz = /bits/ 64 <2265600000>; 595 opp-peak-kBps = <7216000 51609600>; 596 }; 597 598 cpu7_opp15: opp-2361600000 { 599 opp-hz = /bits/ 64 <2361600000>; 600 opp-peak-kBps = <8368000 51609600>; 601 }; 602 603 cpu7_opp16: opp-2457600000 { 604 opp-hz = /bits/ 64 <2457600000>; 605 opp-peak-kBps = <8368000 51609600>; 606 }; 607 608 cpu7_opp17: opp-2553600000 { 609 opp-hz = /bits/ 64 <2553600000>; 610 opp-peak-kBps = <8368000 51609600>; 611 }; 612 613 cpu7_opp18: opp-2649600000 { 614 opp-hz = /bits/ 64 <2649600000>; 615 opp-peak-kBps = <8368000 51609600>; 616 }; 617 618 cpu7_opp19: opp-2745600000 { 619 opp-hz = /bits/ 64 <2745600000>; 620 opp-peak-kBps = <8368000 51609600>; 621 }; 622 623 cpu7_opp20: opp-2841600000 { 624 opp-hz = /bits/ 64 <2841600000>; 625 opp-peak-kBps = <8368000 51609600>; 626 }; 627 }; 628 629 firmware { 630 scm: scm { 631 compatible = "qcom,scm"; 632 #reset-cells = <1>; 633 }; 634 }; 635 636 memory@80000000 { 637 device_type = "memory"; 638 /* We expect the bootloader to fill in the size */ 639 reg = <0x0 0x80000000 0x0 0x0>; 640 }; 641 642 pmu { 643 compatible = "arm,armv8-pmuv3"; 644 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 645 }; 646 647 psci { 648 compatible = "arm,psci-1.0"; 649 method = "smc"; 650 651 CPU_PD0: cpu0 { 652 #power-domain-cells = <0>; 653 power-domains = <&CLUSTER_PD>; 654 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 655 }; 656 657 CPU_PD1: cpu1 { 658 #power-domain-cells = <0>; 659 power-domains = <&CLUSTER_PD>; 660 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 661 }; 662 663 CPU_PD2: cpu2 { 664 #power-domain-cells = <0>; 665 power-domains = <&CLUSTER_PD>; 666 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 667 }; 668 669 CPU_PD3: cpu3 { 670 #power-domain-cells = <0>; 671 power-domains = <&CLUSTER_PD>; 672 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 673 }; 674 675 CPU_PD4: cpu4 { 676 #power-domain-cells = <0>; 677 power-domains = <&CLUSTER_PD>; 678 domain-idle-states = <&BIG_CPU_SLEEP_0>; 679 }; 680 681 CPU_PD5: cpu5 { 682 #power-domain-cells = <0>; 683 power-domains = <&CLUSTER_PD>; 684 domain-idle-states = <&BIG_CPU_SLEEP_0>; 685 }; 686 687 CPU_PD6: cpu6 { 688 #power-domain-cells = <0>; 689 power-domains = <&CLUSTER_PD>; 690 domain-idle-states = <&BIG_CPU_SLEEP_0>; 691 }; 692 693 CPU_PD7: cpu7 { 694 #power-domain-cells = <0>; 695 power-domains = <&CLUSTER_PD>; 696 domain-idle-states = <&BIG_CPU_SLEEP_0>; 697 }; 698 699 CLUSTER_PD: cpu-cluster0 { 700 #power-domain-cells = <0>; 701 domain-idle-states = <&CLUSTER_SLEEP_0>; 702 }; 703 }; 704 705 reserved-memory { 706 #address-cells = <2>; 707 #size-cells = <2>; 708 ranges; 709 710 hyp_mem: memory@80000000 { 711 reg = <0x0 0x80000000 0x0 0x600000>; 712 no-map; 713 }; 714 715 xbl_aop_mem: memory@80700000 { 716 reg = <0x0 0x80700000 0x0 0x160000>; 717 no-map; 718 }; 719 720 cmd_db: memory@80860000 { 721 compatible = "qcom,cmd-db"; 722 reg = <0x0 0x80860000 0x0 0x20000>; 723 no-map; 724 }; 725 726 smem_mem: memory@80900000 { 727 reg = <0x0 0x80900000 0x0 0x200000>; 728 no-map; 729 }; 730 731 removed_mem: memory@80b00000 { 732 reg = <0x0 0x80b00000 0x0 0x5300000>; 733 no-map; 734 }; 735 736 camera_mem: memory@86200000 { 737 reg = <0x0 0x86200000 0x0 0x500000>; 738 no-map; 739 }; 740 741 wlan_mem: memory@86700000 { 742 reg = <0x0 0x86700000 0x0 0x100000>; 743 no-map; 744 }; 745 746 ipa_fw_mem: memory@86800000 { 747 reg = <0x0 0x86800000 0x0 0x10000>; 748 no-map; 749 }; 750 751 ipa_gsi_mem: memory@86810000 { 752 reg = <0x0 0x86810000 0x0 0xa000>; 753 no-map; 754 }; 755 756 gpu_mem: memory@8681a000 { 757 reg = <0x0 0x8681a000 0x0 0x2000>; 758 no-map; 759 }; 760 761 npu_mem: memory@86900000 { 762 reg = <0x0 0x86900000 0x0 0x500000>; 763 no-map; 764 }; 765 766 video_mem: memory@86e00000 { 767 reg = <0x0 0x86e00000 0x0 0x500000>; 768 no-map; 769 }; 770 771 cvp_mem: memory@87300000 { 772 reg = <0x0 0x87300000 0x0 0x500000>; 773 no-map; 774 }; 775 776 cdsp_mem: memory@87800000 { 777 reg = <0x0 0x87800000 0x0 0x1400000>; 778 no-map; 779 }; 780 781 slpi_mem: memory@88c00000 { 782 reg = <0x0 0x88c00000 0x0 0x1500000>; 783 no-map; 784 }; 785 786 adsp_mem: memory@8a100000 { 787 reg = <0x0 0x8a100000 0x0 0x1d00000>; 788 no-map; 789 }; 790 791 spss_mem: memory@8be00000 { 792 reg = <0x0 0x8be00000 0x0 0x100000>; 793 no-map; 794 }; 795 796 cdsp_secure_heap: memory@8bf00000 { 797 reg = <0x0 0x8bf00000 0x0 0x4600000>; 798 no-map; 799 }; 800 }; 801 802 smem { 803 compatible = "qcom,smem"; 804 memory-region = <&smem_mem>; 805 hwlocks = <&tcsr_mutex 3>; 806 }; 807 808 smp2p-adsp { 809 compatible = "qcom,smp2p"; 810 qcom,smem = <443>, <429>; 811 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 812 IPCC_MPROC_SIGNAL_SMP2P 813 IRQ_TYPE_EDGE_RISING>; 814 mboxes = <&ipcc IPCC_CLIENT_LPASS 815 IPCC_MPROC_SIGNAL_SMP2P>; 816 817 qcom,local-pid = <0>; 818 qcom,remote-pid = <2>; 819 820 smp2p_adsp_out: master-kernel { 821 qcom,entry-name = "master-kernel"; 822 #qcom,smem-state-cells = <1>; 823 }; 824 825 smp2p_adsp_in: slave-kernel { 826 qcom,entry-name = "slave-kernel"; 827 interrupt-controller; 828 #interrupt-cells = <2>; 829 }; 830 }; 831 832 smp2p-cdsp { 833 compatible = "qcom,smp2p"; 834 qcom,smem = <94>, <432>; 835 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 836 IPCC_MPROC_SIGNAL_SMP2P 837 IRQ_TYPE_EDGE_RISING>; 838 mboxes = <&ipcc IPCC_CLIENT_CDSP 839 IPCC_MPROC_SIGNAL_SMP2P>; 840 841 qcom,local-pid = <0>; 842 qcom,remote-pid = <5>; 843 844 smp2p_cdsp_out: master-kernel { 845 qcom,entry-name = "master-kernel"; 846 #qcom,smem-state-cells = <1>; 847 }; 848 849 smp2p_cdsp_in: slave-kernel { 850 qcom,entry-name = "slave-kernel"; 851 interrupt-controller; 852 #interrupt-cells = <2>; 853 }; 854 }; 855 856 smp2p-slpi { 857 compatible = "qcom,smp2p"; 858 qcom,smem = <481>, <430>; 859 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 860 IPCC_MPROC_SIGNAL_SMP2P 861 IRQ_TYPE_EDGE_RISING>; 862 mboxes = <&ipcc IPCC_CLIENT_SLPI 863 IPCC_MPROC_SIGNAL_SMP2P>; 864 865 qcom,local-pid = <0>; 866 qcom,remote-pid = <3>; 867 868 smp2p_slpi_out: master-kernel { 869 qcom,entry-name = "master-kernel"; 870 #qcom,smem-state-cells = <1>; 871 }; 872 873 smp2p_slpi_in: slave-kernel { 874 qcom,entry-name = "slave-kernel"; 875 interrupt-controller; 876 #interrupt-cells = <2>; 877 }; 878 }; 879 880 soc: soc@0 { 881 #address-cells = <2>; 882 #size-cells = <2>; 883 ranges = <0 0 0 0 0x10 0>; 884 dma-ranges = <0 0 0 0 0x10 0>; 885 compatible = "simple-bus"; 886 887 gcc: clock-controller@100000 { 888 compatible = "qcom,gcc-sm8250"; 889 reg = <0x0 0x00100000 0x0 0x1f0000>; 890 #clock-cells = <1>; 891 #reset-cells = <1>; 892 #power-domain-cells = <1>; 893 clock-names = "bi_tcxo", 894 "bi_tcxo_ao", 895 "sleep_clk"; 896 clocks = <&rpmhcc RPMH_CXO_CLK>, 897 <&rpmhcc RPMH_CXO_CLK_A>, 898 <&sleep_clk>; 899 }; 900 901 ipcc: mailbox@408000 { 902 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 903 reg = <0 0x00408000 0 0x1000>; 904 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 905 interrupt-controller; 906 #interrupt-cells = <3>; 907 #mbox-cells = <2>; 908 }; 909 910 rng: rng@793000 { 911 compatible = "qcom,prng-ee"; 912 reg = <0 0x00793000 0 0x1000>; 913 clocks = <&gcc GCC_PRNG_AHB_CLK>; 914 clock-names = "core"; 915 }; 916 917 qup_opp_table: qup-opp-table { 918 compatible = "operating-points-v2"; 919 920 opp-50000000 { 921 opp-hz = /bits/ 64 <50000000>; 922 required-opps = <&rpmhpd_opp_min_svs>; 923 }; 924 925 opp-75000000 { 926 opp-hz = /bits/ 64 <75000000>; 927 required-opps = <&rpmhpd_opp_low_svs>; 928 }; 929 930 opp-120000000 { 931 opp-hz = /bits/ 64 <120000000>; 932 required-opps = <&rpmhpd_opp_svs>; 933 }; 934 }; 935 936 gpi_dma2: dma-controller@800000 { 937 compatible = "qcom,sm8250-gpi-dma"; 938 reg = <0 0x00800000 0 0x70000>; 939 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 949 dma-channels = <10>; 950 dma-channel-mask = <0x3f>; 951 iommus = <&apps_smmu 0x76 0x0>; 952 #dma-cells = <3>; 953 status = "disabled"; 954 }; 955 956 qupv3_id_2: geniqup@8c0000 { 957 compatible = "qcom,geni-se-qup"; 958 reg = <0x0 0x008c0000 0x0 0x6000>; 959 clock-names = "m-ahb", "s-ahb"; 960 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 961 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 962 #address-cells = <2>; 963 #size-cells = <2>; 964 iommus = <&apps_smmu 0x63 0x0>; 965 ranges; 966 status = "disabled"; 967 968 i2c14: i2c@880000 { 969 compatible = "qcom,geni-i2c"; 970 reg = <0 0x00880000 0 0x4000>; 971 clock-names = "se"; 972 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&qup_i2c14_default>; 975 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 976 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 977 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 978 dma-names = "tx", "rx"; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 status = "disabled"; 982 }; 983 984 spi14: spi@880000 { 985 compatible = "qcom,geni-spi"; 986 reg = <0 0x00880000 0 0x4000>; 987 clock-names = "se"; 988 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 989 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 990 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 991 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 992 dma-names = "tx", "rx"; 993 power-domains = <&rpmhpd SM8250_CX>; 994 operating-points-v2 = <&qup_opp_table>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 i2c15: i2c@884000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0 0x00884000 0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c15_default>; 1007 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1008 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1009 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 status = "disabled"; 1014 }; 1015 1016 spi15: spi@884000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0 0x00884000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1021 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1022 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1023 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1024 dma-names = "tx", "rx"; 1025 power-domains = <&rpmhpd SM8250_CX>; 1026 operating-points-v2 = <&qup_opp_table>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 i2c16: i2c@888000 { 1033 compatible = "qcom,geni-i2c"; 1034 reg = <0 0x00888000 0 0x4000>; 1035 clock-names = "se"; 1036 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_i2c16_default>; 1039 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1040 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1041 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1042 dma-names = "tx", "rx"; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 spi16: spi@888000 { 1049 compatible = "qcom,geni-spi"; 1050 reg = <0 0x00888000 0 0x4000>; 1051 clock-names = "se"; 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1053 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1054 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1055 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1056 dma-names = "tx", "rx"; 1057 power-domains = <&rpmhpd SM8250_CX>; 1058 operating-points-v2 = <&qup_opp_table>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 i2c17: i2c@88c000 { 1065 compatible = "qcom,geni-i2c"; 1066 reg = <0 0x0088c000 0 0x4000>; 1067 clock-names = "se"; 1068 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_i2c17_default>; 1071 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1072 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1073 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1074 dma-names = "tx", "rx"; 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 status = "disabled"; 1078 }; 1079 1080 spi17: spi@88c000 { 1081 compatible = "qcom,geni-spi"; 1082 reg = <0 0x0088c000 0 0x4000>; 1083 clock-names = "se"; 1084 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1085 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1086 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1087 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1088 dma-names = "tx", "rx"; 1089 power-domains = <&rpmhpd SM8250_CX>; 1090 operating-points-v2 = <&qup_opp_table>; 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 status = "disabled"; 1094 }; 1095 1096 uart17: serial@88c000 { 1097 compatible = "qcom,geni-uart"; 1098 reg = <0 0x0088c000 0 0x4000>; 1099 clock-names = "se"; 1100 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1101 pinctrl-names = "default"; 1102 pinctrl-0 = <&qup_uart17_default>; 1103 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1104 power-domains = <&rpmhpd SM8250_CX>; 1105 operating-points-v2 = <&qup_opp_table>; 1106 status = "disabled"; 1107 }; 1108 1109 i2c18: i2c@890000 { 1110 compatible = "qcom,geni-i2c"; 1111 reg = <0 0x00890000 0 0x4000>; 1112 clock-names = "se"; 1113 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&qup_i2c18_default>; 1116 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1117 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1118 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1119 dma-names = "tx", "rx"; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 status = "disabled"; 1123 }; 1124 1125 spi18: spi@890000 { 1126 compatible = "qcom,geni-spi"; 1127 reg = <0 0x00890000 0 0x4000>; 1128 clock-names = "se"; 1129 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1130 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1131 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1132 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1133 dma-names = "tx", "rx"; 1134 power-domains = <&rpmhpd SM8250_CX>; 1135 operating-points-v2 = <&qup_opp_table>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 status = "disabled"; 1139 }; 1140 1141 uart18: serial@890000 { 1142 compatible = "qcom,geni-uart"; 1143 reg = <0 0x00890000 0 0x4000>; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_uart18_default>; 1148 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1149 power-domains = <&rpmhpd SM8250_CX>; 1150 operating-points-v2 = <&qup_opp_table>; 1151 status = "disabled"; 1152 }; 1153 1154 i2c19: i2c@894000 { 1155 compatible = "qcom,geni-i2c"; 1156 reg = <0 0x00894000 0 0x4000>; 1157 clock-names = "se"; 1158 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1159 pinctrl-names = "default"; 1160 pinctrl-0 = <&qup_i2c19_default>; 1161 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1162 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1163 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1164 dma-names = "tx", "rx"; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 status = "disabled"; 1168 }; 1169 1170 spi19: spi@894000 { 1171 compatible = "qcom,geni-spi"; 1172 reg = <0 0x00894000 0 0x4000>; 1173 clock-names = "se"; 1174 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1175 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1176 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1177 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1178 dma-names = "tx", "rx"; 1179 power-domains = <&rpmhpd SM8250_CX>; 1180 operating-points-v2 = <&qup_opp_table>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 status = "disabled"; 1184 }; 1185 }; 1186 1187 gpi_dma0: dma-controller@900000 { 1188 compatible = "qcom,sm8250-gpi-dma"; 1189 reg = <0 0x00900000 0 0x70000>; 1190 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1203 dma-channels = <15>; 1204 dma-channel-mask = <0x7ff>; 1205 iommus = <&apps_smmu 0x5b6 0x0>; 1206 #dma-cells = <3>; 1207 status = "disabled"; 1208 }; 1209 1210 qupv3_id_0: geniqup@9c0000 { 1211 compatible = "qcom,geni-se-qup"; 1212 reg = <0x0 0x009c0000 0x0 0x6000>; 1213 clock-names = "m-ahb", "s-ahb"; 1214 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1215 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1216 #address-cells = <2>; 1217 #size-cells = <2>; 1218 iommus = <&apps_smmu 0x5a3 0x0>; 1219 ranges; 1220 status = "disabled"; 1221 1222 i2c0: i2c@980000 { 1223 compatible = "qcom,geni-i2c"; 1224 reg = <0 0x00980000 0 0x4000>; 1225 clock-names = "se"; 1226 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&qup_i2c0_default>; 1229 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1230 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1231 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1232 dma-names = "tx", "rx"; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 1238 spi0: spi@980000 { 1239 compatible = "qcom,geni-spi"; 1240 reg = <0 0x00980000 0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1243 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1244 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1245 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1246 dma-names = "tx", "rx"; 1247 power-domains = <&rpmhpd SM8250_CX>; 1248 operating-points-v2 = <&qup_opp_table>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 status = "disabled"; 1252 }; 1253 1254 i2c1: i2c@984000 { 1255 compatible = "qcom,geni-i2c"; 1256 reg = <0 0x00984000 0 0x4000>; 1257 clock-names = "se"; 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1259 pinctrl-names = "default"; 1260 pinctrl-0 = <&qup_i2c1_default>; 1261 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1262 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1263 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1264 dma-names = "tx", "rx"; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 status = "disabled"; 1268 }; 1269 1270 spi1: spi@984000 { 1271 compatible = "qcom,geni-spi"; 1272 reg = <0 0x00984000 0 0x4000>; 1273 clock-names = "se"; 1274 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1275 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1276 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1277 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1278 dma-names = "tx", "rx"; 1279 power-domains = <&rpmhpd SM8250_CX>; 1280 operating-points-v2 = <&qup_opp_table>; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 status = "disabled"; 1284 }; 1285 1286 i2c2: i2c@988000 { 1287 compatible = "qcom,geni-i2c"; 1288 reg = <0 0x00988000 0 0x4000>; 1289 clock-names = "se"; 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&qup_i2c2_default>; 1293 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1294 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1295 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1296 dma-names = "tx", "rx"; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 status = "disabled"; 1300 }; 1301 1302 spi2: spi@988000 { 1303 compatible = "qcom,geni-spi"; 1304 reg = <0 0x00988000 0 0x4000>; 1305 clock-names = "se"; 1306 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1307 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1308 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1309 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1310 dma-names = "tx", "rx"; 1311 power-domains = <&rpmhpd SM8250_CX>; 1312 operating-points-v2 = <&qup_opp_table>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 uart2: serial@988000 { 1319 compatible = "qcom,geni-debug-uart"; 1320 reg = <0 0x00988000 0 0x4000>; 1321 clock-names = "se"; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&qup_uart2_default>; 1325 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1326 power-domains = <&rpmhpd SM8250_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 status = "disabled"; 1329 }; 1330 1331 i2c3: i2c@98c000 { 1332 compatible = "qcom,geni-i2c"; 1333 reg = <0 0x0098c000 0 0x4000>; 1334 clock-names = "se"; 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_i2c3_default>; 1338 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1339 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1340 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1341 dma-names = "tx", "rx"; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 status = "disabled"; 1345 }; 1346 1347 spi3: spi@98c000 { 1348 compatible = "qcom,geni-spi"; 1349 reg = <0 0x0098c000 0 0x4000>; 1350 clock-names = "se"; 1351 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1352 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1353 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1354 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1355 dma-names = "tx", "rx"; 1356 power-domains = <&rpmhpd SM8250_CX>; 1357 operating-points-v2 = <&qup_opp_table>; 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 status = "disabled"; 1361 }; 1362 1363 i2c4: i2c@990000 { 1364 compatible = "qcom,geni-i2c"; 1365 reg = <0 0x00990000 0 0x4000>; 1366 clock-names = "se"; 1367 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_i2c4_default>; 1370 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1371 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1372 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1373 dma-names = "tx", "rx"; 1374 #address-cells = <1>; 1375 #size-cells = <0>; 1376 status = "disabled"; 1377 }; 1378 1379 spi4: spi@990000 { 1380 compatible = "qcom,geni-spi"; 1381 reg = <0 0x00990000 0 0x4000>; 1382 clock-names = "se"; 1383 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1384 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1385 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1386 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1387 dma-names = "tx", "rx"; 1388 power-domains = <&rpmhpd SM8250_CX>; 1389 operating-points-v2 = <&qup_opp_table>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 i2c5: i2c@994000 { 1396 compatible = "qcom,geni-i2c"; 1397 reg = <0 0x00994000 0 0x4000>; 1398 clock-names = "se"; 1399 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&qup_i2c5_default>; 1402 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1403 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1404 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1405 dma-names = "tx", "rx"; 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 status = "disabled"; 1409 }; 1410 1411 spi5: spi@994000 { 1412 compatible = "qcom,geni-spi"; 1413 reg = <0 0x00994000 0 0x4000>; 1414 clock-names = "se"; 1415 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1416 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1417 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1418 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1419 dma-names = "tx", "rx"; 1420 power-domains = <&rpmhpd SM8250_CX>; 1421 operating-points-v2 = <&qup_opp_table>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 status = "disabled"; 1425 }; 1426 1427 i2c6: i2c@998000 { 1428 compatible = "qcom,geni-i2c"; 1429 reg = <0 0x00998000 0 0x4000>; 1430 clock-names = "se"; 1431 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1432 pinctrl-names = "default"; 1433 pinctrl-0 = <&qup_i2c6_default>; 1434 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1435 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1436 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1437 dma-names = "tx", "rx"; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 status = "disabled"; 1441 }; 1442 1443 spi6: spi@998000 { 1444 compatible = "qcom,geni-spi"; 1445 reg = <0 0x00998000 0 0x4000>; 1446 clock-names = "se"; 1447 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1448 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1449 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1450 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1451 dma-names = "tx", "rx"; 1452 power-domains = <&rpmhpd SM8250_CX>; 1453 operating-points-v2 = <&qup_opp_table>; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 status = "disabled"; 1457 }; 1458 1459 uart6: serial@998000 { 1460 compatible = "qcom,geni-uart"; 1461 reg = <0 0x00998000 0 0x4000>; 1462 clock-names = "se"; 1463 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1464 pinctrl-names = "default"; 1465 pinctrl-0 = <&qup_uart6_default>; 1466 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1467 power-domains = <&rpmhpd SM8250_CX>; 1468 operating-points-v2 = <&qup_opp_table>; 1469 status = "disabled"; 1470 }; 1471 1472 i2c7: i2c@99c000 { 1473 compatible = "qcom,geni-i2c"; 1474 reg = <0 0x0099c000 0 0x4000>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_i2c7_default>; 1479 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1480 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1481 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1482 dma-names = "tx", "rx"; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 status = "disabled"; 1486 }; 1487 1488 spi7: spi@99c000 { 1489 compatible = "qcom,geni-spi"; 1490 reg = <0 0x0099c000 0 0x4000>; 1491 clock-names = "se"; 1492 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1493 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1494 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1495 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1496 dma-names = "tx", "rx"; 1497 power-domains = <&rpmhpd SM8250_CX>; 1498 operating-points-v2 = <&qup_opp_table>; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 status = "disabled"; 1502 }; 1503 }; 1504 1505 gpi_dma1: dma-controller@a00000 { 1506 compatible = "qcom,sm8250-gpi-dma"; 1507 reg = <0 0x00a00000 0 0x70000>; 1508 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1518 dma-channels = <10>; 1519 dma-channel-mask = <0x3f>; 1520 iommus = <&apps_smmu 0x56 0x0>; 1521 #dma-cells = <3>; 1522 status = "disabled"; 1523 }; 1524 1525 qupv3_id_1: geniqup@ac0000 { 1526 compatible = "qcom,geni-se-qup"; 1527 reg = <0x0 0x00ac0000 0x0 0x6000>; 1528 clock-names = "m-ahb", "s-ahb"; 1529 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1530 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1531 #address-cells = <2>; 1532 #size-cells = <2>; 1533 iommus = <&apps_smmu 0x43 0x0>; 1534 ranges; 1535 status = "disabled"; 1536 1537 i2c8: i2c@a80000 { 1538 compatible = "qcom,geni-i2c"; 1539 reg = <0 0x00a80000 0 0x4000>; 1540 clock-names = "se"; 1541 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1542 pinctrl-names = "default"; 1543 pinctrl-0 = <&qup_i2c8_default>; 1544 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1545 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1546 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1547 dma-names = "tx", "rx"; 1548 #address-cells = <1>; 1549 #size-cells = <0>; 1550 status = "disabled"; 1551 }; 1552 1553 spi8: spi@a80000 { 1554 compatible = "qcom,geni-spi"; 1555 reg = <0 0x00a80000 0 0x4000>; 1556 clock-names = "se"; 1557 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1558 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1559 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1560 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1561 dma-names = "tx", "rx"; 1562 power-domains = <&rpmhpd SM8250_CX>; 1563 operating-points-v2 = <&qup_opp_table>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 status = "disabled"; 1567 }; 1568 1569 i2c9: i2c@a84000 { 1570 compatible = "qcom,geni-i2c"; 1571 reg = <0 0x00a84000 0 0x4000>; 1572 clock-names = "se"; 1573 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1574 pinctrl-names = "default"; 1575 pinctrl-0 = <&qup_i2c9_default>; 1576 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1577 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1578 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1579 dma-names = "tx", "rx"; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 status = "disabled"; 1583 }; 1584 1585 spi9: spi@a84000 { 1586 compatible = "qcom,geni-spi"; 1587 reg = <0 0x00a84000 0 0x4000>; 1588 clock-names = "se"; 1589 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1590 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1591 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1592 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1593 dma-names = "tx", "rx"; 1594 power-domains = <&rpmhpd SM8250_CX>; 1595 operating-points-v2 = <&qup_opp_table>; 1596 #address-cells = <1>; 1597 #size-cells = <0>; 1598 status = "disabled"; 1599 }; 1600 1601 i2c10: i2c@a88000 { 1602 compatible = "qcom,geni-i2c"; 1603 reg = <0 0x00a88000 0 0x4000>; 1604 clock-names = "se"; 1605 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_i2c10_default>; 1608 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1609 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1610 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1611 dma-names = "tx", "rx"; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 status = "disabled"; 1615 }; 1616 1617 spi10: spi@a88000 { 1618 compatible = "qcom,geni-spi"; 1619 reg = <0 0x00a88000 0 0x4000>; 1620 clock-names = "se"; 1621 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1622 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1623 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1624 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1625 dma-names = "tx", "rx"; 1626 power-domains = <&rpmhpd SM8250_CX>; 1627 operating-points-v2 = <&qup_opp_table>; 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 status = "disabled"; 1631 }; 1632 1633 i2c11: i2c@a8c000 { 1634 compatible = "qcom,geni-i2c"; 1635 reg = <0 0x00a8c000 0 0x4000>; 1636 clock-names = "se"; 1637 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1638 pinctrl-names = "default"; 1639 pinctrl-0 = <&qup_i2c11_default>; 1640 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1641 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1642 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1643 dma-names = "tx", "rx"; 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 status = "disabled"; 1647 }; 1648 1649 spi11: spi@a8c000 { 1650 compatible = "qcom,geni-spi"; 1651 reg = <0 0x00a8c000 0 0x4000>; 1652 clock-names = "se"; 1653 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1654 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1655 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1656 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1657 dma-names = "tx", "rx"; 1658 power-domains = <&rpmhpd SM8250_CX>; 1659 operating-points-v2 = <&qup_opp_table>; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 status = "disabled"; 1663 }; 1664 1665 i2c12: i2c@a90000 { 1666 compatible = "qcom,geni-i2c"; 1667 reg = <0 0x00a90000 0 0x4000>; 1668 clock-names = "se"; 1669 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1670 pinctrl-names = "default"; 1671 pinctrl-0 = <&qup_i2c12_default>; 1672 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1673 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1674 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1675 dma-names = "tx", "rx"; 1676 #address-cells = <1>; 1677 #size-cells = <0>; 1678 status = "disabled"; 1679 }; 1680 1681 spi12: spi@a90000 { 1682 compatible = "qcom,geni-spi"; 1683 reg = <0 0x00a90000 0 0x4000>; 1684 clock-names = "se"; 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1686 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1687 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1688 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1689 dma-names = "tx", "rx"; 1690 power-domains = <&rpmhpd SM8250_CX>; 1691 operating-points-v2 = <&qup_opp_table>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 status = "disabled"; 1695 }; 1696 1697 uart12: serial@a90000 { 1698 compatible = "qcom,geni-debug-uart"; 1699 reg = <0x0 0x00a90000 0x0 0x4000>; 1700 clock-names = "se"; 1701 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1702 pinctrl-names = "default"; 1703 pinctrl-0 = <&qup_uart12_default>; 1704 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1705 power-domains = <&rpmhpd SM8250_CX>; 1706 operating-points-v2 = <&qup_opp_table>; 1707 status = "disabled"; 1708 }; 1709 1710 i2c13: i2c@a94000 { 1711 compatible = "qcom,geni-i2c"; 1712 reg = <0 0x00a94000 0 0x4000>; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_i2c13_default>; 1717 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1718 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1719 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1720 dma-names = "tx", "rx"; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 status = "disabled"; 1724 }; 1725 1726 spi13: spi@a94000 { 1727 compatible = "qcom,geni-spi"; 1728 reg = <0 0x00a94000 0 0x4000>; 1729 clock-names = "se"; 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1731 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1732 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1733 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1734 dma-names = "tx", "rx"; 1735 power-domains = <&rpmhpd SM8250_CX>; 1736 operating-points-v2 = <&qup_opp_table>; 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 status = "disabled"; 1740 }; 1741 }; 1742 1743 config_noc: interconnect@1500000 { 1744 compatible = "qcom,sm8250-config-noc"; 1745 reg = <0 0x01500000 0 0xa580>; 1746 #interconnect-cells = <1>; 1747 qcom,bcm-voters = <&apps_bcm_voter>; 1748 }; 1749 1750 system_noc: interconnect@1620000 { 1751 compatible = "qcom,sm8250-system-noc"; 1752 reg = <0 0x01620000 0 0x1c200>; 1753 #interconnect-cells = <1>; 1754 qcom,bcm-voters = <&apps_bcm_voter>; 1755 }; 1756 1757 mc_virt: interconnect@163d000 { 1758 compatible = "qcom,sm8250-mc-virt"; 1759 reg = <0 0x0163d000 0 0x1000>; 1760 #interconnect-cells = <1>; 1761 qcom,bcm-voters = <&apps_bcm_voter>; 1762 }; 1763 1764 aggre1_noc: interconnect@16e0000 { 1765 compatible = "qcom,sm8250-aggre1-noc"; 1766 reg = <0 0x016e0000 0 0x1f180>; 1767 #interconnect-cells = <1>; 1768 qcom,bcm-voters = <&apps_bcm_voter>; 1769 }; 1770 1771 aggre2_noc: interconnect@1700000 { 1772 compatible = "qcom,sm8250-aggre2-noc"; 1773 reg = <0 0x01700000 0 0x33000>; 1774 #interconnect-cells = <1>; 1775 qcom,bcm-voters = <&apps_bcm_voter>; 1776 }; 1777 1778 compute_noc: interconnect@1733000 { 1779 compatible = "qcom,sm8250-compute-noc"; 1780 reg = <0 0x01733000 0 0xa180>; 1781 #interconnect-cells = <1>; 1782 qcom,bcm-voters = <&apps_bcm_voter>; 1783 }; 1784 1785 mmss_noc: interconnect@1740000 { 1786 compatible = "qcom,sm8250-mmss-noc"; 1787 reg = <0 0x01740000 0 0x1f080>; 1788 #interconnect-cells = <1>; 1789 qcom,bcm-voters = <&apps_bcm_voter>; 1790 }; 1791 1792 pcie0: pci@1c00000 { 1793 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1794 reg = <0 0x01c00000 0 0x3000>, 1795 <0 0x60000000 0 0xf1d>, 1796 <0 0x60000f20 0 0xa8>, 1797 <0 0x60001000 0 0x1000>, 1798 <0 0x60100000 0 0x100000>; 1799 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1800 device_type = "pci"; 1801 linux,pci-domain = <0>; 1802 bus-range = <0x00 0xff>; 1803 num-lanes = <1>; 1804 1805 #address-cells = <3>; 1806 #size-cells = <2>; 1807 1808 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1809 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1810 1811 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1812 interrupt-names = "msi"; 1813 #interrupt-cells = <1>; 1814 interrupt-map-mask = <0 0 0 0x7>; 1815 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1816 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1817 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1818 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1819 1820 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1821 <&gcc GCC_PCIE_0_AUX_CLK>, 1822 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1823 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1824 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1825 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1826 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1827 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1828 clock-names = "pipe", 1829 "aux", 1830 "cfg", 1831 "bus_master", 1832 "bus_slave", 1833 "slave_q2a", 1834 "tbu", 1835 "ddrss_sf_tbu"; 1836 1837 iommus = <&apps_smmu 0x1c00 0x7f>; 1838 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1839 <0x100 &apps_smmu 0x1c01 0x1>; 1840 1841 resets = <&gcc GCC_PCIE_0_BCR>; 1842 reset-names = "pci"; 1843 1844 power-domains = <&gcc PCIE_0_GDSC>; 1845 1846 phys = <&pcie0_lane>; 1847 phy-names = "pciephy"; 1848 1849 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1850 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1851 1852 pinctrl-names = "default"; 1853 pinctrl-0 = <&pcie0_default_state>; 1854 1855 status = "disabled"; 1856 }; 1857 1858 pcie0_phy: phy@1c06000 { 1859 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1860 reg = <0 0x01c06000 0 0x1c0>; 1861 #address-cells = <2>; 1862 #size-cells = <2>; 1863 ranges; 1864 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1865 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1866 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1867 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1868 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1869 1870 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1871 reset-names = "phy"; 1872 1873 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1874 assigned-clock-rates = <100000000>; 1875 1876 status = "disabled"; 1877 1878 pcie0_lane: phy@1c06200 { 1879 reg = <0 0x1c06200 0 0x170>, /* tx */ 1880 <0 0x1c06400 0 0x200>, /* rx */ 1881 <0 0x1c06800 0 0x1f0>, /* pcs */ 1882 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1883 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1884 clock-names = "pipe0"; 1885 1886 #phy-cells = <0>; 1887 1888 #clock-cells = <0>; 1889 clock-output-names = "pcie_0_pipe_clk"; 1890 }; 1891 }; 1892 1893 pcie1: pci@1c08000 { 1894 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1895 reg = <0 0x01c08000 0 0x3000>, 1896 <0 0x40000000 0 0xf1d>, 1897 <0 0x40000f20 0 0xa8>, 1898 <0 0x40001000 0 0x1000>, 1899 <0 0x40100000 0 0x100000>; 1900 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1901 device_type = "pci"; 1902 linux,pci-domain = <1>; 1903 bus-range = <0x00 0xff>; 1904 num-lanes = <2>; 1905 1906 #address-cells = <3>; 1907 #size-cells = <2>; 1908 1909 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1910 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1911 1912 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1913 interrupt-names = "msi"; 1914 #interrupt-cells = <1>; 1915 interrupt-map-mask = <0 0 0 0x7>; 1916 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1917 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1918 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1919 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1920 1921 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1922 <&gcc GCC_PCIE_1_AUX_CLK>, 1923 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1924 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1925 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1926 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1927 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1928 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1929 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1930 clock-names = "pipe", 1931 "aux", 1932 "cfg", 1933 "bus_master", 1934 "bus_slave", 1935 "slave_q2a", 1936 "ref", 1937 "tbu", 1938 "ddrss_sf_tbu"; 1939 1940 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1941 assigned-clock-rates = <19200000>; 1942 1943 iommus = <&apps_smmu 0x1c80 0x7f>; 1944 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1945 <0x100 &apps_smmu 0x1c81 0x1>; 1946 1947 resets = <&gcc GCC_PCIE_1_BCR>; 1948 reset-names = "pci"; 1949 1950 power-domains = <&gcc PCIE_1_GDSC>; 1951 1952 phys = <&pcie1_lane>; 1953 phy-names = "pciephy"; 1954 1955 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 1956 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1957 1958 pinctrl-names = "default"; 1959 pinctrl-0 = <&pcie1_default_state>; 1960 1961 status = "disabled"; 1962 }; 1963 1964 pcie1_phy: phy@1c0e000 { 1965 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1966 reg = <0 0x01c0e000 0 0x1c0>; 1967 #address-cells = <2>; 1968 #size-cells = <2>; 1969 ranges; 1970 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1971 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1972 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1973 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1974 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1975 1976 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1977 reset-names = "phy"; 1978 1979 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1980 assigned-clock-rates = <100000000>; 1981 1982 status = "disabled"; 1983 1984 pcie1_lane: phy@1c0e200 { 1985 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1986 <0 0x1c0e400 0 0x200>, /* rx0 */ 1987 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1988 <0 0x1c0e600 0 0x170>, /* tx1 */ 1989 <0 0x1c0e800 0 0x200>, /* rx1 */ 1990 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1991 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1992 clock-names = "pipe0"; 1993 1994 #phy-cells = <0>; 1995 1996 #clock-cells = <0>; 1997 clock-output-names = "pcie_1_pipe_clk"; 1998 }; 1999 }; 2000 2001 pcie2: pci@1c10000 { 2002 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 2003 reg = <0 0x01c10000 0 0x3000>, 2004 <0 0x64000000 0 0xf1d>, 2005 <0 0x64000f20 0 0xa8>, 2006 <0 0x64001000 0 0x1000>, 2007 <0 0x64100000 0 0x100000>; 2008 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2009 device_type = "pci"; 2010 linux,pci-domain = <2>; 2011 bus-range = <0x00 0xff>; 2012 num-lanes = <2>; 2013 2014 #address-cells = <3>; 2015 #size-cells = <2>; 2016 2017 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 2018 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2019 2020 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2021 interrupt-names = "msi"; 2022 #interrupt-cells = <1>; 2023 interrupt-map-mask = <0 0 0 0x7>; 2024 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2025 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2026 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2027 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2028 2029 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2030 <&gcc GCC_PCIE_2_AUX_CLK>, 2031 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2032 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2033 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2034 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2035 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2036 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2037 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2038 clock-names = "pipe", 2039 "aux", 2040 "cfg", 2041 "bus_master", 2042 "bus_slave", 2043 "slave_q2a", 2044 "ref", 2045 "tbu", 2046 "ddrss_sf_tbu"; 2047 2048 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2049 assigned-clock-rates = <19200000>; 2050 2051 iommus = <&apps_smmu 0x1d00 0x7f>; 2052 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2053 <0x100 &apps_smmu 0x1d01 0x1>; 2054 2055 resets = <&gcc GCC_PCIE_2_BCR>; 2056 reset-names = "pci"; 2057 2058 power-domains = <&gcc PCIE_2_GDSC>; 2059 2060 phys = <&pcie2_lane>; 2061 phy-names = "pciephy"; 2062 2063 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2064 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2065 2066 pinctrl-names = "default"; 2067 pinctrl-0 = <&pcie2_default_state>; 2068 2069 status = "disabled"; 2070 }; 2071 2072 pcie2_phy: phy@1c16000 { 2073 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2074 reg = <0 0x1c16000 0 0x1c0>; 2075 #address-cells = <2>; 2076 #size-cells = <2>; 2077 ranges; 2078 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2079 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2080 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2081 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2082 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2083 2084 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2085 reset-names = "phy"; 2086 2087 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2088 assigned-clock-rates = <100000000>; 2089 2090 status = "disabled"; 2091 2092 pcie2_lane: phy@1c16200 { 2093 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 2094 <0 0x1c16400 0 0x200>, /* rx0 */ 2095 <0 0x1c16a00 0 0x1f0>, /* pcs */ 2096 <0 0x1c16600 0 0x170>, /* tx1 */ 2097 <0 0x1c16800 0 0x200>, /* rx1 */ 2098 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2099 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2100 clock-names = "pipe0"; 2101 2102 #phy-cells = <0>; 2103 2104 #clock-cells = <0>; 2105 clock-output-names = "pcie_2_pipe_clk"; 2106 }; 2107 }; 2108 2109 ufs_mem_hc: ufshc@1d84000 { 2110 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2111 "jedec,ufs-2.0"; 2112 reg = <0 0x01d84000 0 0x3000>; 2113 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2114 phys = <&ufs_mem_phy_lanes>; 2115 phy-names = "ufsphy"; 2116 lanes-per-direction = <2>; 2117 #reset-cells = <1>; 2118 resets = <&gcc GCC_UFS_PHY_BCR>; 2119 reset-names = "rst"; 2120 2121 power-domains = <&gcc UFS_PHY_GDSC>; 2122 2123 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2124 2125 clock-names = 2126 "core_clk", 2127 "bus_aggr_clk", 2128 "iface_clk", 2129 "core_clk_unipro", 2130 "ref_clk", 2131 "tx_lane0_sync_clk", 2132 "rx_lane0_sync_clk", 2133 "rx_lane1_sync_clk"; 2134 clocks = 2135 <&gcc GCC_UFS_PHY_AXI_CLK>, 2136 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2137 <&gcc GCC_UFS_PHY_AHB_CLK>, 2138 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2139 <&rpmhcc RPMH_CXO_CLK>, 2140 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2141 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2142 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2143 freq-table-hz = 2144 <37500000 300000000>, 2145 <0 0>, 2146 <0 0>, 2147 <37500000 300000000>, 2148 <0 0>, 2149 <0 0>, 2150 <0 0>, 2151 <0 0>; 2152 2153 status = "disabled"; 2154 }; 2155 2156 ufs_mem_phy: phy@1d87000 { 2157 compatible = "qcom,sm8250-qmp-ufs-phy"; 2158 reg = <0 0x01d87000 0 0x1c0>; 2159 #address-cells = <2>; 2160 #size-cells = <2>; 2161 ranges; 2162 clock-names = "ref", 2163 "ref_aux"; 2164 clocks = <&rpmhcc RPMH_CXO_CLK>, 2165 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2166 2167 resets = <&ufs_mem_hc 0>; 2168 reset-names = "ufsphy"; 2169 status = "disabled"; 2170 2171 ufs_mem_phy_lanes: phy@1d87400 { 2172 reg = <0 0x01d87400 0 0x108>, 2173 <0 0x01d87600 0 0x1e0>, 2174 <0 0x01d87c00 0 0x1dc>, 2175 <0 0x01d87800 0 0x108>, 2176 <0 0x01d87a00 0 0x1e0>; 2177 #phy-cells = <0>; 2178 }; 2179 }; 2180 2181 ipa_virt: interconnect@1e00000 { 2182 compatible = "qcom,sm8250-ipa-virt"; 2183 reg = <0 0x01e00000 0 0x1000>; 2184 #interconnect-cells = <1>; 2185 qcom,bcm-voters = <&apps_bcm_voter>; 2186 }; 2187 2188 tcsr_mutex: hwlock@1f40000 { 2189 compatible = "qcom,tcsr-mutex"; 2190 reg = <0x0 0x01f40000 0x0 0x40000>; 2191 #hwlock-cells = <1>; 2192 }; 2193 2194 wsamacro: codec@3240000 { 2195 compatible = "qcom,sm8250-lpass-wsa-macro"; 2196 reg = <0 0x03240000 0 0x1000>; 2197 clocks = <&audiocc 1>, 2198 <&audiocc 0>, 2199 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2200 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2201 <&aoncc 0>, 2202 <&vamacro>; 2203 2204 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2205 2206 #clock-cells = <0>; 2207 clock-frequency = <9600000>; 2208 clock-output-names = "mclk"; 2209 #sound-dai-cells = <1>; 2210 2211 pinctrl-names = "default"; 2212 pinctrl-0 = <&wsa_swr_active>; 2213 }; 2214 2215 swr0: soundwire-controller@3250000 { 2216 reg = <0 0x03250000 0 0x2000>; 2217 compatible = "qcom,soundwire-v1.5.1"; 2218 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2219 clocks = <&wsamacro>; 2220 clock-names = "iface"; 2221 2222 qcom,din-ports = <2>; 2223 qcom,dout-ports = <6>; 2224 2225 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2226 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2227 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2228 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2229 2230 #sound-dai-cells = <1>; 2231 #address-cells = <2>; 2232 #size-cells = <0>; 2233 }; 2234 2235 audiocc: clock-controller@3300000 { 2236 compatible = "qcom,sm8250-lpass-audiocc"; 2237 reg = <0 0x03300000 0 0x30000>; 2238 #clock-cells = <1>; 2239 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2240 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2241 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2242 clock-names = "core", "audio", "bus"; 2243 }; 2244 2245 vamacro: codec@3370000 { 2246 compatible = "qcom,sm8250-lpass-va-macro"; 2247 reg = <0 0x03370000 0 0x1000>; 2248 clocks = <&aoncc 0>, 2249 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2250 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2251 2252 clock-names = "mclk", "macro", "dcodec"; 2253 2254 #clock-cells = <0>; 2255 clock-frequency = <9600000>; 2256 clock-output-names = "fsgen"; 2257 #sound-dai-cells = <1>; 2258 }; 2259 2260 rxmacro: rxmacro@3200000 { 2261 pinctrl-names = "default"; 2262 pinctrl-0 = <&rx_swr_active>; 2263 compatible = "qcom,sm8250-lpass-rx-macro"; 2264 reg = <0 0x3200000 0 0x1000>; 2265 status = "disabled"; 2266 2267 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2268 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2269 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2270 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2271 <&vamacro>; 2272 2273 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2274 2275 #clock-cells = <0>; 2276 clock-frequency = <9600000>; 2277 clock-output-names = "mclk"; 2278 #sound-dai-cells = <1>; 2279 }; 2280 2281 swr1: soundwire-controller@3210000 { 2282 reg = <0 0x3210000 0 0x2000>; 2283 compatible = "qcom,soundwire-v1.5.1"; 2284 status = "disabled"; 2285 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2286 clocks = <&rxmacro>; 2287 clock-names = "iface"; 2288 label = "RX"; 2289 qcom,din-ports = <0>; 2290 qcom,dout-ports = <5>; 2291 2292 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; 2293 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2294 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2295 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; 2296 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; 2297 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; 2298 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; 2299 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2300 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; 2301 2302 #sound-dai-cells = <1>; 2303 #address-cells = <2>; 2304 #size-cells = <0>; 2305 }; 2306 2307 txmacro: txmacro@3220000 { 2308 pinctrl-names = "default"; 2309 pinctrl-0 = <&tx_swr_active>; 2310 compatible = "qcom,sm8250-lpass-tx-macro"; 2311 reg = <0 0x3220000 0 0x1000>; 2312 status = "disabled"; 2313 2314 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2315 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2316 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2317 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2318 <&vamacro>; 2319 2320 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2321 2322 #clock-cells = <0>; 2323 clock-frequency = <9600000>; 2324 clock-output-names = "mclk"; 2325 #address-cells = <2>; 2326 #size-cells = <2>; 2327 #sound-dai-cells = <1>; 2328 }; 2329 2330 /* tx macro */ 2331 swr2: soundwire-controller@3230000 { 2332 reg = <0 0x3230000 0 0x2000>; 2333 compatible = "qcom,soundwire-v1.5.1"; 2334 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2335 interrupt-names = "core"; 2336 status = "disabled"; 2337 2338 clocks = <&txmacro>; 2339 clock-names = "iface"; 2340 label = "TX"; 2341 2342 qcom,din-ports = <5>; 2343 qcom,dout-ports = <0>; 2344 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; 2345 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; 2346 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; 2347 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2348 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2349 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2350 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2351 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2352 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; 2353 qcom,port-offset = <1>; 2354 #sound-dai-cells = <1>; 2355 #address-cells = <2>; 2356 #size-cells = <0>; 2357 }; 2358 2359 aoncc: clock-controller@3380000 { 2360 compatible = "qcom,sm8250-lpass-aoncc"; 2361 reg = <0 0x03380000 0 0x40000>; 2362 #clock-cells = <1>; 2363 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2364 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2365 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2366 clock-names = "core", "audio", "bus"; 2367 }; 2368 2369 lpass_tlmm: pinctrl@33c0000{ 2370 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2371 reg = <0 0x033c0000 0x0 0x20000>, 2372 <0 0x03550000 0x0 0x10000>; 2373 gpio-controller; 2374 #gpio-cells = <2>; 2375 gpio-ranges = <&lpass_tlmm 0 0 14>; 2376 2377 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2378 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2379 clock-names = "core", "audio"; 2380 2381 wsa_swr_active: wsa-swr-active-pins { 2382 clk { 2383 pins = "gpio10"; 2384 function = "wsa_swr_clk"; 2385 drive-strength = <2>; 2386 slew-rate = <1>; 2387 bias-disable; 2388 }; 2389 2390 data { 2391 pins = "gpio11"; 2392 function = "wsa_swr_data"; 2393 drive-strength = <2>; 2394 slew-rate = <1>; 2395 bias-bus-hold; 2396 2397 }; 2398 }; 2399 2400 wsa_swr_sleep: wsa-swr-sleep-pins { 2401 clk { 2402 pins = "gpio10"; 2403 function = "wsa_swr_clk"; 2404 drive-strength = <2>; 2405 input-enable; 2406 bias-pull-down; 2407 }; 2408 2409 data { 2410 pins = "gpio11"; 2411 function = "wsa_swr_data"; 2412 drive-strength = <2>; 2413 input-enable; 2414 bias-pull-down; 2415 2416 }; 2417 }; 2418 2419 dmic01_active: dmic01-active-pins { 2420 clk { 2421 pins = "gpio6"; 2422 function = "dmic1_clk"; 2423 drive-strength = <8>; 2424 output-high; 2425 }; 2426 data { 2427 pins = "gpio7"; 2428 function = "dmic1_data"; 2429 drive-strength = <8>; 2430 input-enable; 2431 }; 2432 }; 2433 2434 dmic01_sleep: dmic01-sleep-pins { 2435 clk { 2436 pins = "gpio6"; 2437 function = "dmic1_clk"; 2438 drive-strength = <2>; 2439 bias-disable; 2440 output-low; 2441 }; 2442 2443 data { 2444 pins = "gpio7"; 2445 function = "dmic1_data"; 2446 drive-strength = <2>; 2447 pull-down; 2448 input-enable; 2449 }; 2450 }; 2451 2452 rx_swr_active: rx_swr-active-pins { 2453 clk { 2454 pins = "gpio3"; 2455 function = "swr_rx_clk"; 2456 drive-strength = <2>; 2457 slew-rate = <1>; 2458 bias-disable; 2459 }; 2460 2461 data { 2462 pins = "gpio4", "gpio5"; 2463 function = "swr_rx_data"; 2464 drive-strength = <2>; 2465 slew-rate = <1>; 2466 bias-bus-hold; 2467 }; 2468 }; 2469 2470 tx_swr_active: tx_swr-active-pins { 2471 clk { 2472 pins = "gpio0"; 2473 function = "swr_tx_clk"; 2474 drive-strength = <2>; 2475 slew-rate = <1>; 2476 bias-disable; 2477 }; 2478 2479 data { 2480 pins = "gpio1", "gpio2"; 2481 function = "swr_tx_data"; 2482 drive-strength = <2>; 2483 slew-rate = <1>; 2484 bias-bus-hold; 2485 }; 2486 }; 2487 2488 tx_swr_sleep: tx_swr-sleep-pins { 2489 clk { 2490 pins = "gpio0"; 2491 function = "swr_tx_clk"; 2492 drive-strength = <2>; 2493 input-enable; 2494 bias-pull-down; 2495 }; 2496 2497 data1 { 2498 pins = "gpio1"; 2499 function = "swr_tx_data"; 2500 drive-strength = <2>; 2501 input-enable; 2502 bias-bus-hold; 2503 }; 2504 2505 data2 { 2506 pins = "gpio2"; 2507 function = "swr_tx_data"; 2508 drive-strength = <2>; 2509 input-enable; 2510 bias-pull-down; 2511 }; 2512 }; 2513 }; 2514 2515 gpu: gpu@3d00000 { 2516 compatible = "qcom,adreno-650.2", 2517 "qcom,adreno"; 2518 2519 reg = <0 0x03d00000 0 0x40000>; 2520 reg-names = "kgsl_3d0_reg_memory"; 2521 2522 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2523 2524 iommus = <&adreno_smmu 0 0x401>; 2525 2526 operating-points-v2 = <&gpu_opp_table>; 2527 2528 qcom,gmu = <&gmu>; 2529 2530 status = "disabled"; 2531 2532 zap-shader { 2533 memory-region = <&gpu_mem>; 2534 }; 2535 2536 /* note: downstream checks gpu binning for 670 Mhz */ 2537 gpu_opp_table: opp-table { 2538 compatible = "operating-points-v2"; 2539 2540 opp-670000000 { 2541 opp-hz = /bits/ 64 <670000000>; 2542 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2543 }; 2544 2545 opp-587000000 { 2546 opp-hz = /bits/ 64 <587000000>; 2547 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2548 }; 2549 2550 opp-525000000 { 2551 opp-hz = /bits/ 64 <525000000>; 2552 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2553 }; 2554 2555 opp-490000000 { 2556 opp-hz = /bits/ 64 <490000000>; 2557 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2558 }; 2559 2560 opp-441600000 { 2561 opp-hz = /bits/ 64 <441600000>; 2562 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2563 }; 2564 2565 opp-400000000 { 2566 opp-hz = /bits/ 64 <400000000>; 2567 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2568 }; 2569 2570 opp-305000000 { 2571 opp-hz = /bits/ 64 <305000000>; 2572 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2573 }; 2574 }; 2575 }; 2576 2577 gmu: gmu@3d6a000 { 2578 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2579 2580 reg = <0 0x03d6a000 0 0x30000>, 2581 <0 0x3de0000 0 0x10000>, 2582 <0 0xb290000 0 0x10000>, 2583 <0 0xb490000 0 0x10000>; 2584 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2585 2586 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2588 interrupt-names = "hfi", "gmu"; 2589 2590 clocks = <&gpucc GPU_CC_AHB_CLK>, 2591 <&gpucc GPU_CC_CX_GMU_CLK>, 2592 <&gpucc GPU_CC_CXO_CLK>, 2593 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2594 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2595 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2596 2597 power-domains = <&gpucc GPU_CX_GDSC>, 2598 <&gpucc GPU_GX_GDSC>; 2599 power-domain-names = "cx", "gx"; 2600 2601 iommus = <&adreno_smmu 5 0x400>; 2602 2603 operating-points-v2 = <&gmu_opp_table>; 2604 2605 status = "disabled"; 2606 2607 gmu_opp_table: opp-table { 2608 compatible = "operating-points-v2"; 2609 2610 opp-200000000 { 2611 opp-hz = /bits/ 64 <200000000>; 2612 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2613 }; 2614 }; 2615 }; 2616 2617 gpucc: clock-controller@3d90000 { 2618 compatible = "qcom,sm8250-gpucc"; 2619 reg = <0 0x03d90000 0 0x9000>; 2620 clocks = <&rpmhcc RPMH_CXO_CLK>, 2621 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2622 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2623 clock-names = "bi_tcxo", 2624 "gcc_gpu_gpll0_clk_src", 2625 "gcc_gpu_gpll0_div_clk_src"; 2626 #clock-cells = <1>; 2627 #reset-cells = <1>; 2628 #power-domain-cells = <1>; 2629 }; 2630 2631 adreno_smmu: iommu@3da0000 { 2632 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 2633 reg = <0 0x03da0000 0 0x10000>; 2634 #iommu-cells = <2>; 2635 #global-interrupts = <2>; 2636 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2637 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2638 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2639 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2640 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2641 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2642 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2643 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2644 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2645 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2646 clocks = <&gpucc GPU_CC_AHB_CLK>, 2647 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2648 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2649 clock-names = "ahb", "bus", "iface"; 2650 2651 power-domains = <&gpucc GPU_CX_GDSC>; 2652 }; 2653 2654 slpi: remoteproc@5c00000 { 2655 compatible = "qcom,sm8250-slpi-pas"; 2656 reg = <0 0x05c00000 0 0x4000>; 2657 2658 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2659 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2660 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2661 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2662 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2663 interrupt-names = "wdog", "fatal", "ready", 2664 "handover", "stop-ack"; 2665 2666 clocks = <&rpmhcc RPMH_CXO_CLK>; 2667 clock-names = "xo"; 2668 2669 power-domains = <&rpmhpd SM8250_LCX>, 2670 <&rpmhpd SM8250_LMX>; 2671 power-domain-names = "lcx", "lmx"; 2672 2673 memory-region = <&slpi_mem>; 2674 2675 qcom,qmp = <&aoss_qmp>; 2676 2677 qcom,smem-states = <&smp2p_slpi_out 0>; 2678 qcom,smem-state-names = "stop"; 2679 2680 status = "disabled"; 2681 2682 glink-edge { 2683 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2684 IPCC_MPROC_SIGNAL_GLINK_QMP 2685 IRQ_TYPE_EDGE_RISING>; 2686 mboxes = <&ipcc IPCC_CLIENT_SLPI 2687 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2688 2689 label = "slpi"; 2690 qcom,remote-pid = <3>; 2691 2692 fastrpc { 2693 compatible = "qcom,fastrpc"; 2694 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2695 label = "sdsp"; 2696 qcom,non-secure-domain; 2697 #address-cells = <1>; 2698 #size-cells = <0>; 2699 2700 compute-cb@1 { 2701 compatible = "qcom,fastrpc-compute-cb"; 2702 reg = <1>; 2703 iommus = <&apps_smmu 0x0541 0x0>; 2704 }; 2705 2706 compute-cb@2 { 2707 compatible = "qcom,fastrpc-compute-cb"; 2708 reg = <2>; 2709 iommus = <&apps_smmu 0x0542 0x0>; 2710 }; 2711 2712 compute-cb@3 { 2713 compatible = "qcom,fastrpc-compute-cb"; 2714 reg = <3>; 2715 iommus = <&apps_smmu 0x0543 0x0>; 2716 /* note: shared-cb = <4> in downstream */ 2717 }; 2718 }; 2719 }; 2720 }; 2721 2722 cdsp: remoteproc@8300000 { 2723 compatible = "qcom,sm8250-cdsp-pas"; 2724 reg = <0 0x08300000 0 0x10000>; 2725 2726 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2727 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2728 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2729 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2730 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2731 interrupt-names = "wdog", "fatal", "ready", 2732 "handover", "stop-ack"; 2733 2734 clocks = <&rpmhcc RPMH_CXO_CLK>; 2735 clock-names = "xo"; 2736 2737 power-domains = <&rpmhpd SM8250_CX>; 2738 2739 memory-region = <&cdsp_mem>; 2740 2741 qcom,qmp = <&aoss_qmp>; 2742 2743 qcom,smem-states = <&smp2p_cdsp_out 0>; 2744 qcom,smem-state-names = "stop"; 2745 2746 status = "disabled"; 2747 2748 glink-edge { 2749 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2750 IPCC_MPROC_SIGNAL_GLINK_QMP 2751 IRQ_TYPE_EDGE_RISING>; 2752 mboxes = <&ipcc IPCC_CLIENT_CDSP 2753 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2754 2755 label = "cdsp"; 2756 qcom,remote-pid = <5>; 2757 2758 fastrpc { 2759 compatible = "qcom,fastrpc"; 2760 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2761 label = "cdsp"; 2762 qcom,non-secure-domain; 2763 #address-cells = <1>; 2764 #size-cells = <0>; 2765 2766 compute-cb@1 { 2767 compatible = "qcom,fastrpc-compute-cb"; 2768 reg = <1>; 2769 iommus = <&apps_smmu 0x1001 0x0460>; 2770 }; 2771 2772 compute-cb@2 { 2773 compatible = "qcom,fastrpc-compute-cb"; 2774 reg = <2>; 2775 iommus = <&apps_smmu 0x1002 0x0460>; 2776 }; 2777 2778 compute-cb@3 { 2779 compatible = "qcom,fastrpc-compute-cb"; 2780 reg = <3>; 2781 iommus = <&apps_smmu 0x1003 0x0460>; 2782 }; 2783 2784 compute-cb@4 { 2785 compatible = "qcom,fastrpc-compute-cb"; 2786 reg = <4>; 2787 iommus = <&apps_smmu 0x1004 0x0460>; 2788 }; 2789 2790 compute-cb@5 { 2791 compatible = "qcom,fastrpc-compute-cb"; 2792 reg = <5>; 2793 iommus = <&apps_smmu 0x1005 0x0460>; 2794 }; 2795 2796 compute-cb@6 { 2797 compatible = "qcom,fastrpc-compute-cb"; 2798 reg = <6>; 2799 iommus = <&apps_smmu 0x1006 0x0460>; 2800 }; 2801 2802 compute-cb@7 { 2803 compatible = "qcom,fastrpc-compute-cb"; 2804 reg = <7>; 2805 iommus = <&apps_smmu 0x1007 0x0460>; 2806 }; 2807 2808 compute-cb@8 { 2809 compatible = "qcom,fastrpc-compute-cb"; 2810 reg = <8>; 2811 iommus = <&apps_smmu 0x1008 0x0460>; 2812 }; 2813 2814 /* note: secure cb9 in downstream */ 2815 }; 2816 }; 2817 }; 2818 2819 sound: sound { 2820 }; 2821 2822 usb_1_hsphy: phy@88e3000 { 2823 compatible = "qcom,sm8250-usb-hs-phy", 2824 "qcom,usb-snps-hs-7nm-phy"; 2825 reg = <0 0x088e3000 0 0x400>; 2826 status = "disabled"; 2827 #phy-cells = <0>; 2828 2829 clocks = <&rpmhcc RPMH_CXO_CLK>; 2830 clock-names = "ref"; 2831 2832 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2833 }; 2834 2835 usb_2_hsphy: phy@88e4000 { 2836 compatible = "qcom,sm8250-usb-hs-phy", 2837 "qcom,usb-snps-hs-7nm-phy"; 2838 reg = <0 0x088e4000 0 0x400>; 2839 status = "disabled"; 2840 #phy-cells = <0>; 2841 2842 clocks = <&rpmhcc RPMH_CXO_CLK>; 2843 clock-names = "ref"; 2844 2845 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2846 }; 2847 2848 usb_1_qmpphy: phy@88e9000 { 2849 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 2850 reg = <0 0x088e9000 0 0x200>, 2851 <0 0x088e8000 0 0x40>, 2852 <0 0x088ea000 0 0x200>; 2853 status = "disabled"; 2854 #address-cells = <2>; 2855 #size-cells = <2>; 2856 ranges; 2857 2858 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2859 <&rpmhcc RPMH_CXO_CLK>, 2860 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2861 clock-names = "aux", "ref_clk_src", "com_aux"; 2862 2863 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2864 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2865 reset-names = "phy", "common"; 2866 2867 usb_1_ssphy: usb3-phy@88e9200 { 2868 reg = <0 0x088e9200 0 0x200>, 2869 <0 0x088e9400 0 0x200>, 2870 <0 0x088e9c00 0 0x400>, 2871 <0 0x088e9600 0 0x200>, 2872 <0 0x088e9800 0 0x200>, 2873 <0 0x088e9a00 0 0x100>; 2874 #clock-cells = <0>; 2875 #phy-cells = <0>; 2876 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2877 clock-names = "pipe0"; 2878 clock-output-names = "usb3_phy_pipe_clk_src"; 2879 }; 2880 2881 dp_phy: dp-phy@88ea200 { 2882 reg = <0 0x088ea200 0 0x200>, 2883 <0 0x088ea400 0 0x200>, 2884 <0 0x088eac00 0 0x400>, 2885 <0 0x088ea600 0 0x200>, 2886 <0 0x088ea800 0 0x200>, 2887 <0 0x088eaa00 0 0x100>; 2888 #phy-cells = <0>; 2889 #clock-cells = <1>; 2890 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2891 clock-names = "pipe0"; 2892 clock-output-names = "usb3_phy_pipe_clk_src"; 2893 }; 2894 }; 2895 2896 usb_2_qmpphy: phy@88eb000 { 2897 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2898 reg = <0 0x088eb000 0 0x200>; 2899 status = "disabled"; 2900 #address-cells = <2>; 2901 #size-cells = <2>; 2902 ranges; 2903 2904 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2905 <&rpmhcc RPMH_CXO_CLK>, 2906 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2907 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2908 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2909 2910 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2911 <&gcc GCC_USB3_PHY_SEC_BCR>; 2912 reset-names = "phy", "common"; 2913 2914 usb_2_ssphy: phy@88eb200 { 2915 reg = <0 0x088eb200 0 0x200>, 2916 <0 0x088eb400 0 0x200>, 2917 <0 0x088eb800 0 0x800>; 2918 #clock-cells = <0>; 2919 #phy-cells = <0>; 2920 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2921 clock-names = "pipe0"; 2922 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2923 }; 2924 }; 2925 2926 sdhc_2: sdhci@8804000 { 2927 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2928 reg = <0 0x08804000 0 0x1000>; 2929 2930 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2931 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2932 interrupt-names = "hc_irq", "pwr_irq"; 2933 2934 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2935 <&gcc GCC_SDCC2_APPS_CLK>, 2936 <&rpmhcc RPMH_CXO_CLK>; 2937 clock-names = "iface", "core", "xo"; 2938 iommus = <&apps_smmu 0x4a0 0x0>; 2939 qcom,dll-config = <0x0007642c>; 2940 qcom,ddr-config = <0x80040868>; 2941 power-domains = <&rpmhpd SM8250_CX>; 2942 operating-points-v2 = <&sdhc2_opp_table>; 2943 2944 status = "disabled"; 2945 2946 sdhc2_opp_table: sdhc2-opp-table { 2947 compatible = "operating-points-v2"; 2948 2949 opp-19200000 { 2950 opp-hz = /bits/ 64 <19200000>; 2951 required-opps = <&rpmhpd_opp_min_svs>; 2952 }; 2953 2954 opp-50000000 { 2955 opp-hz = /bits/ 64 <50000000>; 2956 required-opps = <&rpmhpd_opp_low_svs>; 2957 }; 2958 2959 opp-100000000 { 2960 opp-hz = /bits/ 64 <100000000>; 2961 required-opps = <&rpmhpd_opp_svs>; 2962 }; 2963 2964 opp-202000000 { 2965 opp-hz = /bits/ 64 <202000000>; 2966 required-opps = <&rpmhpd_opp_svs_l1>; 2967 }; 2968 }; 2969 }; 2970 2971 dc_noc: interconnect@90c0000 { 2972 compatible = "qcom,sm8250-dc-noc"; 2973 reg = <0 0x090c0000 0 0x4200>; 2974 #interconnect-cells = <1>; 2975 qcom,bcm-voters = <&apps_bcm_voter>; 2976 }; 2977 2978 gem_noc: interconnect@9100000 { 2979 compatible = "qcom,sm8250-gem-noc"; 2980 reg = <0 0x09100000 0 0xb4000>; 2981 #interconnect-cells = <1>; 2982 qcom,bcm-voters = <&apps_bcm_voter>; 2983 }; 2984 2985 npu_noc: interconnect@9990000 { 2986 compatible = "qcom,sm8250-npu-noc"; 2987 reg = <0 0x09990000 0 0x1600>; 2988 #interconnect-cells = <1>; 2989 qcom,bcm-voters = <&apps_bcm_voter>; 2990 }; 2991 2992 usb_1: usb@a6f8800 { 2993 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2994 reg = <0 0x0a6f8800 0 0x400>; 2995 status = "disabled"; 2996 #address-cells = <2>; 2997 #size-cells = <2>; 2998 ranges; 2999 dma-ranges; 3000 3001 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3002 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3003 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3004 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3005 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3006 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3007 clock-names = "cfg_noc", 3008 "core", 3009 "iface", 3010 "sleep", 3011 "mock_utmi", 3012 "xo"; 3013 3014 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3015 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3016 assigned-clock-rates = <19200000>, <200000000>; 3017 3018 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3019 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3020 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3021 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3022 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3023 "dm_hs_phy_irq", "ss_phy_irq"; 3024 3025 power-domains = <&gcc USB30_PRIM_GDSC>; 3026 3027 resets = <&gcc GCC_USB30_PRIM_BCR>; 3028 3029 usb_1_dwc3: usb@a600000 { 3030 compatible = "snps,dwc3"; 3031 reg = <0 0x0a600000 0 0xcd00>; 3032 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3033 iommus = <&apps_smmu 0x0 0x0>; 3034 snps,dis_u2_susphy_quirk; 3035 snps,dis_enblslpm_quirk; 3036 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3037 phy-names = "usb2-phy", "usb3-phy"; 3038 }; 3039 }; 3040 3041 system-cache-controller@9200000 { 3042 compatible = "qcom,sm8250-llcc"; 3043 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 3044 reg-names = "llcc_base", "llcc_broadcast_base"; 3045 }; 3046 3047 usb_2: usb@a8f8800 { 3048 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3049 reg = <0 0x0a8f8800 0 0x400>; 3050 status = "disabled"; 3051 #address-cells = <2>; 3052 #size-cells = <2>; 3053 ranges; 3054 dma-ranges; 3055 3056 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3057 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3058 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3059 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3060 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3061 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3062 clock-names = "cfg_noc", 3063 "core", 3064 "iface", 3065 "sleep", 3066 "mock_utmi", 3067 "xo"; 3068 3069 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3070 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3071 assigned-clock-rates = <19200000>, <200000000>; 3072 3073 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3074 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3075 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3076 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 3077 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3078 "dm_hs_phy_irq", "ss_phy_irq"; 3079 3080 power-domains = <&gcc USB30_SEC_GDSC>; 3081 3082 resets = <&gcc GCC_USB30_SEC_BCR>; 3083 3084 usb_2_dwc3: usb@a800000 { 3085 compatible = "snps,dwc3"; 3086 reg = <0 0x0a800000 0 0xcd00>; 3087 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3088 iommus = <&apps_smmu 0x20 0>; 3089 snps,dis_u2_susphy_quirk; 3090 snps,dis_enblslpm_quirk; 3091 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3092 phy-names = "usb2-phy", "usb3-phy"; 3093 }; 3094 }; 3095 3096 venus: video-codec@aa00000 { 3097 compatible = "qcom,sm8250-venus"; 3098 reg = <0 0x0aa00000 0 0x100000>; 3099 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3100 power-domains = <&videocc MVS0C_GDSC>, 3101 <&videocc MVS0_GDSC>, 3102 <&rpmhpd SM8250_MX>; 3103 power-domain-names = "venus", "vcodec0", "mx"; 3104 operating-points-v2 = <&venus_opp_table>; 3105 3106 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3107 <&videocc VIDEO_CC_MVS0C_CLK>, 3108 <&videocc VIDEO_CC_MVS0_CLK>; 3109 clock-names = "iface", "core", "vcodec0_core"; 3110 3111 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 3112 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 3113 interconnect-names = "cpu-cfg", "video-mem"; 3114 3115 iommus = <&apps_smmu 0x2100 0x0400>; 3116 memory-region = <&video_mem>; 3117 3118 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3119 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3120 reset-names = "bus", "core"; 3121 3122 status = "disabled"; 3123 3124 video-decoder { 3125 compatible = "venus-decoder"; 3126 }; 3127 3128 video-encoder { 3129 compatible = "venus-encoder"; 3130 }; 3131 3132 venus_opp_table: venus-opp-table { 3133 compatible = "operating-points-v2"; 3134 3135 opp-720000000 { 3136 opp-hz = /bits/ 64 <720000000>; 3137 required-opps = <&rpmhpd_opp_low_svs>; 3138 }; 3139 3140 opp-1014000000 { 3141 opp-hz = /bits/ 64 <1014000000>; 3142 required-opps = <&rpmhpd_opp_svs>; 3143 }; 3144 3145 opp-1098000000 { 3146 opp-hz = /bits/ 64 <1098000000>; 3147 required-opps = <&rpmhpd_opp_svs_l1>; 3148 }; 3149 3150 opp-1332000000 { 3151 opp-hz = /bits/ 64 <1332000000>; 3152 required-opps = <&rpmhpd_opp_nom>; 3153 }; 3154 }; 3155 }; 3156 3157 videocc: clock-controller@abf0000 { 3158 compatible = "qcom,sm8250-videocc"; 3159 reg = <0 0x0abf0000 0 0x10000>; 3160 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3161 <&rpmhcc RPMH_CXO_CLK>, 3162 <&rpmhcc RPMH_CXO_CLK_A>; 3163 power-domains = <&rpmhpd SM8250_MMCX>; 3164 required-opps = <&rpmhpd_opp_low_svs>; 3165 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3166 #clock-cells = <1>; 3167 #reset-cells = <1>; 3168 #power-domain-cells = <1>; 3169 }; 3170 3171 cci0: cci@ac4f000 { 3172 compatible = "qcom,sm8250-cci"; 3173 #address-cells = <1>; 3174 #size-cells = <0>; 3175 3176 reg = <0 0x0ac4f000 0 0x1000>; 3177 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3178 power-domains = <&camcc TITAN_TOP_GDSC>; 3179 3180 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3181 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3182 <&camcc CAM_CC_CPAS_AHB_CLK>, 3183 <&camcc CAM_CC_CCI_0_CLK>, 3184 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3185 clock-names = "camnoc_axi", 3186 "slow_ahb_src", 3187 "cpas_ahb", 3188 "cci", 3189 "cci_src"; 3190 3191 pinctrl-0 = <&cci0_default>; 3192 pinctrl-1 = <&cci0_sleep>; 3193 pinctrl-names = "default", "sleep"; 3194 3195 status = "disabled"; 3196 3197 cci0_i2c0: i2c-bus@0 { 3198 reg = <0>; 3199 clock-frequency = <1000000>; 3200 #address-cells = <1>; 3201 #size-cells = <0>; 3202 }; 3203 3204 cci0_i2c1: i2c-bus@1 { 3205 reg = <1>; 3206 clock-frequency = <1000000>; 3207 #address-cells = <1>; 3208 #size-cells = <0>; 3209 }; 3210 }; 3211 3212 cci1: cci@ac50000 { 3213 compatible = "qcom,sm8250-cci"; 3214 #address-cells = <1>; 3215 #size-cells = <0>; 3216 3217 reg = <0 0x0ac50000 0 0x1000>; 3218 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3219 power-domains = <&camcc TITAN_TOP_GDSC>; 3220 3221 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3222 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3223 <&camcc CAM_CC_CPAS_AHB_CLK>, 3224 <&camcc CAM_CC_CCI_1_CLK>, 3225 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3226 clock-names = "camnoc_axi", 3227 "slow_ahb_src", 3228 "cpas_ahb", 3229 "cci", 3230 "cci_src"; 3231 3232 pinctrl-0 = <&cci1_default>; 3233 pinctrl-1 = <&cci1_sleep>; 3234 pinctrl-names = "default", "sleep"; 3235 3236 status = "disabled"; 3237 3238 cci1_i2c0: i2c-bus@0 { 3239 reg = <0>; 3240 clock-frequency = <1000000>; 3241 #address-cells = <1>; 3242 #size-cells = <0>; 3243 }; 3244 3245 cci1_i2c1: i2c-bus@1 { 3246 reg = <1>; 3247 clock-frequency = <1000000>; 3248 #address-cells = <1>; 3249 #size-cells = <0>; 3250 }; 3251 }; 3252 3253 camss: camss@ac6a000 { 3254 compatible = "qcom,sm8250-camss"; 3255 status = "disabled"; 3256 3257 reg = <0 0xac6a000 0 0x2000>, 3258 <0 0xac6c000 0 0x2000>, 3259 <0 0xac6e000 0 0x1000>, 3260 <0 0xac70000 0 0x1000>, 3261 <0 0xac72000 0 0x1000>, 3262 <0 0xac74000 0 0x1000>, 3263 <0 0xacb4000 0 0xd000>, 3264 <0 0xacc3000 0 0xd000>, 3265 <0 0xacd9000 0 0x2200>, 3266 <0 0xacdb200 0 0x2200>; 3267 reg-names = "csiphy0", 3268 "csiphy1", 3269 "csiphy2", 3270 "csiphy3", 3271 "csiphy4", 3272 "csiphy5", 3273 "vfe0", 3274 "vfe1", 3275 "vfe_lite0", 3276 "vfe_lite1"; 3277 3278 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 3292 interrupt-names = "csiphy0", 3293 "csiphy1", 3294 "csiphy2", 3295 "csiphy3", 3296 "csiphy4", 3297 "csiphy5", 3298 "csid0", 3299 "csid1", 3300 "csid2", 3301 "csid3", 3302 "vfe0", 3303 "vfe1", 3304 "vfe_lite0", 3305 "vfe_lite1"; 3306 3307 power-domains = <&camcc IFE_0_GDSC>, 3308 <&camcc IFE_1_GDSC>, 3309 <&camcc TITAN_TOP_GDSC>; 3310 3311 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3312 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3313 <&gcc GCC_CAMERA_SF_AXI_CLK>, 3314 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3315 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 3316 <&camcc CAM_CC_CORE_AHB_CLK>, 3317 <&camcc CAM_CC_CPAS_AHB_CLK>, 3318 <&camcc CAM_CC_CSIPHY0_CLK>, 3319 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 3320 <&camcc CAM_CC_CSIPHY1_CLK>, 3321 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 3322 <&camcc CAM_CC_CSIPHY2_CLK>, 3323 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 3324 <&camcc CAM_CC_CSIPHY3_CLK>, 3325 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 3326 <&camcc CAM_CC_CSIPHY4_CLK>, 3327 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 3328 <&camcc CAM_CC_CSIPHY5_CLK>, 3329 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 3330 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3331 <&camcc CAM_CC_IFE_0_AHB_CLK>, 3332 <&camcc CAM_CC_IFE_0_AXI_CLK>, 3333 <&camcc CAM_CC_IFE_0_CLK>, 3334 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 3335 <&camcc CAM_CC_IFE_0_CSID_CLK>, 3336 <&camcc CAM_CC_IFE_0_AREG_CLK>, 3337 <&camcc CAM_CC_IFE_1_AHB_CLK>, 3338 <&camcc CAM_CC_IFE_1_AXI_CLK>, 3339 <&camcc CAM_CC_IFE_1_CLK>, 3340 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 3341 <&camcc CAM_CC_IFE_1_CSID_CLK>, 3342 <&camcc CAM_CC_IFE_1_AREG_CLK>, 3343 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 3344 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 3345 <&camcc CAM_CC_IFE_LITE_CLK>, 3346 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 3347 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 3348 3349 clock-names = "cam_ahb_clk", 3350 "cam_hf_axi", 3351 "cam_sf_axi", 3352 "camnoc_axi", 3353 "camnoc_axi_src", 3354 "core_ahb", 3355 "cpas_ahb", 3356 "csiphy0", 3357 "csiphy0_timer", 3358 "csiphy1", 3359 "csiphy1_timer", 3360 "csiphy2", 3361 "csiphy2_timer", 3362 "csiphy3", 3363 "csiphy3_timer", 3364 "csiphy4", 3365 "csiphy4_timer", 3366 "csiphy5", 3367 "csiphy5_timer", 3368 "slow_ahb_src", 3369 "vfe0_ahb", 3370 "vfe0_axi", 3371 "vfe0", 3372 "vfe0_cphy_rx", 3373 "vfe0_csid", 3374 "vfe0_areg", 3375 "vfe1_ahb", 3376 "vfe1_axi", 3377 "vfe1", 3378 "vfe1_cphy_rx", 3379 "vfe1_csid", 3380 "vfe1_areg", 3381 "vfe_lite_ahb", 3382 "vfe_lite_axi", 3383 "vfe_lite", 3384 "vfe_lite_cphy_rx", 3385 "vfe_lite_csid"; 3386 3387 iommus = <&apps_smmu 0x800 0x400>, 3388 <&apps_smmu 0x801 0x400>, 3389 <&apps_smmu 0x840 0x400>, 3390 <&apps_smmu 0x841 0x400>, 3391 <&apps_smmu 0xc00 0x400>, 3392 <&apps_smmu 0xc01 0x400>, 3393 <&apps_smmu 0xc40 0x400>, 3394 <&apps_smmu 0xc41 0x400>; 3395 3396 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, 3397 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, 3398 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, 3399 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; 3400 interconnect-names = "cam_ahb", 3401 "cam_hf_0_mnoc", 3402 "cam_sf_0_mnoc", 3403 "cam_sf_icp_mnoc"; 3404 }; 3405 3406 camcc: clock-controller@ad00000 { 3407 compatible = "qcom,sm8250-camcc"; 3408 reg = <0 0x0ad00000 0 0x10000>; 3409 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3410 <&rpmhcc RPMH_CXO_CLK>, 3411 <&rpmhcc RPMH_CXO_CLK_A>, 3412 <&sleep_clk>; 3413 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3414 power-domains = <&rpmhpd SM8250_MMCX>; 3415 required-opps = <&rpmhpd_opp_low_svs>; 3416 #clock-cells = <1>; 3417 #reset-cells = <1>; 3418 #power-domain-cells = <1>; 3419 }; 3420 3421 mdss: mdss@ae00000 { 3422 compatible = "qcom,sm8250-mdss"; 3423 reg = <0 0x0ae00000 0 0x1000>; 3424 reg-names = "mdss"; 3425 3426 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3427 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3428 interconnect-names = "mdp0-mem", "mdp1-mem"; 3429 3430 power-domains = <&dispcc MDSS_GDSC>; 3431 3432 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3433 <&gcc GCC_DISP_HF_AXI_CLK>, 3434 <&gcc GCC_DISP_SF_AXI_CLK>, 3435 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3436 clock-names = "iface", "bus", "nrt_bus", "core"; 3437 3438 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3439 assigned-clock-rates = <460000000>; 3440 3441 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3442 interrupt-controller; 3443 #interrupt-cells = <1>; 3444 3445 iommus = <&apps_smmu 0x820 0x402>; 3446 3447 status = "disabled"; 3448 3449 #address-cells = <2>; 3450 #size-cells = <2>; 3451 ranges; 3452 3453 mdss_mdp: mdp@ae01000 { 3454 compatible = "qcom,sm8250-dpu"; 3455 reg = <0 0x0ae01000 0 0x8f000>, 3456 <0 0x0aeb0000 0 0x2008>; 3457 reg-names = "mdp", "vbif"; 3458 3459 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3460 <&gcc GCC_DISP_HF_AXI_CLK>, 3461 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3462 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3463 clock-names = "iface", "bus", "core", "vsync"; 3464 3465 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3466 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3467 assigned-clock-rates = <460000000>, 3468 <19200000>; 3469 3470 operating-points-v2 = <&mdp_opp_table>; 3471 power-domains = <&rpmhpd SM8250_MMCX>; 3472 3473 interrupt-parent = <&mdss>; 3474 interrupts = <0>; 3475 3476 ports { 3477 #address-cells = <1>; 3478 #size-cells = <0>; 3479 3480 port@0 { 3481 reg = <0>; 3482 dpu_intf1_out: endpoint { 3483 remote-endpoint = <&dsi0_in>; 3484 }; 3485 }; 3486 3487 port@1 { 3488 reg = <1>; 3489 dpu_intf2_out: endpoint { 3490 remote-endpoint = <&dsi1_in>; 3491 }; 3492 }; 3493 }; 3494 3495 mdp_opp_table: mdp-opp-table { 3496 compatible = "operating-points-v2"; 3497 3498 opp-200000000 { 3499 opp-hz = /bits/ 64 <200000000>; 3500 required-opps = <&rpmhpd_opp_low_svs>; 3501 }; 3502 3503 opp-300000000 { 3504 opp-hz = /bits/ 64 <300000000>; 3505 required-opps = <&rpmhpd_opp_svs>; 3506 }; 3507 3508 opp-345000000 { 3509 opp-hz = /bits/ 64 <345000000>; 3510 required-opps = <&rpmhpd_opp_svs_l1>; 3511 }; 3512 3513 opp-460000000 { 3514 opp-hz = /bits/ 64 <460000000>; 3515 required-opps = <&rpmhpd_opp_nom>; 3516 }; 3517 }; 3518 }; 3519 3520 dsi0: dsi@ae94000 { 3521 compatible = "qcom,mdss-dsi-ctrl"; 3522 reg = <0 0x0ae94000 0 0x400>; 3523 reg-names = "dsi_ctrl"; 3524 3525 interrupt-parent = <&mdss>; 3526 interrupts = <4>; 3527 3528 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3529 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3530 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3531 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3532 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3533 <&gcc GCC_DISP_HF_AXI_CLK>; 3534 clock-names = "byte", 3535 "byte_intf", 3536 "pixel", 3537 "core", 3538 "iface", 3539 "bus"; 3540 3541 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3542 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 3543 3544 operating-points-v2 = <&dsi_opp_table>; 3545 power-domains = <&rpmhpd SM8250_MMCX>; 3546 3547 phys = <&dsi0_phy>; 3548 phy-names = "dsi"; 3549 3550 status = "disabled"; 3551 3552 #address-cells = <1>; 3553 #size-cells = <0>; 3554 3555 ports { 3556 #address-cells = <1>; 3557 #size-cells = <0>; 3558 3559 port@0 { 3560 reg = <0>; 3561 dsi0_in: endpoint { 3562 remote-endpoint = <&dpu_intf1_out>; 3563 }; 3564 }; 3565 3566 port@1 { 3567 reg = <1>; 3568 dsi0_out: endpoint { 3569 }; 3570 }; 3571 }; 3572 }; 3573 3574 dsi0_phy: dsi-phy@ae94400 { 3575 compatible = "qcom,dsi-phy-7nm"; 3576 reg = <0 0x0ae94400 0 0x200>, 3577 <0 0x0ae94600 0 0x280>, 3578 <0 0x0ae94900 0 0x260>; 3579 reg-names = "dsi_phy", 3580 "dsi_phy_lane", 3581 "dsi_pll"; 3582 3583 #clock-cells = <1>; 3584 #phy-cells = <0>; 3585 3586 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3587 <&rpmhcc RPMH_CXO_CLK>; 3588 clock-names = "iface", "ref"; 3589 3590 status = "disabled"; 3591 }; 3592 3593 dsi1: dsi@ae96000 { 3594 compatible = "qcom,mdss-dsi-ctrl"; 3595 reg = <0 0x0ae96000 0 0x400>; 3596 reg-names = "dsi_ctrl"; 3597 3598 interrupt-parent = <&mdss>; 3599 interrupts = <5>; 3600 3601 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3602 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3603 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3604 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3605 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3606 <&gcc GCC_DISP_HF_AXI_CLK>; 3607 clock-names = "byte", 3608 "byte_intf", 3609 "pixel", 3610 "core", 3611 "iface", 3612 "bus"; 3613 3614 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3615 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 3616 3617 operating-points-v2 = <&dsi_opp_table>; 3618 power-domains = <&rpmhpd SM8250_MMCX>; 3619 3620 phys = <&dsi1_phy>; 3621 phy-names = "dsi"; 3622 3623 status = "disabled"; 3624 3625 #address-cells = <1>; 3626 #size-cells = <0>; 3627 3628 ports { 3629 #address-cells = <1>; 3630 #size-cells = <0>; 3631 3632 port@0 { 3633 reg = <0>; 3634 dsi1_in: endpoint { 3635 remote-endpoint = <&dpu_intf2_out>; 3636 }; 3637 }; 3638 3639 port@1 { 3640 reg = <1>; 3641 dsi1_out: endpoint { 3642 }; 3643 }; 3644 }; 3645 }; 3646 3647 dsi1_phy: dsi-phy@ae96400 { 3648 compatible = "qcom,dsi-phy-7nm"; 3649 reg = <0 0x0ae96400 0 0x200>, 3650 <0 0x0ae96600 0 0x280>, 3651 <0 0x0ae96900 0 0x260>; 3652 reg-names = "dsi_phy", 3653 "dsi_phy_lane", 3654 "dsi_pll"; 3655 3656 #clock-cells = <1>; 3657 #phy-cells = <0>; 3658 3659 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3660 <&rpmhcc RPMH_CXO_CLK>; 3661 clock-names = "iface", "ref"; 3662 3663 status = "disabled"; 3664 3665 dsi_opp_table: dsi-opp-table { 3666 compatible = "operating-points-v2"; 3667 3668 opp-187500000 { 3669 opp-hz = /bits/ 64 <187500000>; 3670 required-opps = <&rpmhpd_opp_low_svs>; 3671 }; 3672 3673 opp-300000000 { 3674 opp-hz = /bits/ 64 <300000000>; 3675 required-opps = <&rpmhpd_opp_svs>; 3676 }; 3677 3678 opp-358000000 { 3679 opp-hz = /bits/ 64 <358000000>; 3680 required-opps = <&rpmhpd_opp_svs_l1>; 3681 }; 3682 }; 3683 }; 3684 }; 3685 3686 dispcc: clock-controller@af00000 { 3687 compatible = "qcom,sm8250-dispcc"; 3688 reg = <0 0x0af00000 0 0x10000>; 3689 power-domains = <&rpmhpd SM8250_MMCX>; 3690 required-opps = <&rpmhpd_opp_low_svs>; 3691 clocks = <&rpmhcc RPMH_CXO_CLK>, 3692 <&dsi0_phy 0>, 3693 <&dsi0_phy 1>, 3694 <&dsi1_phy 0>, 3695 <&dsi1_phy 1>, 3696 <&dp_phy 0>, 3697 <&dp_phy 1>; 3698 clock-names = "bi_tcxo", 3699 "dsi0_phy_pll_out_byteclk", 3700 "dsi0_phy_pll_out_dsiclk", 3701 "dsi1_phy_pll_out_byteclk", 3702 "dsi1_phy_pll_out_dsiclk", 3703 "dp_phy_pll_link_clk", 3704 "dp_phy_pll_vco_div_clk"; 3705 #clock-cells = <1>; 3706 #reset-cells = <1>; 3707 #power-domain-cells = <1>; 3708 }; 3709 3710 pdc: interrupt-controller@b220000 { 3711 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 3712 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3713 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3714 <125 63 1>, <126 716 12>; 3715 #interrupt-cells = <2>; 3716 interrupt-parent = <&intc>; 3717 interrupt-controller; 3718 }; 3719 3720 tsens0: thermal-sensor@c263000 { 3721 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3722 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3723 <0 0x0c222000 0 0x1ff>; /* SROT */ 3724 #qcom,sensors = <16>; 3725 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3727 interrupt-names = "uplow", "critical"; 3728 #thermal-sensor-cells = <1>; 3729 }; 3730 3731 tsens1: thermal-sensor@c265000 { 3732 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3733 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3734 <0 0x0c223000 0 0x1ff>; /* SROT */ 3735 #qcom,sensors = <9>; 3736 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3738 interrupt-names = "uplow", "critical"; 3739 #thermal-sensor-cells = <1>; 3740 }; 3741 3742 aoss_qmp: power-controller@c300000 { 3743 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 3744 reg = <0 0x0c300000 0 0x400>; 3745 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3746 IPCC_MPROC_SIGNAL_GLINK_QMP 3747 IRQ_TYPE_EDGE_RISING>; 3748 mboxes = <&ipcc IPCC_CLIENT_AOP 3749 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3750 3751 #clock-cells = <0>; 3752 }; 3753 3754 sram@c3f0000 { 3755 compatible = "qcom,rpmh-stats"; 3756 reg = <0 0x0c3f0000 0 0x400>; 3757 }; 3758 3759 spmi_bus: spmi@c440000 { 3760 compatible = "qcom,spmi-pmic-arb"; 3761 reg = <0x0 0x0c440000 0x0 0x0001100>, 3762 <0x0 0x0c600000 0x0 0x2000000>, 3763 <0x0 0x0e600000 0x0 0x0100000>, 3764 <0x0 0x0e700000 0x0 0x00a0000>, 3765 <0x0 0x0c40a000 0x0 0x0026000>; 3766 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3767 interrupt-names = "periph_irq"; 3768 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3769 qcom,ee = <0>; 3770 qcom,channel = <0>; 3771 #address-cells = <2>; 3772 #size-cells = <0>; 3773 interrupt-controller; 3774 #interrupt-cells = <4>; 3775 }; 3776 3777 tlmm: pinctrl@f100000 { 3778 compatible = "qcom,sm8250-pinctrl"; 3779 reg = <0 0x0f100000 0 0x300000>, 3780 <0 0x0f500000 0 0x300000>, 3781 <0 0x0f900000 0 0x300000>; 3782 reg-names = "west", "south", "north"; 3783 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3784 gpio-controller; 3785 #gpio-cells = <2>; 3786 interrupt-controller; 3787 #interrupt-cells = <2>; 3788 gpio-ranges = <&tlmm 0 0 181>; 3789 wakeup-parent = <&pdc>; 3790 3791 cci0_default: cci0-default { 3792 cci0_i2c0_default: cci0-i2c0-default { 3793 /* SDA, SCL */ 3794 pins = "gpio101", "gpio102"; 3795 function = "cci_i2c"; 3796 3797 bias-pull-up; 3798 drive-strength = <2>; /* 2 mA */ 3799 }; 3800 3801 cci0_i2c1_default: cci0-i2c1-default { 3802 /* SDA, SCL */ 3803 pins = "gpio103", "gpio104"; 3804 function = "cci_i2c"; 3805 3806 bias-pull-up; 3807 drive-strength = <2>; /* 2 mA */ 3808 }; 3809 }; 3810 3811 cci0_sleep: cci0-sleep { 3812 cci0_i2c0_sleep: cci0-i2c0-sleep { 3813 /* SDA, SCL */ 3814 pins = "gpio101", "gpio102"; 3815 function = "cci_i2c"; 3816 3817 drive-strength = <2>; /* 2 mA */ 3818 bias-pull-down; 3819 }; 3820 3821 cci0_i2c1_sleep: cci0-i2c1-sleep { 3822 /* SDA, SCL */ 3823 pins = "gpio103", "gpio104"; 3824 function = "cci_i2c"; 3825 3826 drive-strength = <2>; /* 2 mA */ 3827 bias-pull-down; 3828 }; 3829 }; 3830 3831 cci1_default: cci1-default { 3832 cci1_i2c0_default: cci1-i2c0-default { 3833 /* SDA, SCL */ 3834 pins = "gpio105","gpio106"; 3835 function = "cci_i2c"; 3836 3837 bias-pull-up; 3838 drive-strength = <2>; /* 2 mA */ 3839 }; 3840 3841 cci1_i2c1_default: cci1-i2c1-default { 3842 /* SDA, SCL */ 3843 pins = "gpio107","gpio108"; 3844 function = "cci_i2c"; 3845 3846 bias-pull-up; 3847 drive-strength = <2>; /* 2 mA */ 3848 }; 3849 }; 3850 3851 cci1_sleep: cci1-sleep { 3852 cci1_i2c0_sleep: cci1-i2c0-sleep { 3853 /* SDA, SCL */ 3854 pins = "gpio105","gpio106"; 3855 function = "cci_i2c"; 3856 3857 bias-pull-down; 3858 drive-strength = <2>; /* 2 mA */ 3859 }; 3860 3861 cci1_i2c1_sleep: cci1-i2c1-sleep { 3862 /* SDA, SCL */ 3863 pins = "gpio107","gpio108"; 3864 function = "cci_i2c"; 3865 3866 bias-pull-down; 3867 drive-strength = <2>; /* 2 mA */ 3868 }; 3869 }; 3870 3871 pri_mi2s_active: pri-mi2s-active { 3872 sclk { 3873 pins = "gpio138"; 3874 function = "mi2s0_sck"; 3875 drive-strength = <8>; 3876 bias-disable; 3877 }; 3878 3879 ws { 3880 pins = "gpio141"; 3881 function = "mi2s0_ws"; 3882 drive-strength = <8>; 3883 output-high; 3884 }; 3885 3886 data0 { 3887 pins = "gpio139"; 3888 function = "mi2s0_data0"; 3889 drive-strength = <8>; 3890 bias-disable; 3891 output-high; 3892 }; 3893 3894 data1 { 3895 pins = "gpio140"; 3896 function = "mi2s0_data1"; 3897 drive-strength = <8>; 3898 output-high; 3899 }; 3900 }; 3901 3902 qup_i2c0_default: qup-i2c0-default { 3903 mux { 3904 pins = "gpio28", "gpio29"; 3905 function = "qup0"; 3906 }; 3907 3908 config { 3909 pins = "gpio28", "gpio29"; 3910 drive-strength = <2>; 3911 bias-disable; 3912 }; 3913 }; 3914 3915 qup_i2c1_default: qup-i2c1-default { 3916 pinmux { 3917 pins = "gpio4", "gpio5"; 3918 function = "qup1"; 3919 }; 3920 3921 config { 3922 pins = "gpio4", "gpio5"; 3923 drive-strength = <2>; 3924 bias-disable; 3925 }; 3926 }; 3927 3928 qup_i2c2_default: qup-i2c2-default { 3929 mux { 3930 pins = "gpio115", "gpio116"; 3931 function = "qup2"; 3932 }; 3933 3934 config { 3935 pins = "gpio115", "gpio116"; 3936 drive-strength = <2>; 3937 bias-disable; 3938 }; 3939 }; 3940 3941 qup_i2c3_default: qup-i2c3-default { 3942 mux { 3943 pins = "gpio119", "gpio120"; 3944 function = "qup3"; 3945 }; 3946 3947 config { 3948 pins = "gpio119", "gpio120"; 3949 drive-strength = <2>; 3950 bias-disable; 3951 }; 3952 }; 3953 3954 qup_i2c4_default: qup-i2c4-default { 3955 mux { 3956 pins = "gpio8", "gpio9"; 3957 function = "qup4"; 3958 }; 3959 3960 config { 3961 pins = "gpio8", "gpio9"; 3962 drive-strength = <2>; 3963 bias-disable; 3964 }; 3965 }; 3966 3967 qup_i2c5_default: qup-i2c5-default { 3968 mux { 3969 pins = "gpio12", "gpio13"; 3970 function = "qup5"; 3971 }; 3972 3973 config { 3974 pins = "gpio12", "gpio13"; 3975 drive-strength = <2>; 3976 bias-disable; 3977 }; 3978 }; 3979 3980 qup_i2c6_default: qup-i2c6-default { 3981 mux { 3982 pins = "gpio16", "gpio17"; 3983 function = "qup6"; 3984 }; 3985 3986 config { 3987 pins = "gpio16", "gpio17"; 3988 drive-strength = <2>; 3989 bias-disable; 3990 }; 3991 }; 3992 3993 qup_i2c7_default: qup-i2c7-default { 3994 mux { 3995 pins = "gpio20", "gpio21"; 3996 function = "qup7"; 3997 }; 3998 3999 config { 4000 pins = "gpio20", "gpio21"; 4001 drive-strength = <2>; 4002 bias-disable; 4003 }; 4004 }; 4005 4006 qup_i2c8_default: qup-i2c8-default { 4007 mux { 4008 pins = "gpio24", "gpio25"; 4009 function = "qup8"; 4010 }; 4011 4012 config { 4013 pins = "gpio24", "gpio25"; 4014 drive-strength = <2>; 4015 bias-disable; 4016 }; 4017 }; 4018 4019 qup_i2c9_default: qup-i2c9-default { 4020 mux { 4021 pins = "gpio125", "gpio126"; 4022 function = "qup9"; 4023 }; 4024 4025 config { 4026 pins = "gpio125", "gpio126"; 4027 drive-strength = <2>; 4028 bias-disable; 4029 }; 4030 }; 4031 4032 qup_i2c10_default: qup-i2c10-default { 4033 mux { 4034 pins = "gpio129", "gpio130"; 4035 function = "qup10"; 4036 }; 4037 4038 config { 4039 pins = "gpio129", "gpio130"; 4040 drive-strength = <2>; 4041 bias-disable; 4042 }; 4043 }; 4044 4045 qup_i2c11_default: qup-i2c11-default { 4046 mux { 4047 pins = "gpio60", "gpio61"; 4048 function = "qup11"; 4049 }; 4050 4051 config { 4052 pins = "gpio60", "gpio61"; 4053 drive-strength = <2>; 4054 bias-disable; 4055 }; 4056 }; 4057 4058 qup_i2c12_default: qup-i2c12-default { 4059 mux { 4060 pins = "gpio32", "gpio33"; 4061 function = "qup12"; 4062 }; 4063 4064 config { 4065 pins = "gpio32", "gpio33"; 4066 drive-strength = <2>; 4067 bias-disable; 4068 }; 4069 }; 4070 4071 qup_i2c13_default: qup-i2c13-default { 4072 mux { 4073 pins = "gpio36", "gpio37"; 4074 function = "qup13"; 4075 }; 4076 4077 config { 4078 pins = "gpio36", "gpio37"; 4079 drive-strength = <2>; 4080 bias-disable; 4081 }; 4082 }; 4083 4084 qup_i2c14_default: qup-i2c14-default { 4085 mux { 4086 pins = "gpio40", "gpio41"; 4087 function = "qup14"; 4088 }; 4089 4090 config { 4091 pins = "gpio40", "gpio41"; 4092 drive-strength = <2>; 4093 bias-disable; 4094 }; 4095 }; 4096 4097 qup_i2c15_default: qup-i2c15-default { 4098 mux { 4099 pins = "gpio44", "gpio45"; 4100 function = "qup15"; 4101 }; 4102 4103 config { 4104 pins = "gpio44", "gpio45"; 4105 drive-strength = <2>; 4106 bias-disable; 4107 }; 4108 }; 4109 4110 qup_i2c16_default: qup-i2c16-default { 4111 mux { 4112 pins = "gpio48", "gpio49"; 4113 function = "qup16"; 4114 }; 4115 4116 config { 4117 pins = "gpio48", "gpio49"; 4118 drive-strength = <2>; 4119 bias-disable; 4120 }; 4121 }; 4122 4123 qup_i2c17_default: qup-i2c17-default { 4124 mux { 4125 pins = "gpio52", "gpio53"; 4126 function = "qup17"; 4127 }; 4128 4129 config { 4130 pins = "gpio52", "gpio53"; 4131 drive-strength = <2>; 4132 bias-disable; 4133 }; 4134 }; 4135 4136 qup_i2c18_default: qup-i2c18-default { 4137 mux { 4138 pins = "gpio56", "gpio57"; 4139 function = "qup18"; 4140 }; 4141 4142 config { 4143 pins = "gpio56", "gpio57"; 4144 drive-strength = <2>; 4145 bias-disable; 4146 }; 4147 }; 4148 4149 qup_i2c19_default: qup-i2c19-default { 4150 mux { 4151 pins = "gpio0", "gpio1"; 4152 function = "qup19"; 4153 }; 4154 4155 config { 4156 pins = "gpio0", "gpio1"; 4157 drive-strength = <2>; 4158 bias-disable; 4159 }; 4160 }; 4161 4162 qup_spi0_cs: qup-spi0-cs { 4163 pins = "gpio31"; 4164 function = "qup0"; 4165 }; 4166 4167 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 4168 pins = "gpio31"; 4169 function = "gpio"; 4170 }; 4171 4172 qup_spi0_data_clk: qup-spi0-data-clk { 4173 pins = "gpio28", "gpio29", 4174 "gpio30"; 4175 function = "qup0"; 4176 }; 4177 4178 qup_spi1_cs: qup-spi1-cs { 4179 pins = "gpio7"; 4180 function = "qup1"; 4181 }; 4182 4183 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 4184 pins = "gpio7"; 4185 function = "gpio"; 4186 }; 4187 4188 qup_spi1_data_clk: qup-spi1-data-clk { 4189 pins = "gpio4", "gpio5", 4190 "gpio6"; 4191 function = "qup1"; 4192 }; 4193 4194 qup_spi2_cs: qup-spi2-cs { 4195 pins = "gpio118"; 4196 function = "qup2"; 4197 }; 4198 4199 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 4200 pins = "gpio118"; 4201 function = "gpio"; 4202 }; 4203 4204 qup_spi2_data_clk: qup-spi2-data-clk { 4205 pins = "gpio115", "gpio116", 4206 "gpio117"; 4207 function = "qup2"; 4208 }; 4209 4210 qup_spi3_cs: qup-spi3-cs { 4211 pins = "gpio122"; 4212 function = "qup3"; 4213 }; 4214 4215 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 4216 pins = "gpio122"; 4217 function = "gpio"; 4218 }; 4219 4220 qup_spi3_data_clk: qup-spi3-data-clk { 4221 pins = "gpio119", "gpio120", 4222 "gpio121"; 4223 function = "qup3"; 4224 }; 4225 4226 qup_spi4_cs: qup-spi4-cs { 4227 pins = "gpio11"; 4228 function = "qup4"; 4229 }; 4230 4231 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 4232 pins = "gpio11"; 4233 function = "gpio"; 4234 }; 4235 4236 qup_spi4_data_clk: qup-spi4-data-clk { 4237 pins = "gpio8", "gpio9", 4238 "gpio10"; 4239 function = "qup4"; 4240 }; 4241 4242 qup_spi5_cs: qup-spi5-cs { 4243 pins = "gpio15"; 4244 function = "qup5"; 4245 }; 4246 4247 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 4248 pins = "gpio15"; 4249 function = "gpio"; 4250 }; 4251 4252 qup_spi5_data_clk: qup-spi5-data-clk { 4253 pins = "gpio12", "gpio13", 4254 "gpio14"; 4255 function = "qup5"; 4256 }; 4257 4258 qup_spi6_cs: qup-spi6-cs { 4259 pins = "gpio19"; 4260 function = "qup6"; 4261 }; 4262 4263 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 4264 pins = "gpio19"; 4265 function = "gpio"; 4266 }; 4267 4268 qup_spi6_data_clk: qup-spi6-data-clk { 4269 pins = "gpio16", "gpio17", 4270 "gpio18"; 4271 function = "qup6"; 4272 }; 4273 4274 qup_spi7_cs: qup-spi7-cs { 4275 pins = "gpio23"; 4276 function = "qup7"; 4277 }; 4278 4279 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 4280 pins = "gpio23"; 4281 function = "gpio"; 4282 }; 4283 4284 qup_spi7_data_clk: qup-spi7-data-clk { 4285 pins = "gpio20", "gpio21", 4286 "gpio22"; 4287 function = "qup7"; 4288 }; 4289 4290 qup_spi8_cs: qup-spi8-cs { 4291 pins = "gpio27"; 4292 function = "qup8"; 4293 }; 4294 4295 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 4296 pins = "gpio27"; 4297 function = "gpio"; 4298 }; 4299 4300 qup_spi8_data_clk: qup-spi8-data-clk { 4301 pins = "gpio24", "gpio25", 4302 "gpio26"; 4303 function = "qup8"; 4304 }; 4305 4306 qup_spi9_cs: qup-spi9-cs { 4307 pins = "gpio128"; 4308 function = "qup9"; 4309 }; 4310 4311 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 4312 pins = "gpio128"; 4313 function = "gpio"; 4314 }; 4315 4316 qup_spi9_data_clk: qup-spi9-data-clk { 4317 pins = "gpio125", "gpio126", 4318 "gpio127"; 4319 function = "qup9"; 4320 }; 4321 4322 qup_spi10_cs: qup-spi10-cs { 4323 pins = "gpio132"; 4324 function = "qup10"; 4325 }; 4326 4327 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 4328 pins = "gpio132"; 4329 function = "gpio"; 4330 }; 4331 4332 qup_spi10_data_clk: qup-spi10-data-clk { 4333 pins = "gpio129", "gpio130", 4334 "gpio131"; 4335 function = "qup10"; 4336 }; 4337 4338 qup_spi11_cs: qup-spi11-cs { 4339 pins = "gpio63"; 4340 function = "qup11"; 4341 }; 4342 4343 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 4344 pins = "gpio63"; 4345 function = "gpio"; 4346 }; 4347 4348 qup_spi11_data_clk: qup-spi11-data-clk { 4349 pins = "gpio60", "gpio61", 4350 "gpio62"; 4351 function = "qup11"; 4352 }; 4353 4354 qup_spi12_cs: qup-spi12-cs { 4355 pins = "gpio35"; 4356 function = "qup12"; 4357 }; 4358 4359 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4360 pins = "gpio35"; 4361 function = "gpio"; 4362 }; 4363 4364 qup_spi12_data_clk: qup-spi12-data-clk { 4365 pins = "gpio32", "gpio33", 4366 "gpio34"; 4367 function = "qup12"; 4368 }; 4369 4370 qup_spi13_cs: qup-spi13-cs { 4371 pins = "gpio39"; 4372 function = "qup13"; 4373 }; 4374 4375 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4376 pins = "gpio39"; 4377 function = "gpio"; 4378 }; 4379 4380 qup_spi13_data_clk: qup-spi13-data-clk { 4381 pins = "gpio36", "gpio37", 4382 "gpio38"; 4383 function = "qup13"; 4384 }; 4385 4386 qup_spi14_cs: qup-spi14-cs { 4387 pins = "gpio43"; 4388 function = "qup14"; 4389 }; 4390 4391 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4392 pins = "gpio43"; 4393 function = "gpio"; 4394 }; 4395 4396 qup_spi14_data_clk: qup-spi14-data-clk { 4397 pins = "gpio40", "gpio41", 4398 "gpio42"; 4399 function = "qup14"; 4400 }; 4401 4402 qup_spi15_cs: qup-spi15-cs { 4403 pins = "gpio47"; 4404 function = "qup15"; 4405 }; 4406 4407 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4408 pins = "gpio47"; 4409 function = "gpio"; 4410 }; 4411 4412 qup_spi15_data_clk: qup-spi15-data-clk { 4413 pins = "gpio44", "gpio45", 4414 "gpio46"; 4415 function = "qup15"; 4416 }; 4417 4418 qup_spi16_cs: qup-spi16-cs { 4419 pins = "gpio51"; 4420 function = "qup16"; 4421 }; 4422 4423 qup_spi16_cs_gpio: qup-spi16-cs-gpio { 4424 pins = "gpio51"; 4425 function = "gpio"; 4426 }; 4427 4428 qup_spi16_data_clk: qup-spi16-data-clk { 4429 pins = "gpio48", "gpio49", 4430 "gpio50"; 4431 function = "qup16"; 4432 }; 4433 4434 qup_spi17_cs: qup-spi17-cs { 4435 pins = "gpio55"; 4436 function = "qup17"; 4437 }; 4438 4439 qup_spi17_cs_gpio: qup-spi17-cs-gpio { 4440 pins = "gpio55"; 4441 function = "gpio"; 4442 }; 4443 4444 qup_spi17_data_clk: qup-spi17-data-clk { 4445 pins = "gpio52", "gpio53", 4446 "gpio54"; 4447 function = "qup17"; 4448 }; 4449 4450 qup_spi18_cs: qup-spi18-cs { 4451 pins = "gpio59"; 4452 function = "qup18"; 4453 }; 4454 4455 qup_spi18_cs_gpio: qup-spi18-cs-gpio { 4456 pins = "gpio59"; 4457 function = "gpio"; 4458 }; 4459 4460 qup_spi18_data_clk: qup-spi18-data-clk { 4461 pins = "gpio56", "gpio57", 4462 "gpio58"; 4463 function = "qup18"; 4464 }; 4465 4466 qup_spi19_cs: qup-spi19-cs { 4467 pins = "gpio3"; 4468 function = "qup19"; 4469 }; 4470 4471 qup_spi19_cs_gpio: qup-spi19-cs-gpio { 4472 pins = "gpio3"; 4473 function = "gpio"; 4474 }; 4475 4476 qup_spi19_data_clk: qup-spi19-data-clk { 4477 pins = "gpio0", "gpio1", 4478 "gpio2"; 4479 function = "qup19"; 4480 }; 4481 4482 qup_uart2_default: qup-uart2-default { 4483 mux { 4484 pins = "gpio117", "gpio118"; 4485 function = "qup2"; 4486 }; 4487 }; 4488 4489 qup_uart6_default: qup-uart6-default { 4490 mux { 4491 pins = "gpio16", "gpio17", 4492 "gpio18", "gpio19"; 4493 function = "qup6"; 4494 }; 4495 }; 4496 4497 qup_uart12_default: qup-uart12-default { 4498 mux { 4499 pins = "gpio34", "gpio35"; 4500 function = "qup12"; 4501 }; 4502 }; 4503 4504 qup_uart17_default: qup-uart17-default { 4505 mux { 4506 pins = "gpio52", "gpio53", 4507 "gpio54", "gpio55"; 4508 function = "qup17"; 4509 }; 4510 }; 4511 4512 qup_uart18_default: qup-uart18-default { 4513 mux { 4514 pins = "gpio58", "gpio59"; 4515 function = "qup18"; 4516 }; 4517 }; 4518 4519 tert_mi2s_active: tert-mi2s-active { 4520 sck { 4521 pins = "gpio133"; 4522 function = "mi2s2_sck"; 4523 drive-strength = <8>; 4524 bias-disable; 4525 }; 4526 4527 data0 { 4528 pins = "gpio134"; 4529 function = "mi2s2_data0"; 4530 drive-strength = <8>; 4531 bias-disable; 4532 output-high; 4533 }; 4534 4535 ws { 4536 pins = "gpio135"; 4537 function = "mi2s2_ws"; 4538 drive-strength = <8>; 4539 output-high; 4540 }; 4541 }; 4542 4543 sdc2_sleep_state: sdc2-sleep { 4544 clk { 4545 pins = "sdc2_clk"; 4546 drive-strength = <2>; 4547 bias-disable; 4548 }; 4549 4550 cmd { 4551 pins = "sdc2_cmd"; 4552 drive-strength = <2>; 4553 bias-pull-up; 4554 }; 4555 4556 data { 4557 pins = "sdc2_data"; 4558 drive-strength = <2>; 4559 bias-pull-up; 4560 }; 4561 }; 4562 4563 pcie0_default_state: pcie0-default { 4564 perst { 4565 pins = "gpio79"; 4566 function = "gpio"; 4567 drive-strength = <2>; 4568 bias-pull-down; 4569 }; 4570 4571 clkreq { 4572 pins = "gpio80"; 4573 function = "pci_e0"; 4574 drive-strength = <2>; 4575 bias-pull-up; 4576 }; 4577 4578 wake { 4579 pins = "gpio81"; 4580 function = "gpio"; 4581 drive-strength = <2>; 4582 bias-pull-up; 4583 }; 4584 }; 4585 4586 pcie1_default_state: pcie1-default { 4587 perst { 4588 pins = "gpio82"; 4589 function = "gpio"; 4590 drive-strength = <2>; 4591 bias-pull-down; 4592 }; 4593 4594 clkreq { 4595 pins = "gpio83"; 4596 function = "pci_e1"; 4597 drive-strength = <2>; 4598 bias-pull-up; 4599 }; 4600 4601 wake { 4602 pins = "gpio84"; 4603 function = "gpio"; 4604 drive-strength = <2>; 4605 bias-pull-up; 4606 }; 4607 }; 4608 4609 pcie2_default_state: pcie2-default { 4610 perst { 4611 pins = "gpio85"; 4612 function = "gpio"; 4613 drive-strength = <2>; 4614 bias-pull-down; 4615 }; 4616 4617 clkreq { 4618 pins = "gpio86"; 4619 function = "pci_e2"; 4620 drive-strength = <2>; 4621 bias-pull-up; 4622 }; 4623 4624 wake { 4625 pins = "gpio87"; 4626 function = "gpio"; 4627 drive-strength = <2>; 4628 bias-pull-up; 4629 }; 4630 }; 4631 }; 4632 4633 apps_smmu: iommu@15000000 { 4634 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 4635 reg = <0 0x15000000 0 0x100000>; 4636 #iommu-cells = <2>; 4637 #global-interrupts = <2>; 4638 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4639 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4640 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4641 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4642 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4643 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4644 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4645 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4646 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4647 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4648 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4649 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4650 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4651 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4652 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4653 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4654 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4655 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4656 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4657 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4658 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4659 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4660 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4661 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4662 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4663 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4664 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4665 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4666 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4667 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4668 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4669 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4670 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4671 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4672 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4673 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4674 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4675 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4676 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4677 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4678 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4679 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4680 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4681 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4682 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4683 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4684 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4685 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4686 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4687 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4688 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4689 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4690 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4691 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4692 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4693 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4694 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4695 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4696 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4697 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4698 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4699 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4700 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4701 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4702 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4703 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4704 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4705 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4706 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4707 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4708 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4709 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4710 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4711 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4712 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4713 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4714 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4715 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4716 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4717 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4718 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4719 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4720 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4721 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4722 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4723 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4724 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4725 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4726 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4727 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4728 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4729 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4730 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4731 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4732 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4733 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4734 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 4735 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 4736 }; 4737 4738 adsp: remoteproc@17300000 { 4739 compatible = "qcom,sm8250-adsp-pas"; 4740 reg = <0 0x17300000 0 0x100>; 4741 4742 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 4743 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4744 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4745 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4746 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4747 interrupt-names = "wdog", "fatal", "ready", 4748 "handover", "stop-ack"; 4749 4750 clocks = <&rpmhcc RPMH_CXO_CLK>; 4751 clock-names = "xo"; 4752 4753 power-domains = <&rpmhpd SM8250_LCX>, 4754 <&rpmhpd SM8250_LMX>; 4755 power-domain-names = "lcx", "lmx"; 4756 4757 memory-region = <&adsp_mem>; 4758 4759 qcom,qmp = <&aoss_qmp>; 4760 4761 qcom,smem-states = <&smp2p_adsp_out 0>; 4762 qcom,smem-state-names = "stop"; 4763 4764 status = "disabled"; 4765 4766 glink-edge { 4767 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4768 IPCC_MPROC_SIGNAL_GLINK_QMP 4769 IRQ_TYPE_EDGE_RISING>; 4770 mboxes = <&ipcc IPCC_CLIENT_LPASS 4771 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4772 4773 label = "lpass"; 4774 qcom,remote-pid = <2>; 4775 4776 apr { 4777 compatible = "qcom,apr-v2"; 4778 qcom,glink-channels = "apr_audio_svc"; 4779 qcom,domain = <APR_DOMAIN_ADSP>; 4780 #address-cells = <1>; 4781 #size-cells = <0>; 4782 4783 apr-service@3 { 4784 reg = <APR_SVC_ADSP_CORE>; 4785 compatible = "qcom,q6core"; 4786 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4787 }; 4788 4789 q6afe: apr-service@4 { 4790 compatible = "qcom,q6afe"; 4791 reg = <APR_SVC_AFE>; 4792 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4793 q6afedai: dais { 4794 compatible = "qcom,q6afe-dais"; 4795 #address-cells = <1>; 4796 #size-cells = <0>; 4797 #sound-dai-cells = <1>; 4798 }; 4799 4800 q6afecc: cc { 4801 compatible = "qcom,q6afe-clocks"; 4802 #clock-cells = <2>; 4803 }; 4804 }; 4805 4806 q6asm: apr-service@7 { 4807 compatible = "qcom,q6asm"; 4808 reg = <APR_SVC_ASM>; 4809 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4810 q6asmdai: dais { 4811 compatible = "qcom,q6asm-dais"; 4812 #address-cells = <1>; 4813 #size-cells = <0>; 4814 #sound-dai-cells = <1>; 4815 iommus = <&apps_smmu 0x1801 0x0>; 4816 }; 4817 }; 4818 4819 q6adm: apr-service@8 { 4820 compatible = "qcom,q6adm"; 4821 reg = <APR_SVC_ADM>; 4822 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4823 q6routing: routing { 4824 compatible = "qcom,q6adm-routing"; 4825 #sound-dai-cells = <0>; 4826 }; 4827 }; 4828 }; 4829 4830 fastrpc { 4831 compatible = "qcom,fastrpc"; 4832 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4833 label = "adsp"; 4834 qcom,non-secure-domain; 4835 #address-cells = <1>; 4836 #size-cells = <0>; 4837 4838 compute-cb@3 { 4839 compatible = "qcom,fastrpc-compute-cb"; 4840 reg = <3>; 4841 iommus = <&apps_smmu 0x1803 0x0>; 4842 }; 4843 4844 compute-cb@4 { 4845 compatible = "qcom,fastrpc-compute-cb"; 4846 reg = <4>; 4847 iommus = <&apps_smmu 0x1804 0x0>; 4848 }; 4849 4850 compute-cb@5 { 4851 compatible = "qcom,fastrpc-compute-cb"; 4852 reg = <5>; 4853 iommus = <&apps_smmu 0x1805 0x0>; 4854 }; 4855 }; 4856 }; 4857 }; 4858 4859 intc: interrupt-controller@17a00000 { 4860 compatible = "arm,gic-v3"; 4861 #interrupt-cells = <3>; 4862 interrupt-controller; 4863 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4864 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4865 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4866 }; 4867 4868 watchdog@17c10000 { 4869 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 4870 reg = <0 0x17c10000 0 0x1000>; 4871 clocks = <&sleep_clk>; 4872 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4873 }; 4874 4875 timer@17c20000 { 4876 #address-cells = <1>; 4877 #size-cells = <1>; 4878 ranges = <0 0 0 0x20000000>; 4879 compatible = "arm,armv7-timer-mem"; 4880 reg = <0x0 0x17c20000 0x0 0x1000>; 4881 clock-frequency = <19200000>; 4882 4883 frame@17c21000 { 4884 frame-number = <0>; 4885 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4886 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4887 reg = <0x17c21000 0x1000>, 4888 <0x17c22000 0x1000>; 4889 }; 4890 4891 frame@17c23000 { 4892 frame-number = <1>; 4893 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4894 reg = <0x17c23000 0x1000>; 4895 status = "disabled"; 4896 }; 4897 4898 frame@17c25000 { 4899 frame-number = <2>; 4900 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4901 reg = <0x17c25000 0x1000>; 4902 status = "disabled"; 4903 }; 4904 4905 frame@17c27000 { 4906 frame-number = <3>; 4907 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4908 reg = <0x17c27000 0x1000>; 4909 status = "disabled"; 4910 }; 4911 4912 frame@17c29000 { 4913 frame-number = <4>; 4914 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4915 reg = <0x17c29000 0x1000>; 4916 status = "disabled"; 4917 }; 4918 4919 frame@17c2b000 { 4920 frame-number = <5>; 4921 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4922 reg = <0x17c2b000 0x1000>; 4923 status = "disabled"; 4924 }; 4925 4926 frame@17c2d000 { 4927 frame-number = <6>; 4928 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4929 reg = <0x17c2d000 0x1000>; 4930 status = "disabled"; 4931 }; 4932 }; 4933 4934 apps_rsc: rsc@18200000 { 4935 label = "apps_rsc"; 4936 compatible = "qcom,rpmh-rsc"; 4937 reg = <0x0 0x18200000 0x0 0x10000>, 4938 <0x0 0x18210000 0x0 0x10000>, 4939 <0x0 0x18220000 0x0 0x10000>; 4940 reg-names = "drv-0", "drv-1", "drv-2"; 4941 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4942 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4943 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4944 qcom,tcs-offset = <0xd00>; 4945 qcom,drv-id = <2>; 4946 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4947 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4948 4949 rpmhcc: clock-controller { 4950 compatible = "qcom,sm8250-rpmh-clk"; 4951 #clock-cells = <1>; 4952 clock-names = "xo"; 4953 clocks = <&xo_board>; 4954 }; 4955 4956 rpmhpd: power-controller { 4957 compatible = "qcom,sm8250-rpmhpd"; 4958 #power-domain-cells = <1>; 4959 operating-points-v2 = <&rpmhpd_opp_table>; 4960 4961 rpmhpd_opp_table: opp-table { 4962 compatible = "operating-points-v2"; 4963 4964 rpmhpd_opp_ret: opp1 { 4965 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4966 }; 4967 4968 rpmhpd_opp_min_svs: opp2 { 4969 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4970 }; 4971 4972 rpmhpd_opp_low_svs: opp3 { 4973 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4974 }; 4975 4976 rpmhpd_opp_svs: opp4 { 4977 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4978 }; 4979 4980 rpmhpd_opp_svs_l1: opp5 { 4981 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4982 }; 4983 4984 rpmhpd_opp_nom: opp6 { 4985 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4986 }; 4987 4988 rpmhpd_opp_nom_l1: opp7 { 4989 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4990 }; 4991 4992 rpmhpd_opp_nom_l2: opp8 { 4993 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4994 }; 4995 4996 rpmhpd_opp_turbo: opp9 { 4997 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4998 }; 4999 5000 rpmhpd_opp_turbo_l1: opp10 { 5001 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5002 }; 5003 }; 5004 }; 5005 5006 apps_bcm_voter: bcm-voter { 5007 compatible = "qcom,bcm-voter"; 5008 }; 5009 }; 5010 5011 epss_l3: interconnect@18590000 { 5012 compatible = "qcom,sm8250-epss-l3"; 5013 reg = <0 0x18590000 0 0x1000>; 5014 5015 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5016 clock-names = "xo", "alternate"; 5017 5018 #interconnect-cells = <1>; 5019 }; 5020 5021 cpufreq_hw: cpufreq@18591000 { 5022 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 5023 reg = <0 0x18591000 0 0x1000>, 5024 <0 0x18592000 0 0x1000>, 5025 <0 0x18593000 0 0x1000>; 5026 reg-names = "freq-domain0", "freq-domain1", 5027 "freq-domain2"; 5028 5029 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5030 clock-names = "xo", "alternate"; 5031 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5034 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5035 #freq-domain-cells = <1>; 5036 }; 5037 }; 5038 5039 timer { 5040 compatible = "arm,armv8-timer"; 5041 interrupts = <GIC_PPI 13 5042 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5043 <GIC_PPI 14 5044 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5045 <GIC_PPI 11 5046 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5047 <GIC_PPI 10 5048 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5049 }; 5050 5051 thermal-zones { 5052 cpu0-thermal { 5053 polling-delay-passive = <250>; 5054 polling-delay = <1000>; 5055 5056 thermal-sensors = <&tsens0 1>; 5057 5058 trips { 5059 cpu0_alert0: trip-point0 { 5060 temperature = <90000>; 5061 hysteresis = <2000>; 5062 type = "passive"; 5063 }; 5064 5065 cpu0_alert1: trip-point1 { 5066 temperature = <95000>; 5067 hysteresis = <2000>; 5068 type = "passive"; 5069 }; 5070 5071 cpu0_crit: cpu_crit { 5072 temperature = <110000>; 5073 hysteresis = <1000>; 5074 type = "critical"; 5075 }; 5076 }; 5077 5078 cooling-maps { 5079 map0 { 5080 trip = <&cpu0_alert0>; 5081 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5082 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5083 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5084 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5085 }; 5086 map1 { 5087 trip = <&cpu0_alert1>; 5088 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5089 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5090 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5091 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5092 }; 5093 }; 5094 }; 5095 5096 cpu1-thermal { 5097 polling-delay-passive = <250>; 5098 polling-delay = <1000>; 5099 5100 thermal-sensors = <&tsens0 2>; 5101 5102 trips { 5103 cpu1_alert0: trip-point0 { 5104 temperature = <90000>; 5105 hysteresis = <2000>; 5106 type = "passive"; 5107 }; 5108 5109 cpu1_alert1: trip-point1 { 5110 temperature = <95000>; 5111 hysteresis = <2000>; 5112 type = "passive"; 5113 }; 5114 5115 cpu1_crit: cpu_crit { 5116 temperature = <110000>; 5117 hysteresis = <1000>; 5118 type = "critical"; 5119 }; 5120 }; 5121 5122 cooling-maps { 5123 map0 { 5124 trip = <&cpu1_alert0>; 5125 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5126 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5127 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5128 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5129 }; 5130 map1 { 5131 trip = <&cpu1_alert1>; 5132 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5133 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5134 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5135 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5136 }; 5137 }; 5138 }; 5139 5140 cpu2-thermal { 5141 polling-delay-passive = <250>; 5142 polling-delay = <1000>; 5143 5144 thermal-sensors = <&tsens0 3>; 5145 5146 trips { 5147 cpu2_alert0: trip-point0 { 5148 temperature = <90000>; 5149 hysteresis = <2000>; 5150 type = "passive"; 5151 }; 5152 5153 cpu2_alert1: trip-point1 { 5154 temperature = <95000>; 5155 hysteresis = <2000>; 5156 type = "passive"; 5157 }; 5158 5159 cpu2_crit: cpu_crit { 5160 temperature = <110000>; 5161 hysteresis = <1000>; 5162 type = "critical"; 5163 }; 5164 }; 5165 5166 cooling-maps { 5167 map0 { 5168 trip = <&cpu2_alert0>; 5169 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5170 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5171 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5172 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5173 }; 5174 map1 { 5175 trip = <&cpu2_alert1>; 5176 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5177 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5178 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5179 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5180 }; 5181 }; 5182 }; 5183 5184 cpu3-thermal { 5185 polling-delay-passive = <250>; 5186 polling-delay = <1000>; 5187 5188 thermal-sensors = <&tsens0 4>; 5189 5190 trips { 5191 cpu3_alert0: trip-point0 { 5192 temperature = <90000>; 5193 hysteresis = <2000>; 5194 type = "passive"; 5195 }; 5196 5197 cpu3_alert1: trip-point1 { 5198 temperature = <95000>; 5199 hysteresis = <2000>; 5200 type = "passive"; 5201 }; 5202 5203 cpu3_crit: cpu_crit { 5204 temperature = <110000>; 5205 hysteresis = <1000>; 5206 type = "critical"; 5207 }; 5208 }; 5209 5210 cooling-maps { 5211 map0 { 5212 trip = <&cpu3_alert0>; 5213 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5214 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5215 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5216 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5217 }; 5218 map1 { 5219 trip = <&cpu3_alert1>; 5220 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5221 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5222 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5223 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5224 }; 5225 }; 5226 }; 5227 5228 cpu4-top-thermal { 5229 polling-delay-passive = <250>; 5230 polling-delay = <1000>; 5231 5232 thermal-sensors = <&tsens0 7>; 5233 5234 trips { 5235 cpu4_top_alert0: trip-point0 { 5236 temperature = <90000>; 5237 hysteresis = <2000>; 5238 type = "passive"; 5239 }; 5240 5241 cpu4_top_alert1: trip-point1 { 5242 temperature = <95000>; 5243 hysteresis = <2000>; 5244 type = "passive"; 5245 }; 5246 5247 cpu4_top_crit: cpu_crit { 5248 temperature = <110000>; 5249 hysteresis = <1000>; 5250 type = "critical"; 5251 }; 5252 }; 5253 5254 cooling-maps { 5255 map0 { 5256 trip = <&cpu4_top_alert0>; 5257 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5258 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5259 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5260 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5261 }; 5262 map1 { 5263 trip = <&cpu4_top_alert1>; 5264 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5265 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5266 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5267 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5268 }; 5269 }; 5270 }; 5271 5272 cpu5-top-thermal { 5273 polling-delay-passive = <250>; 5274 polling-delay = <1000>; 5275 5276 thermal-sensors = <&tsens0 8>; 5277 5278 trips { 5279 cpu5_top_alert0: trip-point0 { 5280 temperature = <90000>; 5281 hysteresis = <2000>; 5282 type = "passive"; 5283 }; 5284 5285 cpu5_top_alert1: trip-point1 { 5286 temperature = <95000>; 5287 hysteresis = <2000>; 5288 type = "passive"; 5289 }; 5290 5291 cpu5_top_crit: cpu_crit { 5292 temperature = <110000>; 5293 hysteresis = <1000>; 5294 type = "critical"; 5295 }; 5296 }; 5297 5298 cooling-maps { 5299 map0 { 5300 trip = <&cpu5_top_alert0>; 5301 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5302 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5303 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5304 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5305 }; 5306 map1 { 5307 trip = <&cpu5_top_alert1>; 5308 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5309 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5310 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5311 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5312 }; 5313 }; 5314 }; 5315 5316 cpu6-top-thermal { 5317 polling-delay-passive = <250>; 5318 polling-delay = <1000>; 5319 5320 thermal-sensors = <&tsens0 9>; 5321 5322 trips { 5323 cpu6_top_alert0: trip-point0 { 5324 temperature = <90000>; 5325 hysteresis = <2000>; 5326 type = "passive"; 5327 }; 5328 5329 cpu6_top_alert1: trip-point1 { 5330 temperature = <95000>; 5331 hysteresis = <2000>; 5332 type = "passive"; 5333 }; 5334 5335 cpu6_top_crit: cpu_crit { 5336 temperature = <110000>; 5337 hysteresis = <1000>; 5338 type = "critical"; 5339 }; 5340 }; 5341 5342 cooling-maps { 5343 map0 { 5344 trip = <&cpu6_top_alert0>; 5345 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5346 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5347 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5348 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5349 }; 5350 map1 { 5351 trip = <&cpu6_top_alert1>; 5352 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5353 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5354 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5355 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5356 }; 5357 }; 5358 }; 5359 5360 cpu7-top-thermal { 5361 polling-delay-passive = <250>; 5362 polling-delay = <1000>; 5363 5364 thermal-sensors = <&tsens0 10>; 5365 5366 trips { 5367 cpu7_top_alert0: trip-point0 { 5368 temperature = <90000>; 5369 hysteresis = <2000>; 5370 type = "passive"; 5371 }; 5372 5373 cpu7_top_alert1: trip-point1 { 5374 temperature = <95000>; 5375 hysteresis = <2000>; 5376 type = "passive"; 5377 }; 5378 5379 cpu7_top_crit: cpu_crit { 5380 temperature = <110000>; 5381 hysteresis = <1000>; 5382 type = "critical"; 5383 }; 5384 }; 5385 5386 cooling-maps { 5387 map0 { 5388 trip = <&cpu7_top_alert0>; 5389 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5390 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5391 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5392 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5393 }; 5394 map1 { 5395 trip = <&cpu7_top_alert1>; 5396 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5397 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5398 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5399 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5400 }; 5401 }; 5402 }; 5403 5404 cpu4-bottom-thermal { 5405 polling-delay-passive = <250>; 5406 polling-delay = <1000>; 5407 5408 thermal-sensors = <&tsens0 11>; 5409 5410 trips { 5411 cpu4_bottom_alert0: trip-point0 { 5412 temperature = <90000>; 5413 hysteresis = <2000>; 5414 type = "passive"; 5415 }; 5416 5417 cpu4_bottom_alert1: trip-point1 { 5418 temperature = <95000>; 5419 hysteresis = <2000>; 5420 type = "passive"; 5421 }; 5422 5423 cpu4_bottom_crit: cpu_crit { 5424 temperature = <110000>; 5425 hysteresis = <1000>; 5426 type = "critical"; 5427 }; 5428 }; 5429 5430 cooling-maps { 5431 map0 { 5432 trip = <&cpu4_bottom_alert0>; 5433 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5434 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5435 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5436 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5437 }; 5438 map1 { 5439 trip = <&cpu4_bottom_alert1>; 5440 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5441 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5442 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5443 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5444 }; 5445 }; 5446 }; 5447 5448 cpu5-bottom-thermal { 5449 polling-delay-passive = <250>; 5450 polling-delay = <1000>; 5451 5452 thermal-sensors = <&tsens0 12>; 5453 5454 trips { 5455 cpu5_bottom_alert0: trip-point0 { 5456 temperature = <90000>; 5457 hysteresis = <2000>; 5458 type = "passive"; 5459 }; 5460 5461 cpu5_bottom_alert1: trip-point1 { 5462 temperature = <95000>; 5463 hysteresis = <2000>; 5464 type = "passive"; 5465 }; 5466 5467 cpu5_bottom_crit: cpu_crit { 5468 temperature = <110000>; 5469 hysteresis = <1000>; 5470 type = "critical"; 5471 }; 5472 }; 5473 5474 cooling-maps { 5475 map0 { 5476 trip = <&cpu5_bottom_alert0>; 5477 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5478 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5479 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5480 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5481 }; 5482 map1 { 5483 trip = <&cpu5_bottom_alert1>; 5484 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5485 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5486 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5487 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5488 }; 5489 }; 5490 }; 5491 5492 cpu6-bottom-thermal { 5493 polling-delay-passive = <250>; 5494 polling-delay = <1000>; 5495 5496 thermal-sensors = <&tsens0 13>; 5497 5498 trips { 5499 cpu6_bottom_alert0: trip-point0 { 5500 temperature = <90000>; 5501 hysteresis = <2000>; 5502 type = "passive"; 5503 }; 5504 5505 cpu6_bottom_alert1: trip-point1 { 5506 temperature = <95000>; 5507 hysteresis = <2000>; 5508 type = "passive"; 5509 }; 5510 5511 cpu6_bottom_crit: cpu_crit { 5512 temperature = <110000>; 5513 hysteresis = <1000>; 5514 type = "critical"; 5515 }; 5516 }; 5517 5518 cooling-maps { 5519 map0 { 5520 trip = <&cpu6_bottom_alert0>; 5521 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5522 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5523 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5524 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5525 }; 5526 map1 { 5527 trip = <&cpu6_bottom_alert1>; 5528 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5529 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5530 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5531 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5532 }; 5533 }; 5534 }; 5535 5536 cpu7-bottom-thermal { 5537 polling-delay-passive = <250>; 5538 polling-delay = <1000>; 5539 5540 thermal-sensors = <&tsens0 14>; 5541 5542 trips { 5543 cpu7_bottom_alert0: trip-point0 { 5544 temperature = <90000>; 5545 hysteresis = <2000>; 5546 type = "passive"; 5547 }; 5548 5549 cpu7_bottom_alert1: trip-point1 { 5550 temperature = <95000>; 5551 hysteresis = <2000>; 5552 type = "passive"; 5553 }; 5554 5555 cpu7_bottom_crit: cpu_crit { 5556 temperature = <110000>; 5557 hysteresis = <1000>; 5558 type = "critical"; 5559 }; 5560 }; 5561 5562 cooling-maps { 5563 map0 { 5564 trip = <&cpu7_bottom_alert0>; 5565 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5566 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5567 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5568 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5569 }; 5570 map1 { 5571 trip = <&cpu7_bottom_alert1>; 5572 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5573 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5574 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5575 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5576 }; 5577 }; 5578 }; 5579 5580 aoss0-thermal { 5581 polling-delay-passive = <250>; 5582 polling-delay = <1000>; 5583 5584 thermal-sensors = <&tsens0 0>; 5585 5586 trips { 5587 aoss0_alert0: trip-point0 { 5588 temperature = <90000>; 5589 hysteresis = <2000>; 5590 type = "hot"; 5591 }; 5592 }; 5593 }; 5594 5595 cluster0-thermal { 5596 polling-delay-passive = <250>; 5597 polling-delay = <1000>; 5598 5599 thermal-sensors = <&tsens0 5>; 5600 5601 trips { 5602 cluster0_alert0: trip-point0 { 5603 temperature = <90000>; 5604 hysteresis = <2000>; 5605 type = "hot"; 5606 }; 5607 cluster0_crit: cluster0_crit { 5608 temperature = <110000>; 5609 hysteresis = <2000>; 5610 type = "critical"; 5611 }; 5612 }; 5613 }; 5614 5615 cluster1-thermal { 5616 polling-delay-passive = <250>; 5617 polling-delay = <1000>; 5618 5619 thermal-sensors = <&tsens0 6>; 5620 5621 trips { 5622 cluster1_alert0: trip-point0 { 5623 temperature = <90000>; 5624 hysteresis = <2000>; 5625 type = "hot"; 5626 }; 5627 cluster1_crit: cluster1_crit { 5628 temperature = <110000>; 5629 hysteresis = <2000>; 5630 type = "critical"; 5631 }; 5632 }; 5633 }; 5634 5635 gpu-top-thermal { 5636 polling-delay-passive = <250>; 5637 polling-delay = <1000>; 5638 5639 thermal-sensors = <&tsens0 15>; 5640 5641 trips { 5642 gpu1_alert0: trip-point0 { 5643 temperature = <90000>; 5644 hysteresis = <2000>; 5645 type = "hot"; 5646 }; 5647 }; 5648 }; 5649 5650 aoss1-thermal { 5651 polling-delay-passive = <250>; 5652 polling-delay = <1000>; 5653 5654 thermal-sensors = <&tsens1 0>; 5655 5656 trips { 5657 aoss1_alert0: trip-point0 { 5658 temperature = <90000>; 5659 hysteresis = <2000>; 5660 type = "hot"; 5661 }; 5662 }; 5663 }; 5664 5665 wlan-thermal { 5666 polling-delay-passive = <250>; 5667 polling-delay = <1000>; 5668 5669 thermal-sensors = <&tsens1 1>; 5670 5671 trips { 5672 wlan_alert0: trip-point0 { 5673 temperature = <90000>; 5674 hysteresis = <2000>; 5675 type = "hot"; 5676 }; 5677 }; 5678 }; 5679 5680 video-thermal { 5681 polling-delay-passive = <250>; 5682 polling-delay = <1000>; 5683 5684 thermal-sensors = <&tsens1 2>; 5685 5686 trips { 5687 video_alert0: trip-point0 { 5688 temperature = <90000>; 5689 hysteresis = <2000>; 5690 type = "hot"; 5691 }; 5692 }; 5693 }; 5694 5695 mem-thermal { 5696 polling-delay-passive = <250>; 5697 polling-delay = <1000>; 5698 5699 thermal-sensors = <&tsens1 3>; 5700 5701 trips { 5702 mem_alert0: trip-point0 { 5703 temperature = <90000>; 5704 hysteresis = <2000>; 5705 type = "hot"; 5706 }; 5707 }; 5708 }; 5709 5710 q6-hvx-thermal { 5711 polling-delay-passive = <250>; 5712 polling-delay = <1000>; 5713 5714 thermal-sensors = <&tsens1 4>; 5715 5716 trips { 5717 q6_hvx_alert0: trip-point0 { 5718 temperature = <90000>; 5719 hysteresis = <2000>; 5720 type = "hot"; 5721 }; 5722 }; 5723 }; 5724 5725 camera-thermal { 5726 polling-delay-passive = <250>; 5727 polling-delay = <1000>; 5728 5729 thermal-sensors = <&tsens1 5>; 5730 5731 trips { 5732 camera_alert0: trip-point0 { 5733 temperature = <90000>; 5734 hysteresis = <2000>; 5735 type = "hot"; 5736 }; 5737 }; 5738 }; 5739 5740 compute-thermal { 5741 polling-delay-passive = <250>; 5742 polling-delay = <1000>; 5743 5744 thermal-sensors = <&tsens1 6>; 5745 5746 trips { 5747 compute_alert0: trip-point0 { 5748 temperature = <90000>; 5749 hysteresis = <2000>; 5750 type = "hot"; 5751 }; 5752 }; 5753 }; 5754 5755 npu-thermal { 5756 polling-delay-passive = <250>; 5757 polling-delay = <1000>; 5758 5759 thermal-sensors = <&tsens1 7>; 5760 5761 trips { 5762 npu_alert0: trip-point0 { 5763 temperature = <90000>; 5764 hysteresis = <2000>; 5765 type = "hot"; 5766 }; 5767 }; 5768 }; 5769 5770 gpu-bottom-thermal { 5771 polling-delay-passive = <250>; 5772 polling-delay = <1000>; 5773 5774 thermal-sensors = <&tsens1 8>; 5775 5776 trips { 5777 gpu2_alert0: trip-point0 { 5778 temperature = <90000>; 5779 hysteresis = <2000>; 5780 type = "hot"; 5781 }; 5782 }; 5783 }; 5784 }; 5785}; 5786